drivers/video/meson/meson_vclk.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Amlogic Meson Video Processing Unit driver
   4  *
   5  * Copyright (c) 2018 BayLibre, SAS.
   6  * Author: Neil Armstrong <narmstrong@baylibre.com>
   7  */
   8
   9 #include <common.h>
  10 #include <dm.h>
  11 #include <edid.h>
  12 #include "meson_vpu.h"
  13 #include <linux/iopoll.h>
  14 #include <linux/math64.h>
  15
  16 #define writel_bits(mask, val, addr) \
  17         writel((readl(addr) & ~(mask)) | (val), addr)
  18
  19 enum {
  20         MESON_VCLK_TARGET_CVBS = 0,
  21         MESON_VCLK_TARGET_HDMI = 1,
  22         MESON_VCLK_TARGET_DMT = 2,
  23 };
  24
  25 /* HHI Registers */
  26 #define HHI_VID_PLL_CLK_DIV     0x1a0 /* 0x68 offset in data sheet */
  27 #define VID_PLL_EN              BIT(19)
  28 #define VID_PLL_BYPASS          BIT(18)
  29 #define VID_PLL_PRESET          BIT(15)
  30 #define HHI_VIID_CLK_DIV        0x128 /* 0x4a offset in data sheet */
  31 #define VCLK2_DIV_MASK          0xff
  32 #define VCLK2_DIV_EN            BIT(16)
  33 #define VCLK2_DIV_RESET         BIT(17)
  34 #define CTS_VDAC_SEL_MASK       (0xf << 28)
  35 #define CTS_VDAC_SEL_SHIFT      28
  36 #define HHI_VIID_CLK_CNTL       0x12c /* 0x4b offset in data sheet */
  37 #define VCLK2_EN                BIT(19)
  38 #define VCLK2_SEL_MASK          (0x7 << 16)
  39 #define VCLK2_SEL_SHIFT         16
  40 #define VCLK2_SOFT_RESET        BIT(15)
  41 #define VCLK2_DIV1_EN           BIT(0)
  42 #define HHI_VID_CLK_DIV         0x164 /* 0x59 offset in data sheet */
  43 #define VCLK_DIV_MASK           0xff
  44 #define VCLK_DIV_EN             BIT(16)
  45 #define VCLK_DIV_RESET          BIT(17)
  46 #define CTS_ENCP_SEL_MASK       (0xf << 24)
  47 #define CTS_ENCP_SEL_SHIFT      24
  48 #define CTS_ENCI_SEL_MASK       (0xf << 28)
  49 #define CTS_ENCI_SEL_SHIFT      28
  50 #define HHI_VID_CLK_CNTL        0x17c /* 0x5f offset in data sheet */
  51 #define VCLK_EN                 BIT(19)
  52 #define VCLK_SEL_MASK           (0x7 << 16)
  53 #define VCLK_SEL_SHIFT          16
  54 #define VCLK_SOFT_RESET         BIT(15)
  55 #define VCLK_DIV1_EN            BIT(0)
  56 #define VCLK_DIV2_EN            BIT(1)
  57 #define VCLK_DIV4_EN            BIT(2)
  58 #define VCLK_DIV6_EN            BIT(3)
  59 #define VCLK_DIV12_EN           BIT(4)
  60 #define HHI_VID_CLK_CNTL2       0x194 /* 0x65 offset in data sheet */
  61 #define CTS_ENCI_EN             BIT(0)
  62 #define CTS_ENCP_EN             BIT(2)
  63 #define CTS_VDAC_EN             BIT(4)
  64 #define HDMI_TX_PIXEL_EN        BIT(5)
  65 #define HHI_HDMI_CLK_CNTL       0x1cc /* 0x73 offset in data sheet */
  66 #define HDMI_TX_PIXEL_SEL_MASK  (0xf << 16)
  67 #define HDMI_TX_PIXEL_SEL_SHIFT 16
  68 #define CTS_HDMI_SYS_SEL_MASK   (0x7 << 9)
  69 #define CTS_HDMI_SYS_DIV_MASK   (0x7f)
  70 #define CTS_HDMI_SYS_EN         BIT(8)
  71
  72 #define HHI_HDMI_PLL_CNTL       0x320 /* 0xc8 offset in data sheet */
  73 #define HHI_HDMI_PLL_CNTL_EN    BIT(30)
  74 #define HHI_HDMI_PLL_CNTL2      0x324 /* 0xc9 offset in data sheet */
  75 #define HHI_HDMI_PLL_CNTL3      0x328 /* 0xca offset in data sheet */
  76 #define HHI_HDMI_PLL_CNTL4      0x32C /* 0xcb offset in data sheet */
  77 #define HHI_HDMI_PLL_CNTL5      0x330 /* 0xcc offset in data sheet */
  78 #define HHI_HDMI_PLL_CNTL6      0x334 /* 0xcd offset in data sheet */
  79 #define HHI_HDMI_PLL_CNTL7      0x338 /* 0xce offset in data sheet */
  80
  81 #define HDMI_PLL_RESET          BIT(28)
  82 #define HDMI_PLL_RESET_G12A     BIT(29)
  83 #define HDMI_PLL_LOCK           BIT(31)
  84 #define HDMI_PLL_LOCK_G12A      (3 << 30)
  85
  86 #define FREQ_1000_1001(_freq)   DIV_ROUND_CLOSEST(_freq * 1000, 1001)
  87
  88 /* VID PLL Dividers */
  89 enum {
  90         VID_PLL_DIV_1 = 0,
  91         VID_PLL_DIV_2,
  92         VID_PLL_DIV_2p5,
  93         VID_PLL_DIV_3,
  94         VID_PLL_DIV_3p5,
  95         VID_PLL_DIV_3p75,
  96         VID_PLL_DIV_4,
  97         VID_PLL_DIV_5,
  98         VID_PLL_DIV_6,
  99         VID_PLL_DIV_6p25,
 100         VID_PLL_DIV_7,
 101         VID_PLL_DIV_7p5,
 102         VID_PLL_DIV_12,
 103         VID_PLL_DIV_14,
 104         VID_PLL_DIV_15,
 105 };
 106
 107 void meson_vid_pll_set(struct meson_vpu_priv *priv, unsigned int div)
 108 {
 109         unsigned int shift_val = 0;
 110         unsigned int shift_sel = 0;
 111
 112         /* Disable vid_pll output clock */
 113         hhi_update_bits(HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0);
 114         hhi_update_bits(HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0);
 115
 116         switch (div) {
 117         case VID_PLL_DIV_2:
 118                 shift_val = 0x0aaa;
 119                 shift_sel = 0;
 120                 break;
 121         case VID_PLL_DIV_2p5:
 122                 shift_val = 0x5294;
 123                 shift_sel = 2;
 124                 break;
 125         case VID_PLL_DIV_3:
 126                 shift_val = 0x0db6;
 127                 shift_sel = 0;
 128                 break;
 129         case VID_PLL_DIV_3p5:
 130                 shift_val = 0x36cc;
 131                 shift_sel = 1;
 132                 break;
 133         case VID_PLL_DIV_3p75:
 134                 shift_val = 0x6666;
 135                 shift_sel = 2;
 136                 break;
 137         case VID_PLL_DIV_4:
 138                 shift_val = 0x0ccc;
 139                 shift_sel = 0;
 140                 break;
 141         case VID_PLL_DIV_5:
 142                 shift_val = 0x739c;
 143                 shift_sel = 2;
 144                 break;
 145         case VID_PLL_DIV_6:
 146                 shift_val = 0x0e38;
 147                 shift_sel = 0;
 148                 break;
 149         case VID_PLL_DIV_6p25:
 150                 shift_val = 0x0000;
 151                 shift_sel = 3;
 152                 break;
 153         case VID_PLL_DIV_7:
 154                 shift_val = 0x3c78;
 155                 shift_sel = 1;
 156                 break;
 157         case VID_PLL_DIV_7p5:
 158                 shift_val = 0x78f0;
 159                 shift_sel = 2;
 160                 break;
 161         case VID_PLL_DIV_12:
 162                 shift_val = 0x0fc0;
 163                 shift_sel = 0;
 164                 break;
 165         case VID_PLL_DIV_14:
 166                 shift_val = 0x3f80;
 167                 shift_sel = 1;
 168                 break;
 169         case VID_PLL_DIV_15:
 170                 shift_val = 0x7f80;
 171                 shift_sel = 2;
 172                 break;
 173         }
 174
 175         if (div == VID_PLL_DIV_1) {
 176                 /* Enable vid_pll bypass to HDMI pll */
 177                 hhi_update_bits(HHI_VID_PLL_CLK_DIV,
 178                                 VID_PLL_BYPASS, VID_PLL_BYPASS);
 179         } else {
 180                 /* Disable Bypass */
 181                 hhi_update_bits(HHI_VID_PLL_CLK_DIV,
 182                                 VID_PLL_BYPASS, 0);
 183                 /* Clear sel */
 184                 hhi_update_bits(HHI_VID_PLL_CLK_DIV,
 185                                 3 << 16, 0);
 186                 hhi_update_bits(HHI_VID_PLL_CLK_DIV,
 187                                 VID_PLL_PRESET, 0);
 188                 hhi_update_bits(HHI_VID_PLL_CLK_DIV,
 189                                 0x7fff, 0);
 190
 191                 /* Setup sel and val */
 192                 hhi_update_bits(HHI_VID_PLL_CLK_DIV,
 193                                 3 << 16, shift_sel << 16);
 194                 hhi_update_bits(HHI_VID_PLL_CLK_DIV,
 195                                 VID_PLL_PRESET, VID_PLL_PRESET);
 196                 hhi_update_bits(HHI_VID_PLL_CLK_DIV,
 197                                 0x7fff, shift_val);
 198
 199                 hhi_update_bits(HHI_VID_PLL_CLK_DIV,
 200                                 VID_PLL_PRESET, 0);
 201         }
 202
 203         /* Enable the vid_pll output clock */
 204         hhi_update_bits(HHI_VID_PLL_CLK_DIV,
 205                         VID_PLL_EN, VID_PLL_EN);
 206 }
 207
 208 /*
 209  * Setup VCLK2 for 27MHz, and enable clocks for ENCI and VDAC
 210  *
 211  * TOFIX: Refactor into table to also handle HDMI frequency and paths
 212  */
 213 static void meson_venci_cvbs_clock_config(struct meson_vpu_priv *priv)
 214 {
 215         unsigned int val;
 216
 217         /* Setup PLL to output 1.485GHz */
 218         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
 219                 hhi_write(HHI_HDMI_PLL_CNTL, 0x5800023d);
 220                 hhi_write(HHI_HDMI_PLL_CNTL2, 0x00404e00);
 221                 hhi_write(HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
 222                 hhi_write(HHI_HDMI_PLL_CNTL4, 0x801da72c);
 223                 hhi_write(HHI_HDMI_PLL_CNTL5, 0x71486980);
 224                 hhi_write(HHI_HDMI_PLL_CNTL6, 0x00000e55);
 225                 hhi_write(HHI_HDMI_PLL_CNTL, 0x4800023d);
 226
 227                 /* Poll for lock bit */
 228                 readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val,
 229                                    (val & HDMI_PLL_LOCK), 10);
 230         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
 231                    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
 232                 hhi_write(HHI_HDMI_PLL_CNTL, 0x4000027b);
 233                 hhi_write(HHI_HDMI_PLL_CNTL2, 0x800cb300);
 234                 hhi_write(HHI_HDMI_PLL_CNTL3, 0xa6212844);
 235                 hhi_write(HHI_HDMI_PLL_CNTL4, 0x0c4d000c);
 236                 hhi_write(HHI_HDMI_PLL_CNTL5, 0x001fa729);
 237                 hhi_write(HHI_HDMI_PLL_CNTL6, 0x01a31500);
 238
 239                 /* Reset PLL */
 240                 hhi_update_bits(HHI_HDMI_PLL_CNTL,
 241                                 HDMI_PLL_RESET, HDMI_PLL_RESET);
 242                 hhi_update_bits(HHI_HDMI_PLL_CNTL,
 243                                 HDMI_PLL_RESET, 0);
 244
 245                 /* Poll for lock bit */
 246                 readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val,
 247                                    (val & HDMI_PLL_LOCK), 10);
 248         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
 249                 hhi_write(HHI_HDMI_PLL_CNTL, 0x1a0504f7);
 250                 hhi_write(HHI_HDMI_PLL_CNTL2, 0x00010000);
 251                 hhi_write(HHI_HDMI_PLL_CNTL3, 0x00000000);
 252                 hhi_write(HHI_HDMI_PLL_CNTL4, 0x6a28dc00);
 253                 hhi_write(HHI_HDMI_PLL_CNTL5, 0x65771290);
 254                 hhi_write(HHI_HDMI_PLL_CNTL6, 0x39272000);
 255                 hhi_write(HHI_HDMI_PLL_CNTL7, 0x56540000);
 256                 hhi_write(HHI_HDMI_PLL_CNTL, 0x3a0504f7);
 257                 hhi_write(HHI_HDMI_PLL_CNTL, 0x1a0504f7);
 258
 259                 /* Poll for lock bit */
 260                 readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val,
 261                         ((val & HDMI_PLL_LOCK_G12A) == HDMI_PLL_LOCK_G12A),
 262                         10);
 263         }
 264
 265         /* Disable VCLK2 */
 266         hhi_update_bits(HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
 267
 268         /* Setup vid_pll to /1 */
 269         meson_vid_pll_set(priv, VID_PLL_DIV_1);
 270
 271         /* Setup the VCLK2 divider value to achieve 27MHz */
 272         hhi_update_bits(HHI_VIID_CLK_DIV,
 273                         VCLK2_DIV_MASK, (55 - 1));
 274
 275         /* select vid_pll for vclk2 */
 276         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
 277                 hhi_update_bits(HHI_VIID_CLK_CNTL,
 278                                 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
 279         else
 280                 hhi_update_bits(HHI_VIID_CLK_CNTL,
 281                                 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT));
 282
 283         /* enable vclk2 gate */
 284         hhi_update_bits(HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
 285
 286         /* select vclk_div1 for enci */
 287         hhi_update_bits(HHI_VID_CLK_DIV,
 288                         CTS_ENCI_SEL_MASK, (8 << CTS_ENCI_SEL_SHIFT));
 289         /* select vclk_div1 for vdac */
 290         hhi_update_bits(HHI_VIID_CLK_DIV,
 291                         CTS_VDAC_SEL_MASK, (8 << CTS_VDAC_SEL_SHIFT));
 292
 293         /* release vclk2_div_reset and enable vclk2_div */
 294         hhi_update_bits(HHI_VIID_CLK_DIV,
 295                         VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
 296
 297         /* enable vclk2_div1 gate */
 298         hhi_update_bits(HHI_VIID_CLK_CNTL,
 299                         VCLK2_DIV1_EN, VCLK2_DIV1_EN);
 300
 301         /* reset vclk2 */
 302         hhi_update_bits(HHI_VIID_CLK_CNTL,
 303                         VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
 304         hhi_update_bits(HHI_VIID_CLK_CNTL,
 305                         VCLK2_SOFT_RESET, 0);
 306
 307         /* enable enci_clk */
 308         hhi_update_bits(HHI_VID_CLK_CNTL2,
 309                         CTS_ENCI_EN, CTS_ENCI_EN);
 310         /* enable vdac_clk */
 311         hhi_update_bits(HHI_VID_CLK_CNTL2,
 312                         CTS_VDAC_EN, CTS_VDAC_EN);
 313 }
 314
 315 enum {
 316 /* PLL  O1 O2 O3 VP DV     EN TX */
 317 /* 4320 /4 /4 /1 /5 /1  => /2 /2 */
 318         MESON_VCLK_HDMI_ENCI_54000 = 0,
 319 /* 4320 /4 /4 /1 /5 /1  => /1 /2 */
 320         MESON_VCLK_HDMI_DDR_54000,
 321 /* 2970 /4 /1 /1 /5 /1  => /1 /2 */
 322         MESON_VCLK_HDMI_DDR_148500,
 323 /* 2970 /2 /2 /2 /5 /1  => /1 /1 */
 324         MESON_VCLK_HDMI_74250,
 325 /* 2970 /1 /2 /2 /5 /1  => /1 /1 */
 326         MESON_VCLK_HDMI_148500,
 327 /* 2970 /1 /1 /1 /5 /2  => /1 /1 */
 328         MESON_VCLK_HDMI_297000,
 329 /* 5940 /1 /1 /2 /5 /1  => /1 /1 */
 330         MESON_VCLK_HDMI_594000
 331 };
 332
 333 struct meson_vclk_params {
 334         unsigned int pixel_freq;
 335         unsigned int pll_base_freq;
 336         unsigned int pll_od1;
 337         unsigned int pll_od2;
 338         unsigned int pll_od3;
 339         unsigned int vid_pll_div;
 340         unsigned int vclk_div;
 341 } params[] = {
 342         [MESON_VCLK_HDMI_ENCI_54000] = {
 343                 .pixel_freq = 54000,
 344                 .pll_base_freq = 4320000,
 345                 .pll_od1 = 4,
 346                 .pll_od2 = 4,
 347                 .pll_od3 = 1,
 348                 .vid_pll_div = VID_PLL_DIV_5,
 349                 .vclk_div = 1,
 350         },
 351         [MESON_VCLK_HDMI_DDR_54000] = {
 352                 .pixel_freq = 54000,
 353                 .pll_base_freq = 4320000,
 354                 .pll_od1 = 4,
 355                 .pll_od2 = 4,
 356                 .pll_od3 = 1,
 357                 .vid_pll_div = VID_PLL_DIV_5,
 358                 .vclk_div = 1,
 359         },
 360         [MESON_VCLK_HDMI_DDR_148500] = {
 361                 .pixel_freq = 148500,
 362                 .pll_base_freq = 2970000,
 363                 .pll_od1 = 4,
 364                 .pll_od2 = 1,
 365                 .pll_od3 = 1,
 366                 .vid_pll_div = VID_PLL_DIV_5,
 367                 .vclk_div = 1,
 368         },
 369         [MESON_VCLK_HDMI_74250] = {
 370                 .pixel_freq = 74250,
 371                 .pll_base_freq = 2970000,
 372                 .pll_od1 = 2,
 373                 .pll_od2 = 2,
 374                 .pll_od3 = 2,
 375                 .vid_pll_div = VID_PLL_DIV_5,
 376                 .vclk_div = 1,
 377         },
 378         [MESON_VCLK_HDMI_148500] = {
 379                 .pixel_freq = 148500,
 380                 .pll_base_freq = 2970000,
 381                 .pll_od1 = 1,
 382                 .pll_od2 = 2,
 383                 .pll_od3 = 2,
 384                 .vid_pll_div = VID_PLL_DIV_5,
 385                 .vclk_div = 1,
 386         },
 387         [MESON_VCLK_HDMI_297000] = {
 388                 .pixel_freq = 297000,
 389                 .pll_base_freq = 5940000,
 390                 .pll_od1 = 2,
 391                 .pll_od2 = 1,
 392                 .pll_od3 = 1,
 393                 .vid_pll_div = VID_PLL_DIV_5,
 394                 .vclk_div = 2,
 395         },
 396         [MESON_VCLK_HDMI_594000] = {
 397                 .pixel_freq = 594000,
 398                 .pll_base_freq = 5940000,
 399                 .pll_od1 = 1,
 400                 .pll_od2 = 1,
 401                 .pll_od3 = 2,
 402                 .vid_pll_div = VID_PLL_DIV_5,
 403                 .vclk_div = 1,
 404         },
 405         { /* sentinel */ },
 406 };
 407
 408 static inline unsigned int pll_od_to_reg(unsigned int od)
 409 {
 410         switch (od) {
 411         case 1:
 412                 return 0;
 413         case 2:
 414                 return 1;
 415         case 4:
 416                 return 2;
 417         case 8:
 418                 return 3;
 419         }
 420
 421         /* Invalid */
 422         return 0;
 423 }
 424
 425 void meson_hdmi_pll_set_params(struct meson_vpu_priv *priv, unsigned int m,
 426                                unsigned int frac, unsigned int od1,
 427                                unsigned int od2, unsigned int od3)
 428 {
 429         unsigned int val;
 430
 431         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
 432                 hhi_write(HHI_HDMI_PLL_CNTL, 0x58000200 | m);
 433                 if (frac)
 434                         hhi_write(HHI_HDMI_PLL_CNTL2,
 435                                   0x00004000 | frac);
 436                 else
 437                         hhi_write(HHI_HDMI_PLL_CNTL2,
 438                                   0x00000000);
 439                 hhi_write(HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
 440                 hhi_write(HHI_HDMI_PLL_CNTL4, 0x801da72c);
 441                 hhi_write(HHI_HDMI_PLL_CNTL5, 0x71486980);
 442                 hhi_write(HHI_HDMI_PLL_CNTL6, 0x00000e55);
 443
 444                 /* Enable and unreset */
 445                 hhi_update_bits(HHI_HDMI_PLL_CNTL,
 446                                 0x7 << 28, 0x4 << 28);
 447
 448                 /* Poll for lock bit */
 449                 readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val,
 450                                    (val & HDMI_PLL_LOCK), 10);
 451         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
 452                    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
 453                 hhi_write(HHI_HDMI_PLL_CNTL, 0x40000200 | m);
 454                 hhi_write(HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac);
 455                 hhi_write(HHI_HDMI_PLL_CNTL3, 0x860f30c4);
 456                 hhi_write(HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
 457                 hhi_write(HHI_HDMI_PLL_CNTL5, 0x001fa729);
 458                 hhi_write(HHI_HDMI_PLL_CNTL6, 0x01a31500);
 459
 460                 /* Reset PLL */
 461                 hhi_update_bits(HHI_HDMI_PLL_CNTL,
 462                                 HDMI_PLL_RESET, HDMI_PLL_RESET);
 463                 hhi_update_bits(HHI_HDMI_PLL_CNTL,
 464                                 HDMI_PLL_RESET, 0);
 465
 466                 /* Poll for lock bit */
 467                 readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val,
 468                                    (val & HDMI_PLL_LOCK), 10);
 469         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
 470                 hhi_write(HHI_HDMI_PLL_CNTL, 0x0b3a0400 | m);
 471
 472                 /* Enable and reset */
 473                 hhi_update_bits(HHI_HDMI_PLL_CNTL, 0x3 << 28, 0x3 << 28);
 474
 475                 hhi_write(HHI_HDMI_PLL_CNTL2, frac);
 476                 hhi_write(HHI_HDMI_PLL_CNTL3, 0x00000000);
 477
 478                 /* G12A HDMI PLL Needs specific parameters for 5.4GHz */
 479                 if (m >= 0xf7) {
 480                         if (frac < 0x10000) {
 481                                 hhi_write(HHI_HDMI_PLL_CNTL4, 0x6a685c00);
 482                                 hhi_write(HHI_HDMI_PLL_CNTL5, 0x11551293);
 483                         } else {
 484                                 hhi_write(HHI_HDMI_PLL_CNTL4, 0xea68dc00);
 485                                 hhi_write(HHI_HDMI_PLL_CNTL5, 0x65771290);
 486                         }
 487                         hhi_write(HHI_HDMI_PLL_CNTL6, 0x39272000);
 488                         hhi_write(HHI_HDMI_PLL_CNTL7, 0x55540000);
 489                 } else {
 490                         hhi_write(HHI_HDMI_PLL_CNTL4, 0x0a691c00);
 491                         hhi_write(HHI_HDMI_PLL_CNTL5, 0x33771290);
 492                         hhi_write(HHI_HDMI_PLL_CNTL6, 0x39270000);
 493                         hhi_write(HHI_HDMI_PLL_CNTL7, 0x50540000);
 494                 }
 495
 496                 do {
 497                         /* Reset PLL */
 498                         hhi_update_bits(HHI_HDMI_PLL_CNTL,
 499                                         HDMI_PLL_RESET_G12A,
 500                                         HDMI_PLL_RESET_G12A);
 501
 502                         /* UN-Reset PLL */
 503                         hhi_update_bits(HHI_HDMI_PLL_CNTL,
 504                                         HDMI_PLL_RESET_G12A, 0);
 505
 506                         /* Poll for lock bits */
 507                         if (!readl_poll_timeout(
 508                                         priv->hhi_base + HHI_HDMI_PLL_CNTL, val,
 509                                         ((val & HDMI_PLL_LOCK_G12A)
 510                                                 == HDMI_PLL_LOCK_G12A), 100))
 511                                 break;
 512                 } while (1);
 513         }
 514
 515         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
 516                 hhi_update_bits(HHI_HDMI_PLL_CNTL2,
 517                                 3 << 16, pll_od_to_reg(od1) << 16);
 518         else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
 519                  meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
 520                 hhi_update_bits(HHI_HDMI_PLL_CNTL3,
 521                                 3 << 21, pll_od_to_reg(od1) << 21);
 522         else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
 523                 hhi_update_bits(HHI_HDMI_PLL_CNTL,
 524                                 3 << 16, pll_od_to_reg(od1) << 16);
 525
 526         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
 527                 hhi_update_bits(HHI_HDMI_PLL_CNTL2,
 528                                 3 << 22, pll_od_to_reg(od2) << 22);
 529         else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
 530                  meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
 531                 hhi_update_bits(HHI_HDMI_PLL_CNTL3,
 532                                 3 << 23, pll_od_to_reg(od2) << 23);
 533         else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
 534                 hhi_update_bits(HHI_HDMI_PLL_CNTL,
 535                                 3 << 18, pll_od_to_reg(od2) << 18);
 536
 537         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
 538                 hhi_update_bits(HHI_HDMI_PLL_CNTL2,
 539                                 3 << 18, pll_od_to_reg(od3) << 18);
 540         else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
 541                  meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
 542                 hhi_update_bits(HHI_HDMI_PLL_CNTL3,
 543                                 3 << 19, pll_od_to_reg(od3) << 19);
 544         else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
 545                 hhi_update_bits(HHI_HDMI_PLL_CNTL,
 546                                 3 << 20, pll_od_to_reg(od3) << 20);
 547 }
 548
 549 #define XTAL_FREQ 24000
 550
 551 static unsigned int meson_hdmi_pll_get_m(struct meson_vpu_priv *priv,
 552                                          unsigned int pll_freq)
 553 {
 554         /* The GXBB PLL has a /2 pre-multiplier */
 555         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
 556                 pll_freq /= 2;
 557
 558         return pll_freq / XTAL_FREQ;
 559 }
 560
 561 #define HDMI_FRAC_MAX_GXBB      4096
 562 #define HDMI_FRAC_MAX_GXL       1024
 563 #define HDMI_FRAC_MAX_G12A      131072
 564
 565 static unsigned int meson_hdmi_pll_get_frac(struct meson_vpu_priv *priv,
 566                                             unsigned int m,
 567                                             unsigned int pll_freq)
 568 {
 569         unsigned int parent_freq = XTAL_FREQ;
 570         unsigned int frac_max = HDMI_FRAC_MAX_GXL;
 571         unsigned int frac_m;
 572         unsigned int frac;
 573
 574         /* The GXBB PLL has a /2 pre-multiplier and a larger FRAC width */
 575         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
 576                 frac_max = HDMI_FRAC_MAX_GXBB;
 577                 parent_freq *= 2;
 578         }
 579
 580         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
 581                 frac_max = HDMI_FRAC_MAX_G12A;
 582
 583         /* We can have a perfect match !*/
 584         if (pll_freq / m == parent_freq &&
 585             pll_freq % m == 0)
 586                 return 0;
 587
 588         frac = div_u64((u64)pll_freq * (u64)frac_max, parent_freq);
 589         frac_m = m * frac_max;
 590         if (frac_m > frac)
 591                 return frac_max;
 592         frac -= frac_m;
 593
 594         return min((u16)frac, (u16)(frac_max - 1));
 595 }
 596
 597 static bool meson_hdmi_pll_validate_params(struct meson_vpu_priv *priv,
 598                                            unsigned int m,
 599                                            unsigned int frac)
 600 {
 601         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
 602                 /* Empiric supported min/max dividers */
 603                 if (m < 53 || m > 123)
 604                         return false;
 605                 if (frac >= HDMI_FRAC_MAX_GXBB)
 606                         return false;
 607         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
 608                    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
 609                 /* Empiric supported min/max dividers */
 610                 if (m < 106 || m > 247)
 611                         return false;
 612                 if (frac >= HDMI_FRAC_MAX_GXL)
 613                         return false;
 614         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
 615                 /* Empiric supported min/max dividers */
 616                 if (m < 106 || m > 247)
 617                         return false;
 618                 if (frac >= HDMI_FRAC_MAX_G12A)
 619                         return false;
 620         }
 621
 622         return true;
 623 }
 624
 625 static bool meson_hdmi_pll_find_params(struct meson_vpu_priv *priv,
 626                                        unsigned int freq,
 627                                        unsigned int *m,
 628                                        unsigned int *frac,
 629                                        unsigned int *od)
 630 {
 631         /* Cycle from /16 to /2 */
 632         for (*od = 16 ; *od > 1 ; *od >>= 1) {
 633                 *m = meson_hdmi_pll_get_m(priv, freq * *od);
 634                 if (!*m)
 635                         continue;
 636                 *frac = meson_hdmi_pll_get_frac(priv, *m, freq * *od);
 637
 638                 debug("PLL params for %dkHz: m=%x frac=%x od=%d\n",
 639                       freq, *m, *frac, *od);
 640
 641                 if (meson_hdmi_pll_validate_params(priv, *m, *frac))
 642                         return true;
 643         }
 644
 645         return false;
 646 }
 647
 648 /* pll_freq is the frequency after the OD dividers */
 649 bool meson_vclk_dmt_supported_freq(struct meson_vpu_priv *priv,
 650                                    unsigned int freq)
 651 {
 652         unsigned int od, m, frac;
 653
 654         /* In DMT mode, path after PLL is always /10 */
 655         freq *= 10;
 656
 657         if (meson_hdmi_pll_find_params(priv, freq, &m, &frac, &od))
 658                 return true;
 659
 660         return false;
 661 }
 662
 663 /* pll_freq is the frequency after the OD dividers */
 664 static void meson_hdmi_pll_generic_set(struct meson_vpu_priv *priv,
 665                                        unsigned int pll_freq)
 666 {
 667         unsigned int od, m, frac, od1, od2, od3;
 668
 669         if (meson_hdmi_pll_find_params(priv, pll_freq, &m, &frac, &od)) {
 670                 od3 = 1;
 671                 if (od < 4) {
 672                         od1 = 2;
 673                         od2 = 1;
 674                 } else {
 675                         od2 = od / 4;
 676                         od1 = od / od2;
 677                 }
 678
 679                 debug("PLL params for %dkHz: m=%x frac=%x od=%d/%d/%d\n",
 680                       pll_freq, m, frac, od1, od2, od3);
 681
 682                 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
 683
 684                 return;
 685         }
 686
 687         printf("Fatal, unable to find parameters for PLL freq %d\n",
 688                pll_freq);
 689 }
 690
 691 static void
 692 meson_vclk_set(struct meson_vpu_priv *priv, unsigned int pll_base_freq,
 693                unsigned int od1, unsigned int od2, unsigned int od3,
 694                unsigned int vid_pll_div, unsigned int vclk_div,
 695                unsigned int hdmi_tx_div, unsigned int venc_div,
 696                bool hdmi_use_enci, bool vic_alternate_clock)
 697 {
 698         unsigned int m = 0, frac = 0;
 699
 700         /* Set HDMI-TX sys clock */
 701         hhi_update_bits(HHI_HDMI_CLK_CNTL,
 702                         CTS_HDMI_SYS_SEL_MASK, 0);
 703         hhi_update_bits(HHI_HDMI_CLK_CNTL,
 704                         CTS_HDMI_SYS_DIV_MASK, 0);
 705         hhi_update_bits(HHI_HDMI_CLK_CNTL,
 706                         CTS_HDMI_SYS_EN, CTS_HDMI_SYS_EN);
 707
 708         /* Set HDMI PLL rate */
 709         if (!od1 && !od2 && !od3) {
 710                 meson_hdmi_pll_generic_set(priv, pll_base_freq);
 711         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
 712                 switch (pll_base_freq) {
 713                 case 2970000:
 714                         m = 0x3d;
 715                         frac = vic_alternate_clock ? 0xd02 : 0xe00;
 716                         break;
 717                 case 4320000:
 718                         m = vic_alternate_clock ? 0x59 : 0x5a;
 719                         frac = vic_alternate_clock ? 0xe8f : 0;
 720                         break;
 721                 case 5940000:
 722                         m = 0x7b;
 723                         frac = vic_alternate_clock ? 0xa05 : 0xc00;
 724                         break;
 725                 }
 726
 727                 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
 728         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
 729                    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
 730                 switch (pll_base_freq) {
 731                 case 2970000:
 732                         m = 0x7b;
 733                         frac = vic_alternate_clock ? 0x281 : 0x300;
 734                         break;
 735                 case 4320000:
 736                         m = vic_alternate_clock ? 0xb3 : 0xb4;
 737                         frac = vic_alternate_clock ? 0x347 : 0;
 738                         break;
 739                 case 5940000:
 740                         m = 0xf7;
 741                         frac = vic_alternate_clock ? 0x102 : 0x200;
 742                         break;
 743                 }
 744
 745                 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
 746         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
 747                 switch (pll_base_freq) {
 748                 case 2970000:
 749                         m = 0x7b;
 750                         frac = vic_alternate_clock ? 0x140b4 : 0x18000;
 751                         break;
 752                 case 4320000:
 753                         m = vic_alternate_clock ? 0xb3 : 0xb4;
 754                         frac = vic_alternate_clock ? 0x1a3ee : 0;
 755                         break;
 756                 case 5940000:
 757                         m = 0xf7;
 758                         frac = vic_alternate_clock ? 0x8148 : 0x10000;
 759                         break;
 760                 }
 761
 762                 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
 763         }
 764
 765         /* Setup vid_pll divider */
 766         meson_vid_pll_set(priv, vid_pll_div);
 767
 768         /* Set VCLK div */
 769         hhi_update_bits(HHI_VID_CLK_CNTL,
 770                         VCLK_SEL_MASK, 0);
 771         hhi_update_bits(HHI_VID_CLK_DIV,
 772                         VCLK_DIV_MASK, vclk_div - 1);
 773
 774         /* Set HDMI-TX source */
 775         switch (hdmi_tx_div) {
 776         case 1:
 777                 /* enable vclk_div1 gate */
 778                 hhi_update_bits(HHI_VID_CLK_CNTL,
 779                                 VCLK_DIV1_EN, VCLK_DIV1_EN);
 780
 781                 /* select vclk_div1 for HDMI-TX */
 782                 hhi_update_bits(HHI_HDMI_CLK_CNTL,
 783                                 HDMI_TX_PIXEL_SEL_MASK, 0);
 784                 break;
 785         case 2:
 786                 /* enable vclk_div2 gate */
 787                 hhi_update_bits(HHI_VID_CLK_CNTL,
 788                                 VCLK_DIV2_EN, VCLK_DIV2_EN);
 789
 790                 /* select vclk_div2 for HDMI-TX */
 791                 hhi_update_bits(HHI_HDMI_CLK_CNTL,
 792                                 HDMI_TX_PIXEL_SEL_MASK,
 793                                 1 << HDMI_TX_PIXEL_SEL_SHIFT);
 794                 break;
 795         case 4:
 796                 /* enable vclk_div4 gate */
 797                 hhi_update_bits(HHI_VID_CLK_CNTL,
 798                                 VCLK_DIV4_EN, VCLK_DIV4_EN);
 799
 800                 /* select vclk_div4 for HDMI-TX */
 801                 hhi_update_bits(HHI_HDMI_CLK_CNTL,
 802                                 HDMI_TX_PIXEL_SEL_MASK,
 803                                 2 << HDMI_TX_PIXEL_SEL_SHIFT);
 804                 break;
 805         case 6:
 806                 /* enable vclk_div6 gate */
 807                 hhi_update_bits(HHI_VID_CLK_CNTL,
 808                                 VCLK_DIV6_EN, VCLK_DIV6_EN);
 809
 810                 /* select vclk_div6 for HDMI-TX */
 811                 hhi_update_bits(HHI_HDMI_CLK_CNTL,
 812                                 HDMI_TX_PIXEL_SEL_MASK,
 813                                 3 << HDMI_TX_PIXEL_SEL_SHIFT);
 814                 break;
 815         case 12:
 816                 /* enable vclk_div12 gate */
 817                 hhi_update_bits(HHI_VID_CLK_CNTL,
 818                                 VCLK_DIV12_EN, VCLK_DIV12_EN);
 819
 820                 /* select vclk_div12 for HDMI-TX */
 821                 hhi_update_bits(HHI_HDMI_CLK_CNTL,
 822                                 HDMI_TX_PIXEL_SEL_MASK,
 823                                 4 << HDMI_TX_PIXEL_SEL_SHIFT);
 824                 break;
 825         }
 826         hhi_update_bits(HHI_VID_CLK_CNTL2,
 827                         HDMI_TX_PIXEL_EN, HDMI_TX_PIXEL_EN);
 828
 829         /* Set ENCI/ENCP Source */
 830         switch (venc_div) {
 831         case 1:
 832                 /* enable vclk_div1 gate */
 833                 hhi_update_bits(HHI_VID_CLK_CNTL,
 834                                 VCLK_DIV1_EN, VCLK_DIV1_EN);
 835
 836                 if (hdmi_use_enci)
 837                         /* select vclk_div1 for enci */
 838                         hhi_update_bits(HHI_VID_CLK_DIV,
 839                                         CTS_ENCI_SEL_MASK, 0);
 840                 else
 841                         /* select vclk_div1 for encp */
 842                         hhi_update_bits(HHI_VID_CLK_DIV,
 843                                         CTS_ENCP_SEL_MASK, 0);
 844                 break;
 845         case 2:
 846                 /* enable vclk_div2 gate */
 847                 hhi_update_bits(HHI_VID_CLK_CNTL,
 848                                 VCLK_DIV2_EN, VCLK_DIV2_EN);
 849
 850                 if (hdmi_use_enci)
 851                         /* select vclk_div2 for enci */
 852                         hhi_update_bits(HHI_VID_CLK_DIV,
 853                                         CTS_ENCI_SEL_MASK,
 854                                         1 << CTS_ENCI_SEL_SHIFT);
 855                 else
 856                         /* select vclk_div2 for encp */
 857                         hhi_update_bits(HHI_VID_CLK_DIV,
 858                                         CTS_ENCP_SEL_MASK,
 859                                         1 << CTS_ENCP_SEL_SHIFT);
 860                 break;
 861         case 4:
 862                 /* enable vclk_div4 gate */
 863                 hhi_update_bits(HHI_VID_CLK_CNTL,
 864                                 VCLK_DIV4_EN, VCLK_DIV4_EN);
 865
 866                 if (hdmi_use_enci)
 867                         /* select vclk_div4 for enci */
 868                         hhi_update_bits(HHI_VID_CLK_DIV,
 869                                         CTS_ENCI_SEL_MASK,
 870                                         2 << CTS_ENCI_SEL_SHIFT);
 871                 else
 872                         /* select vclk_div4 for encp */
 873                         hhi_update_bits(HHI_VID_CLK_DIV,
 874                                         CTS_ENCP_SEL_MASK,
 875                                         2 << CTS_ENCP_SEL_SHIFT);
 876                 break;
 877         case 6:
 878                 /* enable vclk_div6 gate */
 879                 hhi_update_bits(HHI_VID_CLK_CNTL,
 880                                 VCLK_DIV6_EN, VCLK_DIV6_EN);
 881
 882                 if (hdmi_use_enci)
 883                         /* select vclk_div6 for enci */
 884                         hhi_update_bits(HHI_VID_CLK_DIV,
 885                                         CTS_ENCI_SEL_MASK,
 886                                         3 << CTS_ENCI_SEL_SHIFT);
 887                 else
 888                         /* select vclk_div6 for encp */
 889                         hhi_update_bits(HHI_VID_CLK_DIV,
 890                                         CTS_ENCP_SEL_MASK,
 891                                         3 << CTS_ENCP_SEL_SHIFT);
 892                 break;
 893         case 12:
 894                 /* enable vclk_div12 gate */
 895                 hhi_update_bits(HHI_VID_CLK_CNTL,
 896                                 VCLK_DIV12_EN, VCLK_DIV12_EN);
 897
 898                 if (hdmi_use_enci)
 899                         /* select vclk_div12 for enci */
 900                         hhi_update_bits(HHI_VID_CLK_DIV,
 901                                         CTS_ENCI_SEL_MASK,
 902                                         4 << CTS_ENCI_SEL_SHIFT);
 903                 else
 904                         /* select vclk_div12 for encp */
 905                         hhi_update_bits(HHI_VID_CLK_DIV,
 906                                         CTS_ENCP_SEL_MASK,
 907                                         4 << CTS_ENCP_SEL_SHIFT);
 908                 break;
 909         }
 910
 911         if (hdmi_use_enci)
 912                 /* Enable ENCI clock gate */
 913                 hhi_update_bits(HHI_VID_CLK_CNTL2,
 914                                 CTS_ENCI_EN, CTS_ENCI_EN);
 915         else
 916                 /* Enable ENCP clock gate */
 917                 hhi_update_bits(HHI_VID_CLK_CNTL2,
 918                                 CTS_ENCP_EN, CTS_ENCP_EN);
 919
 920         hhi_update_bits(HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN);
 921 }
 922
 923 static void meson_vclk_setup(struct meson_vpu_priv *priv, unsigned int target,
 924                              unsigned int vclk_freq, unsigned int venc_freq,
 925                              unsigned int dac_freq, bool hdmi_use_enci)
 926 {
 927         bool vic_alternate_clock = false;
 928         unsigned int freq;
 929         unsigned int hdmi_tx_div;
 930         unsigned int venc_div;
 931
 932         if (target == MESON_VCLK_TARGET_CVBS) {
 933                 meson_venci_cvbs_clock_config(priv);
 934                 return;
 935         } else if (target == MESON_VCLK_TARGET_DMT) {
 936                 /* The DMT clock path is fixed after the PLL:
 937                  * - automatic PLL freq + OD management
 938                  * - vid_pll_div = VID_PLL_DIV_5
 939                  * - vclk_div = 2
 940                  * - hdmi_tx_div = 1
 941                  * - venc_div = 1
 942                  * - encp encoder
 943                  */
 944                 meson_vclk_set(priv, vclk_freq * 10, 0, 0, 0,
 945                                VID_PLL_DIV_5, 2, 1, 1, false, false);
 946                 return;
 947         }
 948
 949         hdmi_tx_div = vclk_freq / dac_freq;
 950
 951         if (hdmi_tx_div == 0) {
 952                 printf("Fatal Error, invalid HDMI-TX freq %d\n",
 953                        dac_freq);
 954                 return;
 955         }
 956
 957         venc_div = vclk_freq / venc_freq;
 958
 959         if (venc_div == 0) {
 960                 printf("Fatal Error, invalid HDMI venc freq %d\n",
 961                        venc_freq);
 962                 return;
 963         }
 964
 965         for (freq = 0 ; params[freq].pixel_freq ; ++freq) {
 966                 if (vclk_freq == params[freq].pixel_freq ||
 967                     vclk_freq == FREQ_1000_1001(params[freq].pixel_freq)) {
 968                         if (vclk_freq != params[freq].pixel_freq)
 969                                 vic_alternate_clock = true;
 970                         else
 971                                 vic_alternate_clock = false;
 972
 973                         if (freq == MESON_VCLK_HDMI_ENCI_54000 &&
 974                             !hdmi_use_enci)
 975                                 continue;
 976
 977                         if (freq == MESON_VCLK_HDMI_DDR_54000 &&
 978                             hdmi_use_enci)
 979                                 continue;
 980
 981                         if (freq == MESON_VCLK_HDMI_DDR_148500 &&
 982                             dac_freq == vclk_freq)
 983                                 continue;
 984
 985                         if (freq == MESON_VCLK_HDMI_148500 &&
 986                             dac_freq != vclk_freq)
 987                                 continue;
 988                         break;
 989                 }
 990         }
 991
 992         if (!params[freq].pixel_freq) {
 993                 pr_err("Fatal Error, invalid HDMI vclk freq %d\n", vclk_freq);
 994                 return;
 995         }
 996
 997         meson_vclk_set(priv, params[freq].pll_base_freq,
 998                        params[freq].pll_od1, params[freq].pll_od2,
 999                        params[freq].pll_od3, params[freq].vid_pll_div,
1000                        params[freq].vclk_div, hdmi_tx_div, venc_div,
1001                        hdmi_use_enci, vic_alternate_clock);
1002 }
1003
1004 void meson_vpu_setup_vclk(struct udevice *dev,
1005                           const struct display_timing *mode, bool is_cvbs)
1006 {
1007         struct meson_vpu_priv *priv = dev_get_priv(dev);
1008         unsigned int vclk_freq;
1009
1010         if (is_cvbs)
1011                 return meson_vclk_setup(priv, MESON_VCLK_TARGET_CVBS,
1012                                         0, 0, 0, false);
1013
1014         vclk_freq = mode->pixelclock.typ / 1000;
1015
1016         return meson_vclk_setup(priv, MESON_VCLK_TARGET_DMT,
1017                                 vclk_freq, vclk_freq, vclk_freq, false);
1018 }