1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016-2018 ARM Ltd.
4 * Author: Liviu Dudau <liviu.dudau@foss.arm.com>
18 #include <fdt_support.h>
20 #include <dm/device_compat.h>
21 #include <linux/sizes.h>
23 #define MALIDP_CORE_ID 0x0018
24 #define MALIDP_REG_BG_COLOR 0x0044
25 #define MALIDP_LAYER_LV1 0x0100
26 #define MALIDP_DC_STATUS 0xc000
27 #define MALIDP_DC_CONTROL 0xc010
28 #define MALIDP_DC_CFG_VALID 0xc014
30 /* offsets inside the modesetting register block */
31 #define MALIDP_H_INTERVALS 0x0000
32 #define MALIDP_V_INTERVALS 0x0004
33 #define MALIDP_SYNC_CONTROL 0x0008
34 #define MALIDP_HV_ACTIVESIZE 0x000c
35 #define MALIDP_OUTPUT_DEPTH 0x001c
37 /* offsets inside the layer register block */
38 #define MALIDP_LAYER_FORMAT 0x0000
39 #define MALIDP_LAYER_CONTROL 0x0004
40 #define MALIDP_LAYER_IN_SIZE 0x000c
41 #define MALIDP_LAYER_CMP_SIZE 0x0010
42 #define MALIDP_LAYER_STRIDE 0x0018
43 #define MALIDP_LAYER_PTR_LOW 0x0024
44 #define MALIDP_LAYER_PTR_HIGH 0x0028
46 /* offsets inside the IRQ control blocks */
47 #define MALIDP_REG_MASKIRQ 0x0008
48 #define MALIDP_REG_CLEARIRQ 0x000c
54 #define M10BITS 0x03ff
55 #define M12BITS 0x0fff
56 #define M13BITS 0x1fff
57 #define M16BITS 0xffff
58 #define M17BITS 0x1ffff
60 #define MALIDP_H_FRONTPORCH(x) (((x) & M12BITS) << 0)
61 #define MALIDP_H_BACKPORCH(x) (((x) & M10BITS) << 16)
62 #define MALIDP_V_FRONTPORCH(x) (((x) & M12BITS) << 0)
63 #define MALIDP_V_BACKPORCH(x) (((x) & M8BITS) << 16)
64 #define MALIDP_H_SYNCWIDTH(x) (((x) & M10BITS) << 0)
65 #define MALIDP_V_SYNCWIDTH(x) (((x) & M8BITS) << 16)
66 #define MALIDP_H_ACTIVE(x) (((x) & M13BITS) << 0)
67 #define MALIDP_V_ACTIVE(x) (((x) & M13BITS) << 16)
69 #define MALIDP_CMP_V_SIZE(x) (((x) & M13BITS) << 16)
70 #define MALIDP_CMP_H_SIZE(x) (((x) & M13BITS) << 0)
72 #define MALIDP_IN_V_SIZE(x) (((x) & M13BITS) << 16)
73 #define MALIDP_IN_H_SIZE(x) (((x) & M13BITS) << 0)
75 #define MALIDP_DC_CM_CONTROL(x) ((x) & M1BITS) << 16, 1 << 16
76 #define MALIDP_DC_STATUS_GET_CM(reg) (((reg) >> 16) & M1BITS)
78 #define MALIDP_FORMAT_ARGB8888 0x08
79 #define MALIDP_DEFAULT_BG_R 0x0
80 #define MALIDP_DEFAULT_BG_G 0x0
81 #define MALIDP_DEFAULT_BG_B 0x0
83 #define MALIDP_PRODUCT_ID(core_id) ((u32)(core_id) >> 16)
85 #define MALIDP500 0x500
87 DECLARE_GLOBAL_DATA_PTR;
90 phys_addr_t base_addr;
91 phys_addr_t dc_status_addr;
92 phys_addr_t dc_control_addr;
93 phys_addr_t cval_addr;
94 struct udevice *display; /* display device attached */
97 u16 modeset_regs_offset;
99 u8 clear_irq; /* offset for IRQ clear register */
102 static const struct video_ops malidp_ops = {
105 static int malidp_get_hwid(phys_addr_t base_addr)
110 * reading from the old CORE_ID offset will always
111 * return 0x5000000 on DP500
113 hwid = readl(base_addr + MALIDP_CORE_ID);
114 if (MALIDP_PRODUCT_ID(hwid) == MALIDP500)
116 /* otherwise try the other gen CORE_ID offset */
117 hwid = readl(base_addr + MALIDP_DC_STATUS + MALIDP_CORE_ID);
123 * wait for config mode bit setup to be acted upon by the hardware
125 static int malidp_wait_configdone(struct malidp_priv *malidp)
127 u32 status, tries = 300;
130 status = readl(malidp->dc_status_addr);
131 if ((status >> malidp->config_bit_shift) & 1)
143 * signal the hardware to enter configuration mode
145 static int malidp_enter_config(struct malidp_priv *malidp)
147 setbits_le32(malidp->dc_control_addr, 1 << malidp->config_bit_shift);
148 return malidp_wait_configdone(malidp);
152 * signal the hardware to exit configuration mode
154 static int malidp_leave_config(struct malidp_priv *malidp)
156 clrbits_le32(malidp->dc_control_addr, 1 << malidp->config_bit_shift);
157 return malidp_wait_configdone(malidp);
160 static void malidp_setup_timings(struct malidp_priv *malidp,
161 struct display_timing *timings)
163 u32 val = MALIDP_H_SYNCWIDTH(timings->hsync_len.typ) |
164 MALIDP_V_SYNCWIDTH(timings->vsync_len.typ);
165 writel(val, malidp->base_addr + malidp->modeset_regs_offset +
166 MALIDP_SYNC_CONTROL);
167 val = MALIDP_H_BACKPORCH(timings->hback_porch.typ) |
168 MALIDP_H_FRONTPORCH(timings->hfront_porch.typ);
169 writel(val, malidp->base_addr + malidp->modeset_regs_offset +
171 val = MALIDP_V_BACKPORCH(timings->vback_porch.typ) |
172 MALIDP_V_FRONTPORCH(timings->vfront_porch.typ);
173 writel(val, malidp->base_addr + malidp->modeset_regs_offset +
175 val = MALIDP_H_ACTIVE(timings->hactive.typ) |
176 MALIDP_V_ACTIVE(timings->vactive.typ);
177 writel(val, malidp->base_addr + malidp->modeset_regs_offset +
178 MALIDP_HV_ACTIVESIZE);
179 /* default output bit-depth per colour is 8 bits */
180 writel(0x080808, malidp->base_addr + malidp->modeset_regs_offset +
181 MALIDP_OUTPUT_DEPTH);
184 static int malidp_setup_mode(struct malidp_priv *malidp,
185 struct display_timing *timings)
189 if (clk_set_rate(&malidp->pxlclk, timings->pixelclock.typ) == 0)
192 malidp_setup_timings(malidp, timings);
194 err = display_enable(malidp->display, 8, timings);
196 printf("display_enable failed with %d\n", err);
201 static void malidp_setup_layer(struct malidp_priv *malidp,
202 struct display_timing *timings,
203 u32 layer_offset, phys_addr_t fb_addr)
207 /* setup the base layer's pixel format to A8R8G8B8 */
208 writel(MALIDP_FORMAT_ARGB8888, malidp->base_addr + layer_offset +
209 MALIDP_LAYER_FORMAT);
210 /* setup layer composition size */
211 val = MALIDP_CMP_V_SIZE(timings->vactive.typ) |
212 MALIDP_CMP_H_SIZE(timings->hactive.typ);
213 writel(val, malidp->base_addr + layer_offset +
214 MALIDP_LAYER_CMP_SIZE);
215 /* setup layer input size */
216 val = MALIDP_IN_V_SIZE(timings->vactive.typ) |
217 MALIDP_IN_H_SIZE(timings->hactive.typ);
218 writel(val, malidp->base_addr + layer_offset + MALIDP_LAYER_IN_SIZE);
219 /* setup layer stride in bytes */
220 writel(timings->hactive.typ << 2, malidp->base_addr + layer_offset +
221 MALIDP_LAYER_STRIDE);
222 /* set framebuffer address */
223 writel(lower_32_bits(fb_addr), malidp->base_addr + layer_offset +
224 MALIDP_LAYER_PTR_LOW);
225 writel(upper_32_bits(fb_addr), malidp->base_addr + layer_offset +
226 MALIDP_LAYER_PTR_HIGH);
228 setbits_le32(malidp->base_addr + layer_offset +
229 MALIDP_LAYER_CONTROL, 1);
232 static void malidp_set_configvalid(struct malidp_priv *malidp)
234 setbits_le32(malidp->cval_addr, 1);
237 static int malidp_update_timings_from_edid(struct udevice *dev,
238 struct display_timing *timings)
240 #ifdef CONFIG_DISPLAY
241 struct malidp_priv *priv = dev_get_priv(dev);
242 struct udevice *disp_dev;
245 err = uclass_first_device(UCLASS_DISPLAY, &disp_dev);
249 priv->display = disp_dev;
251 err = display_read_timing(disp_dev, timings);
259 static int malidp_probe(struct udevice *dev)
261 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
262 struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
263 ofnode framebuffer = ofnode_find_subnode(dev_ofnode(dev), "framebuffer");
264 struct malidp_priv *priv = dev_get_priv(dev);
265 struct display_timing timings;
266 phys_addr_t fb_base, fb_size;
271 if (!ofnode_valid(framebuffer))
274 err = clk_get_by_name(dev, "pxlclk", &priv->pxlclk);
276 dev_err(dev, "failed to get pixel clock\n");
279 err = clk_get_by_name(dev, "aclk", &priv->aclk);
281 dev_err(dev, "failed to get AXI clock\n");
285 err = ofnode_decode_display_timing(dev_ofnode(dev), 1, &timings);
287 dev_err(dev, "failed to get any display timings\n");
291 err = malidp_update_timings_from_edid(dev, &timings);
293 printf("malidp_update_timings_from_edid failed: %d\n", err);
297 fb_base = ofnode_get_addr_size(framebuffer, "reg", &fb_size);
298 if (fb_base != FDT_ADDR_T_NONE) {
299 uc_plat->base = fb_base;
300 uc_plat->size = fb_size;
302 printf("cannot get address size for framebuffer\n");
305 err = ofnode_read_u32(framebuffer, "width", &value);
308 uc_priv->xsize = (ushort)value;
310 err = ofnode_read_u32(framebuffer, "height", &value);
313 uc_priv->ysize = (ushort)value;
315 format = ofnode_read_string(framebuffer, "format");
319 } else if (!strncmp(format, "a8r8g8b8", 8)) {
320 uc_priv->bpix = VIDEO_BPP32;
324 priv->base_addr = (phys_addr_t)dev_read_addr(dev);
326 clk_enable(&priv->pxlclk);
327 clk_enable(&priv->aclk);
329 value = malidp_get_hwid(priv->base_addr);
330 printf("Display: Arm Mali DP%3x r%dp%d\n", MALIDP_PRODUCT_ID(value),
331 (value >> 12) & 0xf, (value >> 8) & 0xf);
333 if (MALIDP_PRODUCT_ID(value) == MALIDP500) {
334 /* DP500 is special */
335 priv->modeset_regs_offset = 0x28;
336 priv->dc_status_addr = priv->base_addr;
337 priv->dc_control_addr = priv->base_addr + 0xc;
338 priv->cval_addr = priv->base_addr + 0xf00;
339 priv->config_bit_shift = 17;
342 priv->modeset_regs_offset = 0x30;
343 priv->dc_status_addr = priv->base_addr + MALIDP_DC_STATUS;
344 priv->dc_control_addr = priv->base_addr + MALIDP_DC_CONTROL;
345 priv->cval_addr = priv->base_addr + MALIDP_DC_CFG_VALID;
346 priv->config_bit_shift = 16;
347 priv->clear_irq = MALIDP_REG_CLEARIRQ;
350 /* enter config mode */
351 err = malidp_enter_config(priv);
355 /* disable interrupts */
356 writel(0, priv->dc_status_addr + MALIDP_REG_MASKIRQ);
357 writel(0xffffffff, priv->dc_status_addr + priv->clear_irq);
359 err = malidp_setup_mode(priv, &timings);
363 malidp_setup_layer(priv, &timings, MALIDP_LAYER_LV1,
364 (phys_addr_t)uc_plat->base);
366 err = malidp_leave_config(priv);
370 malidp_set_configvalid(priv);
375 clk_free(&priv->aclk);
377 clk_free(&priv->pxlclk);
382 static int malidp_bind(struct udevice *dev)
384 struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
386 /* choose max possible size: 2K x 2K, XRGB888 framebuffer */
387 uc_plat->size = 4 * 2048 * 2048;
392 static const struct udevice_id malidp_ids[] = {
393 { .compatible = "arm,mali-dp500" },
394 { .compatible = "arm,mali-dp550" },
395 { .compatible = "arm,mali-dp650" },
399 U_BOOT_DRIVER(mali_dp) = {
402 .of_match = malidp_ids,
404 .probe = malidp_probe,
405 .priv_auto_alloc_size = sizeof(struct malidp_priv),