1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016 Google, Inc
14 #include <asm/intel_regs.h>
18 #include <asm/arch/pch.h>
19 #include <asm/arch/sandybridge.h>
20 #include <linux/delay.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 struct gt_powermeter {
29 /* These are magic values - unfortunately the meaning is unknown */
30 static const struct gt_powermeter snb_pm_gt1[] = {
31 { 0xa200, 0xcc000000 },
32 { 0xa204, 0x07000040 },
33 { 0xa208, 0x0000fe00 },
34 { 0xa20c, 0x00000000 },
35 { 0xa210, 0x17000000 },
36 { 0xa214, 0x00000021 },
37 { 0xa218, 0x0817fe19 },
38 { 0xa21c, 0x00000000 },
39 { 0xa220, 0x00000000 },
40 { 0xa224, 0xcc000000 },
41 { 0xa228, 0x07000040 },
42 { 0xa22c, 0x0000fe00 },
43 { 0xa230, 0x00000000 },
44 { 0xa234, 0x17000000 },
45 { 0xa238, 0x00000021 },
46 { 0xa23c, 0x0817fe19 },
47 { 0xa240, 0x00000000 },
48 { 0xa244, 0x00000000 },
49 { 0xa248, 0x8000421e },
53 static const struct gt_powermeter snb_pm_gt2[] = {
54 { 0xa200, 0x330000a6 },
55 { 0xa204, 0x402d0031 },
56 { 0xa208, 0x00165f83 },
57 { 0xa20c, 0xf1000000 },
58 { 0xa210, 0x00000000 },
59 { 0xa214, 0x00160016 },
60 { 0xa218, 0x002a002b },
61 { 0xa21c, 0x00000000 },
62 { 0xa220, 0x00000000 },
63 { 0xa224, 0x330000a6 },
64 { 0xa228, 0x402d0031 },
65 { 0xa22c, 0x00165f83 },
66 { 0xa230, 0xf1000000 },
67 { 0xa234, 0x00000000 },
68 { 0xa238, 0x00160016 },
69 { 0xa23c, 0x002a002b },
70 { 0xa240, 0x00000000 },
71 { 0xa244, 0x00000000 },
72 { 0xa248, 0x8000421e },
76 static const struct gt_powermeter ivb_pm_gt1[] = {
77 { 0xa800, 0x00000000 },
78 { 0xa804, 0x00021c00 },
79 { 0xa808, 0x00000403 },
80 { 0xa80c, 0x02001700 },
81 { 0xa810, 0x05000200 },
82 { 0xa814, 0x00000000 },
83 { 0xa818, 0x00690500 },
84 { 0xa81c, 0x0000007f },
85 { 0xa820, 0x01002501 },
86 { 0xa824, 0x00000300 },
87 { 0xa828, 0x01000331 },
88 { 0xa82c, 0x0000000c },
89 { 0xa830, 0x00010016 },
90 { 0xa834, 0x01100101 },
91 { 0xa838, 0x00010103 },
92 { 0xa83c, 0x00041300 },
93 { 0xa840, 0x00000b30 },
94 { 0xa844, 0x00000000 },
95 { 0xa848, 0x7f000000 },
96 { 0xa84c, 0x05000008 },
97 { 0xa850, 0x00000001 },
98 { 0xa854, 0x00000004 },
99 { 0xa858, 0x00000007 },
100 { 0xa85c, 0x00000000 },
101 { 0xa860, 0x00010000 },
102 { 0xa248, 0x0000221e },
103 { 0xa900, 0x00000000 },
104 { 0xa904, 0x00001c00 },
105 { 0xa908, 0x00000000 },
106 { 0xa90c, 0x06000000 },
107 { 0xa910, 0x09000200 },
108 { 0xa914, 0x00000000 },
109 { 0xa918, 0x00590000 },
110 { 0xa91c, 0x00000000 },
111 { 0xa920, 0x04002501 },
112 { 0xa924, 0x00000100 },
113 { 0xa928, 0x03000410 },
114 { 0xa92c, 0x00000000 },
115 { 0xa930, 0x00020000 },
116 { 0xa934, 0x02070106 },
117 { 0xa938, 0x00010100 },
118 { 0xa93c, 0x00401c00 },
119 { 0xa940, 0x00000000 },
120 { 0xa944, 0x00000000 },
121 { 0xa948, 0x10000e00 },
122 { 0xa94c, 0x02000004 },
123 { 0xa950, 0x00000001 },
124 { 0xa954, 0x00000004 },
125 { 0xa960, 0x00060000 },
126 { 0xaa3c, 0x00001c00 },
127 { 0xaa54, 0x00000004 },
128 { 0xaa60, 0x00060000 },
132 static const struct gt_powermeter ivb_pm_gt2_17w[] = {
133 { 0xa800, 0x20000000 },
134 { 0xa804, 0x000e3800 },
135 { 0xa808, 0x00000806 },
136 { 0xa80c, 0x0c002f00 },
137 { 0xa810, 0x0c000800 },
138 { 0xa814, 0x00000000 },
139 { 0xa818, 0x00d20d00 },
140 { 0xa81c, 0x000000ff },
141 { 0xa820, 0x03004b02 },
142 { 0xa824, 0x00000600 },
143 { 0xa828, 0x07000773 },
144 { 0xa82c, 0x00000000 },
145 { 0xa830, 0x00020032 },
146 { 0xa834, 0x1520040d },
147 { 0xa838, 0x00020105 },
148 { 0xa83c, 0x00083700 },
149 { 0xa840, 0x000016ff },
150 { 0xa844, 0x00000000 },
151 { 0xa848, 0xff000000 },
152 { 0xa84c, 0x0a000010 },
153 { 0xa850, 0x00000002 },
154 { 0xa854, 0x00000008 },
155 { 0xa858, 0x0000000f },
156 { 0xa85c, 0x00000000 },
157 { 0xa860, 0x00020000 },
158 { 0xa248, 0x0000221e },
159 { 0xa900, 0x00000000 },
160 { 0xa904, 0x00003800 },
161 { 0xa908, 0x00000000 },
162 { 0xa90c, 0x0c000000 },
163 { 0xa910, 0x12000800 },
164 { 0xa914, 0x00000000 },
165 { 0xa918, 0x00b20000 },
166 { 0xa91c, 0x00000000 },
167 { 0xa920, 0x08004b02 },
168 { 0xa924, 0x00000300 },
169 { 0xa928, 0x01000820 },
170 { 0xa92c, 0x00000000 },
171 { 0xa930, 0x00030000 },
172 { 0xa934, 0x15150406 },
173 { 0xa938, 0x00020300 },
174 { 0xa93c, 0x00903900 },
175 { 0xa940, 0x00000000 },
176 { 0xa944, 0x00000000 },
177 { 0xa948, 0x20001b00 },
178 { 0xa94c, 0x0a000010 },
179 { 0xa950, 0x00000000 },
180 { 0xa954, 0x00000008 },
181 { 0xa960, 0x00110000 },
182 { 0xaa3c, 0x00003900 },
183 { 0xaa54, 0x00000008 },
184 { 0xaa60, 0x00110000 },
188 static const struct gt_powermeter ivb_pm_gt2_35w[] = {
189 { 0xa800, 0x00000000 },
190 { 0xa804, 0x00030400 },
191 { 0xa808, 0x00000806 },
192 { 0xa80c, 0x0c002f00 },
193 { 0xa810, 0x0c000300 },
194 { 0xa814, 0x00000000 },
195 { 0xa818, 0x00d20d00 },
196 { 0xa81c, 0x000000ff },
197 { 0xa820, 0x03004b02 },
198 { 0xa824, 0x00000600 },
199 { 0xa828, 0x07000773 },
200 { 0xa82c, 0x00000000 },
201 { 0xa830, 0x00020032 },
202 { 0xa834, 0x1520040d },
203 { 0xa838, 0x00020105 },
204 { 0xa83c, 0x00083700 },
205 { 0xa840, 0x000016ff },
206 { 0xa844, 0x00000000 },
207 { 0xa848, 0xff000000 },
208 { 0xa84c, 0x0a000010 },
209 { 0xa850, 0x00000001 },
210 { 0xa854, 0x00000008 },
211 { 0xa858, 0x00000008 },
212 { 0xa85c, 0x00000000 },
213 { 0xa860, 0x00020000 },
214 { 0xa248, 0x0000221e },
215 { 0xa900, 0x00000000 },
216 { 0xa904, 0x00003800 },
217 { 0xa908, 0x00000000 },
218 { 0xa90c, 0x0c000000 },
219 { 0xa910, 0x12000800 },
220 { 0xa914, 0x00000000 },
221 { 0xa918, 0x00b20000 },
222 { 0xa91c, 0x00000000 },
223 { 0xa920, 0x08004b02 },
224 { 0xa924, 0x00000300 },
225 { 0xa928, 0x01000820 },
226 { 0xa92c, 0x00000000 },
227 { 0xa930, 0x00030000 },
228 { 0xa934, 0x15150406 },
229 { 0xa938, 0x00020300 },
230 { 0xa93c, 0x00903900 },
231 { 0xa940, 0x00000000 },
232 { 0xa944, 0x00000000 },
233 { 0xa948, 0x20001b00 },
234 { 0xa94c, 0x0a000010 },
235 { 0xa950, 0x00000000 },
236 { 0xa954, 0x00000008 },
237 { 0xa960, 0x00110000 },
238 { 0xaa3c, 0x00003900 },
239 { 0xaa54, 0x00000008 },
240 { 0xaa60, 0x00110000 },
244 static inline u32 gtt_read(void *bar, u32 reg)
246 return readl(bar + reg);
249 static inline void gtt_write(void *bar, u32 reg, u32 data)
251 writel(data, bar + reg);
254 static void gtt_write_powermeter(void *bar, const struct gt_powermeter *pm)
256 for (; pm && pm->reg; pm++)
257 gtt_write(bar, pm->reg, pm->value);
260 #define GTT_RETRY 1000
261 static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value)
263 unsigned try = GTT_RETRY;
267 data = gtt_read(bar, reg);
268 if ((data & mask) == value)
273 printf("GT init timeout\n");
277 static int gma_pm_init_pre_vbios(void *gtt_bar, int rev)
281 debug("GT Power Management Init, silicon = %#x\n", rev);
283 if (rev < IVB_STEP_C0) {
284 /* 1: Enable force wake */
285 gtt_write(gtt_bar, 0xa18c, 0x00000001);
286 gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0));
288 gtt_write(gtt_bar, 0xa180, 1 << 5);
289 gtt_write(gtt_bar, 0xa188, 0xffff0001);
290 gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0));
293 if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
294 /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
295 reg32 = gtt_read(gtt_bar, 0x42004);
296 reg32 |= (1 << 14) | (1 << 15);
297 gtt_write(gtt_bar, 0x42004, reg32);
300 if (rev >= IVB_STEP_A0) {
301 /* Display Reset Acknowledge Settings */
302 reg32 = gtt_read(gtt_bar, 0x45010);
303 reg32 |= (1 << 1) | (1 << 0);
304 gtt_write(gtt_bar, 0x45010, reg32);
307 /* 2: Get GT SKU from GTT+0x911c[13] */
308 reg32 = gtt_read(gtt_bar, 0x911c);
309 if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {
310 if (reg32 & (1 << 13)) {
311 debug("SNB GT1 Power Meter Weights\n");
312 gtt_write_powermeter(gtt_bar, snb_pm_gt1);
314 debug("SNB GT2 Power Meter Weights\n");
315 gtt_write_powermeter(gtt_bar, snb_pm_gt2);
318 u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf;
320 if (reg32 & (1 << 13)) {
322 debug("IVB GT1 Power Meter Weights\n");
323 gtt_write_powermeter(gtt_bar, ivb_pm_gt1);
326 u32 tdp = readl(MCHBAR_REG(0x5930)) & 0x7fff;
331 debug("IVB GT2 17W Power Meter Weights\n");
332 gtt_write_powermeter(gtt_bar, ivb_pm_gt2_17w);
333 } else if ((tdp >= 25) && (tdp <= 35)) {
335 debug("IVB GT2 25W-35W Power Meter Weights\n");
336 gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
339 debug("IVB GT2 35W Power Meter Weights\n");
340 gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
345 /* 3: Gear ratio map */
346 gtt_write(gtt_bar, 0xa004, 0x00000010);
349 gtt_write(gtt_bar, 0xa000, 0x00070020);
351 /* 5: Dynamic EU trip control */
352 gtt_write(gtt_bar, 0xa080, 0x00000004);
355 reg32 = gtt_read(gtt_bar, 0xa180);
356 reg32 |= (1 << 26) | (1 << 31);
357 /* (bit 20=1 for SNB step D1+ / IVB A0+) */
358 if (rev >= SNB_STEP_D1)
360 gtt_write(gtt_bar, 0xa180, reg32);
362 /* 6a: for SnB step D2+ only */
363 if (((rev & BASE_REV_MASK) == BASE_REV_SNB) &&
364 (rev >= SNB_STEP_D2)) {
365 reg32 = gtt_read(gtt_bar, 0x9400);
367 gtt_write(gtt_bar, 0x9400, reg32);
369 reg32 = gtt_read(gtt_bar, 0x941c);
372 gtt_write(gtt_bar, 0x941c, reg32);
373 gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1));
376 if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
377 reg32 = gtt_read(gtt_bar, 0x907c);
379 gtt_write(gtt_bar, 0x907c, reg32);
381 /* 6b: Clocking reset controls */
382 gtt_write(gtt_bar, 0x9424, 0x00000001);
384 /* 6b: Clocking reset controls */
385 gtt_write(gtt_bar, 0x9424, 0x00000000);
389 if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) {
390 gtt_write(gtt_bar, 0x138128, 0x00000029); /* Mailbox Data */
391 /* Mailbox Cmd for RC6 VID */
392 gtt_write(gtt_bar, 0x138124, 0x80000004);
393 if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31)))
394 gtt_write(gtt_bar, 0x138124, 0x8000000a);
395 gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31));
399 gtt_write(gtt_bar, 0xa090, 0x00000000); /* RC Control */
400 gtt_write(gtt_bar, 0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
401 gtt_write(gtt_bar, 0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
402 gtt_write(gtt_bar, 0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
403 gtt_write(gtt_bar, 0xa0a8, 0x0001e848); /* RC Evaluation Interval */
404 gtt_write(gtt_bar, 0xa0ac, 0x00000019); /* RC Idle Hysteresis */
407 gtt_write(gtt_bar, 0x2054, 0x0000000a); /* Render Idle Max Count */
408 gtt_write(gtt_bar, 0x12054, 0x0000000a); /* Video Idle Max Count */
409 gtt_write(gtt_bar, 0x22054, 0x0000000a); /* Blitter Idle Max Count */
412 gtt_write(gtt_bar, 0xa0b0, 0x00000000); /* Unblock Ack to Busy */
413 gtt_write(gtt_bar, 0xa0b4, 0x000003e8); /* RC1e Threshold */
414 gtt_write(gtt_bar, 0xa0b8, 0x0000c350); /* RC6 Threshold */
415 gtt_write(gtt_bar, 0xa0bc, 0x000186a0); /* RC6p Threshold */
416 gtt_write(gtt_bar, 0xa0c0, 0x0000fa00); /* RC6pp Threshold */
419 gtt_write(gtt_bar, 0xa010, 0x000f4240); /* RP Down Timeout */
420 gtt_write(gtt_bar, 0xa014, 0x12060000); /* RP Interrupt Limits */
421 gtt_write(gtt_bar, 0xa02c, 0x00015f90); /* RP Up Threshold */
422 gtt_write(gtt_bar, 0xa030, 0x000186a0); /* RP Down Threshold */
423 gtt_write(gtt_bar, 0xa068, 0x000186a0); /* RP Up EI */
424 gtt_write(gtt_bar, 0xa06c, 0x000493e0); /* RP Down EI */
425 gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */
427 /* 11a: Enable Render Standby (RC6) */
428 if ((rev & BASE_REV_MASK) == BASE_REV_IVB) {
430 * IvyBridge should also support DeepRenderStandby.
432 * Unfortunately it does not work reliably on all SKUs so
433 * disable it here and it can be enabled by the kernel.
435 gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
437 gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
440 /* 12: Normal Frequency Request */
441 /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */
442 reg32 = readl(MCHBAR_REG(0x5998));
446 gtt_write(gtt_bar, 0xa008, reg32);
449 gtt_write(gtt_bar, 0xa024, 0x00000592);
451 /* 14: Enable PM Interrupts */
452 gtt_write(gtt_bar, 0x4402c, 0x03000076);
454 /* Clear 0x6c024 [8:6] */
455 reg32 = gtt_read(gtt_bar, 0x6c024);
456 reg32 &= ~0x000001c0;
457 gtt_write(gtt_bar, 0x6c024, reg32);
462 static int gma_pm_init_post_vbios(struct udevice *dev, int rev, void *gtt_bar)
464 const void *blob = gd->fdt_blob;
465 int node = dev_of_offset(dev);
466 u32 reg32, cycle_delay;
468 debug("GT Power Management Init (post VBIOS)\n");
470 /* 15: Deassert Force Wake */
471 if (rev < IVB_STEP_C0) {
472 gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1);
473 gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0));
475 gtt_write(gtt_bar, 0xa188, 0x1fffe);
476 if (gtt_poll(gtt_bar, 0x130040, (1 << 0), (0 << 0))) {
477 gtt_write(gtt_bar, 0xa188,
478 gtt_read(gtt_bar, 0xa188) | 1);
482 /* 16: SW RC Control */
483 gtt_write(gtt_bar, 0xa094, 0x00060000);
485 /* Setup Digital Port Hotplug */
486 reg32 = gtt_read(gtt_bar, 0xc4030);
490 if (fdtdec_get_int_array(blob, node, "intel,dp_hotplug",
491 dp_hotplug, ARRAY_SIZE(dp_hotplug)))
494 reg32 = (dp_hotplug[0] & 0x7) << 2;
495 reg32 |= (dp_hotplug[0] & 0x7) << 10;
496 reg32 |= (dp_hotplug[0] & 0x7) << 18;
497 gtt_write(gtt_bar, 0xc4030, reg32);
500 /* Setup Panel Power On Delays */
501 reg32 = gtt_read(gtt_bar, 0xc7208);
503 reg32 = (unsigned)fdtdec_get_int(blob, node,
504 "panel-port-select", 0) << 30;
505 reg32 |= fdtdec_get_int(blob, node, "panel-power-up-delay", 0)
507 reg32 |= fdtdec_get_int(blob, node,
508 "panel-power-backlight-on-delay", 0);
509 gtt_write(gtt_bar, 0xc7208, reg32);
512 /* Setup Panel Power Off Delays */
513 reg32 = gtt_read(gtt_bar, 0xc720c);
515 reg32 = fdtdec_get_int(blob, node, "panel-power-down-delay", 0)
517 reg32 |= fdtdec_get_int(blob, node,
518 "panel-power-backlight-off-delay", 0);
519 gtt_write(gtt_bar, 0xc720c, reg32);
522 /* Setup Panel Power Cycle Delay */
523 cycle_delay = fdtdec_get_int(blob, node,
524 "intel,panel-power-cycle-delay", 0);
526 reg32 = gtt_read(gtt_bar, 0xc7210);
528 reg32 |= cycle_delay;
529 gtt_write(gtt_bar, 0xc7210, reg32);
532 /* Enable Backlight if needed */
533 reg32 = fdtdec_get_int(blob, node, "intel,cpu-backlight", 0);
535 gtt_write(gtt_bar, 0x48250, (1 << 31));
536 gtt_write(gtt_bar, 0x48254, reg32);
538 reg32 = fdtdec_get_int(blob, node, "intel,pch-backlight", 0);
540 gtt_write(gtt_bar, 0xc8250, (1 << 31));
541 gtt_write(gtt_bar, 0xc8254, reg32);
548 * Some vga option roms are used for several chipsets but they only have one
549 * PCI ID in their header. If we encounter such an option rom, we need to do
550 * the mapping ourselves.
553 uint32_t board_map_oprom_vendev(uint32_t vendev)
556 case 0x80860102: /* GT1 Desktop */
557 case 0x8086010a: /* GT1 Server */
558 case 0x80860112: /* GT2 Desktop */
559 case 0x80860116: /* GT2 Mobile */
560 case 0x80860122: /* GT2 Desktop >=1.3GHz */
561 case 0x80860126: /* GT2 Mobile >=1.3GHz */
562 case 0x80860156: /* IVB */
563 case 0x80860166: /* IVB */
564 return 0x80860106; /* GT1 Mobile */
570 static int int15_handler(void)
574 debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
576 switch (M.x86.R_AX) {
579 * Set Panel Fitting Hook:
580 * bit 2 = Graphics Stretching
581 * bit 1 = Text Stretching
582 * bit 0 = Centering (do not set with bit1 or bit2)
583 * 0 = video bios default
586 M.x86.R_CL = 0x00; /* Use video bios default */
591 * Boot Display Device Hook:
602 M.x86.R_CX = 0x0000; /* Use video bios default */
607 * Hook to select active LFP configuration:
608 * 00h = No LVDS, VBIOS does not enable LVDS
609 * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
610 * 02h = SVDO-LVDS, LFP driven by SVDO decoder
611 * 03h = eDP, LFP Driven by Int-DisplayPort encoder
614 M.x86.R_CX = 0x0003; /* eDP */
618 switch (M.x86.R_CH) {
632 /* Get SG/Non-SG mode */
638 /* Interrupt was not handled */
639 debug("Unknown INT15 5f70 function: 0x%02x\n",
648 debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
654 static void sandybridge_setup_graphics(struct udevice *dev,
655 struct udevice *video_dev)
661 dm_pci_read_config16(video_dev, PCI_DEVICE_ID, ®16);
663 case 0x0102: /* GT1 Desktop */
664 case 0x0106: /* GT1 Mobile */
665 case 0x010a: /* GT1 Server */
666 case 0x0112: /* GT2 Desktop */
667 case 0x0116: /* GT2 Mobile */
668 case 0x0122: /* GT2 Desktop >=1.3GHz */
669 case 0x0126: /* GT2 Mobile >=1.3GHz */
670 case 0x0156: /* IvyBridge */
671 case 0x0166: /* IvyBridge */
674 debug("Graphics not supported by this CPU/chipset\n");
678 debug("Initialising Graphics\n");
680 /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
681 dm_pci_read_config16(dev, GGC, ®16);
684 /* Program GTT memory by setting GGC[9:8] = 2MB */
687 /* Enable VGA decode */
689 dm_pci_write_config16(dev, GGC, reg16);
691 /* Enable 256MB aperture */
692 dm_pci_read_config8(video_dev, MSAC, ®8);
695 dm_pci_write_config8(video_dev, MSAC, reg8);
697 /* Erratum workarounds */
698 reg32 = readl(MCHBAR_REG(0x5f00));
699 reg32 |= (1 << 9) | (1 << 10);
700 writel(reg32, MCHBAR_REG(0x5f00));
702 /* Enable SA Clock Gating */
703 reg32 = readl(MCHBAR_REG(0x5f00));
704 writel(reg32 | 1, MCHBAR_REG(0x5f00));
706 /* GPU RC6 workaround for sighting 366252 */
707 reg32 = readl(MCHBAR_REG(0x5d14));
709 writel(reg32, MCHBAR_REG(0x5d14));
712 reg32 = readl(MCHBAR_REG(0x6120));
714 writel(reg32, MCHBAR_REG(0x6120));
716 reg32 = readl(MCHBAR_REG(0x5418));
717 reg32 |= (1 << 4) | (1 << 5);
718 writel(reg32, MCHBAR_REG(0x5418));
721 static int gma_func0_init(struct udevice *dev)
723 struct udevice *nbridge;
730 /* Enable PCH Display Port */
731 writew(0x0010, RCB_REG(DISPBDF));
732 setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
734 ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &nbridge);
737 rev = bridge_silicon_revision(nbridge);
738 sandybridge_setup_graphics(nbridge, dev);
740 /* IGD needs to be Bus Master */
741 dm_pci_read_config32(dev, PCI_COMMAND, ®32);
742 reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
743 dm_pci_write_config32(dev, PCI_COMMAND, reg32);
745 /* Use write-combining for the graphics memory, 256MB */
746 base = dm_pci_read_bar32(dev, 2);
747 mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20);
750 gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0);
751 debug("GT bar %p\n", gtt_bar);
752 ret = gma_pm_init_pre_vbios(gtt_bar, rev);
759 static int bd82x6x_video_probe(struct udevice *dev)
764 rev = gma_func0_init(dev);
767 ret = vbe_setup_video(dev, int15_handler);
771 /* Post VBIOS init */
772 gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0);
773 ret = gma_pm_init_post_vbios(dev, rev, gtt_bar);
780 static const struct udevice_id bd82x6x_video_ids[] = {
781 { .compatible = "intel,gma" },
785 U_BOOT_DRIVER(bd82x6x_video) = {
786 .name = "bd82x6x_video",
788 .of_match = bd82x6x_video_ids,
789 .probe = bd82x6x_video_probe,