1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Copyright 2019 Toradex AG
6 * FSL DCU Framebuffer driver
13 #include <fdt_support.h>
14 #include <fsl_dcu_fb.h>
19 #include "videomodes.h"
21 /* Convert the X,Y resolution pair into a single number */
22 #define RESOLUTION(x, y) (((u32)(x) << 16) | (y))
24 #ifdef CONFIG_SYS_FSL_DCU_LE
25 #define dcu_read32 in_le32
26 #define dcu_write32 out_le32
27 #elif defined(CONFIG_SYS_FSL_DCU_BE)
28 #define dcu_read32 in_be32
29 #define dcu_write32 out_be32
32 #define DCU_MODE_BLEND_ITER(x) ((x) << 20)
33 #define DCU_MODE_RASTER_EN (1 << 14)
34 #define DCU_MODE_NORMAL 1
35 #define DCU_MODE_COLORBAR 3
36 #define DCU_BGND_R(x) ((x) << 16)
37 #define DCU_BGND_G(x) ((x) << 8)
38 #define DCU_BGND_B(x) (x)
39 #define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16)
40 #define DCU_DISP_SIZE_DELTA_X(x) (x)
41 #define DCU_HSYN_PARA_BP(x) ((x) << 22)
42 #define DCU_HSYN_PARA_PW(x) ((x) << 11)
43 #define DCU_HSYN_PARA_FP(x) (x)
44 #define DCU_VSYN_PARA_BP(x) ((x) << 22)
45 #define DCU_VSYN_PARA_PW(x) ((x) << 11)
46 #define DCU_VSYN_PARA_FP(x) (x)
47 #define DCU_SYN_POL_INV_PXCK_FALL (1 << 6)
48 #define DCU_SYN_POL_NEG_REMAIN (0 << 5)
49 #define DCU_SYN_POL_INV_VS_LOW (1 << 1)
50 #define DCU_SYN_POL_INV_HS_LOW (1)
51 #define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16)
52 #define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) << 8)
53 #define DCU_THRESHOLD_OUT_BUF_LOW(x) (x)
54 #define DCU_UPDATE_MODE_MODE (1 << 31)
55 #define DCU_UPDATE_MODE_READREG (1 << 30)
57 #define DCU_CTRLDESCLN_1_HEIGHT(x) ((x) << 16)
58 #define DCU_CTRLDESCLN_1_WIDTH(x) (x)
59 #define DCU_CTRLDESCLN_2_POSY(x) ((x) << 16)
60 #define DCU_CTRLDESCLN_2_POSX(x) (x)
61 #define DCU_CTRLDESCLN_4_EN (1 << 31)
62 #define DCU_CTRLDESCLN_4_TILE_EN (1 << 30)
63 #define DCU_CTRLDESCLN_4_DATA_SEL_CLUT (1 << 29)
64 #define DCU_CTRLDESCLN_4_SAFETY_EN (1 << 28)
65 #define DCU_CTRLDESCLN_4_TRANS(x) ((x) << 20)
66 #define DCU_CTRLDESCLN_4_BPP(x) ((x) << 16)
67 #define DCU_CTRLDESCLN_4_RLE_EN (1 << 15)
68 #define DCU_CTRLDESCLN_4_LUOFFS(x) ((x) << 4)
69 #define DCU_CTRLDESCLN_4_BB_ON (1 << 2)
70 #define DCU_CTRLDESCLN_4_AB(x) (x)
71 #define DCU_CTRLDESCLN_5_CKMAX_R(x) ((x) << 16)
72 #define DCU_CTRLDESCLN_5_CKMAX_G(x) ((x) << 8)
73 #define DCU_CTRLDESCLN_5_CKMAX_B(x) (x)
74 #define DCU_CTRLDESCLN_6_CKMIN_R(x) ((x) << 16)
75 #define DCU_CTRLDESCLN_6_CKMIN_G(x) ((x) << 8)
76 #define DCU_CTRLDESCLN_6_CKMIN_B(x) (x)
77 #define DCU_CTRLDESCLN_7_TILE_VER(x) ((x) << 16)
78 #define DCU_CTRLDESCLN_7_TILE_HOR(x) (x)
79 #define DCU_CTRLDESCLN_8_FG_FCOLOR(x) (x)
80 #define DCU_CTRLDESCLN_9_BG_BCOLOR(x) (x)
82 #define BPP_16_RGB565 4
83 #define BPP_24_RGB888 5
84 #define BPP_32_ARGB8888 6
86 DECLARE_GLOBAL_DATA_PTR;
89 * This setting is used for the TWR_LCD_RGB card
91 static struct fb_videomode fsl_dcu_mode_480_272 = {
103 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
104 .vmode = FB_VMODE_NONINTERLACED
108 * This setting is used for Siliconimage SiI9022A HDMI
110 static struct fb_videomode fsl_dcu_cea_mode_640_480 = {
111 .name = "640x480-60",
123 .vmode = FB_VMODE_NONINTERLACED,
126 static struct fb_videomode fsl_dcu_mode_640_480 = {
127 .name = "640x480-60",
139 .vmode = FB_VMODE_NONINTERLACED,
142 static struct fb_videomode fsl_dcu_mode_800_480 = {
143 .name = "800x480-60",
155 .vmode = FB_VMODE_NONINTERLACED,
158 static struct fb_videomode fsl_dcu_mode_1024_600 = {
159 .name = "1024x600-60",
171 .vmode = FB_VMODE_NONINTERLACED,
192 u8 res_064[0x6c-0x64];
193 u32 parr_err_status1;
194 u8 res_070[0x7c-0x70];
195 u32 parr_err_status3;
196 u32 mparr_err_status1;
197 u8 res_084[0x90-0x84];
198 u32 mparr_err_status3;
199 u32 threshold_inp_buf[2];
200 u8 res_09c[0xa0-0x9c];
211 u8 res_0c4[0xcc-0xc8];
214 u8 res_0d4[0x100-0xd4];
221 u8 res_120[0x200-0x120];
222 u32 ctrldescl[DCU_LAYER_MAX_NUM][16];
225 static void reset_total_layers(void)
227 struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
230 for (i = 0; i < DCU_LAYER_MAX_NUM; i++) {
231 dcu_write32(®s->ctrldescl[i][0], 0);
232 dcu_write32(®s->ctrldescl[i][1], 0);
233 dcu_write32(®s->ctrldescl[i][2], 0);
234 dcu_write32(®s->ctrldescl[i][3], 0);
235 dcu_write32(®s->ctrldescl[i][4], 0);
236 dcu_write32(®s->ctrldescl[i][5], 0);
237 dcu_write32(®s->ctrldescl[i][6], 0);
238 dcu_write32(®s->ctrldescl[i][7], 0);
239 dcu_write32(®s->ctrldescl[i][8], 0);
240 dcu_write32(®s->ctrldescl[i][9], 0);
241 dcu_write32(®s->ctrldescl[i][10], 0);
245 static int layer_ctrldesc_init(struct fb_info fbinfo,
246 int index, u32 pixel_format)
248 struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
249 unsigned int bpp = BPP_24_RGB888;
251 dcu_write32(®s->ctrldescl[index][0],
252 DCU_CTRLDESCLN_1_HEIGHT(fbinfo.var.yres) |
253 DCU_CTRLDESCLN_1_WIDTH(fbinfo.var.xres));
255 dcu_write32(®s->ctrldescl[index][1],
256 DCU_CTRLDESCLN_2_POSY(0) |
257 DCU_CTRLDESCLN_2_POSX(0));
259 dcu_write32(®s->ctrldescl[index][2],
260 (unsigned int)fbinfo.screen_base);
262 switch (pixel_format) {
270 bpp = BPP_32_ARGB8888;
273 printf("unsupported color depth: %u\n", pixel_format);
276 dcu_write32(®s->ctrldescl[index][3],
277 DCU_CTRLDESCLN_4_EN |
278 DCU_CTRLDESCLN_4_TRANS(0xff) |
279 DCU_CTRLDESCLN_4_BPP(bpp) |
280 DCU_CTRLDESCLN_4_AB(0));
282 dcu_write32(®s->ctrldescl[index][4],
283 DCU_CTRLDESCLN_5_CKMAX_R(0xff) |
284 DCU_CTRLDESCLN_5_CKMAX_G(0xff) |
285 DCU_CTRLDESCLN_5_CKMAX_B(0xff));
286 dcu_write32(®s->ctrldescl[index][5],
287 DCU_CTRLDESCLN_6_CKMIN_R(0) |
288 DCU_CTRLDESCLN_6_CKMIN_G(0) |
289 DCU_CTRLDESCLN_6_CKMIN_B(0));
291 dcu_write32(®s->ctrldescl[index][6],
292 DCU_CTRLDESCLN_7_TILE_VER(0) |
293 DCU_CTRLDESCLN_7_TILE_HOR(0));
295 dcu_write32(®s->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0));
296 dcu_write32(®s->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0));
301 int fsl_dcu_init(struct fb_info *fbinfo, unsigned int xres,
302 unsigned int yres, unsigned int pixel_format)
304 struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
305 unsigned int div, mode;
307 * When DM_VIDEO is enabled reservation of framebuffer is done
308 * in advance during bind() call.
310 #if !CONFIG_IS_ENABLED(DM_VIDEO)
311 fbinfo->screen_size = fbinfo->var.xres * fbinfo->var.yres *
312 (fbinfo->var.bits_per_pixel / 8);
314 if (fbinfo->screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) {
315 fbinfo->screen_size = 0;
318 /* Reserve framebuffer at the end of memory */
319 gd->fb_base = gd->bd->bi_dram[0].start +
320 gd->bd->bi_dram[0].size - fbinfo->screen_size;
321 fbinfo->screen_base = (char *)gd->fb_base;
323 memset(fbinfo->screen_base, 0, fbinfo->screen_size);
326 reset_total_layers();
328 dcu_write32(®s->disp_size,
329 DCU_DISP_SIZE_DELTA_Y(fbinfo->var.yres) |
330 DCU_DISP_SIZE_DELTA_X(fbinfo->var.xres / 16));
332 dcu_write32(®s->hsyn_para,
333 DCU_HSYN_PARA_BP(fbinfo->var.left_margin) |
334 DCU_HSYN_PARA_PW(fbinfo->var.hsync_len) |
335 DCU_HSYN_PARA_FP(fbinfo->var.right_margin));
337 dcu_write32(®s->vsyn_para,
338 DCU_VSYN_PARA_BP(fbinfo->var.upper_margin) |
339 DCU_VSYN_PARA_PW(fbinfo->var.vsync_len) |
340 DCU_VSYN_PARA_FP(fbinfo->var.lower_margin));
342 dcu_write32(®s->synpol,
343 DCU_SYN_POL_INV_PXCK_FALL |
344 DCU_SYN_POL_NEG_REMAIN |
345 DCU_SYN_POL_INV_VS_LOW |
346 DCU_SYN_POL_INV_HS_LOW);
348 dcu_write32(®s->bgnd,
349 DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0));
351 dcu_write32(®s->mode,
352 DCU_MODE_BLEND_ITER(2) |
355 dcu_write32(®s->threshold,
356 DCU_THRESHOLD_LS_BF_VS(0x3) |
357 DCU_THRESHOLD_OUT_BUF_HIGH(0x78) |
358 DCU_THRESHOLD_OUT_BUF_LOW(0));
360 mode = dcu_read32(®s->mode);
361 dcu_write32(®s->mode, mode | DCU_MODE_NORMAL);
363 layer_ctrldesc_init(*fbinfo, 0, pixel_format);
365 div = dcu_set_pixel_clock(fbinfo->var.pixclock);
366 dcu_write32(®s->div_ratio, (div - 1));
368 dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG);
373 ulong board_get_usable_ram_top(ulong total_size)
375 return gd->ram_top - CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB;
378 int fsl_probe_common(struct fb_info *fbinfo, unsigned int *win_x,
382 unsigned int depth = 0, freq = 0;
384 struct fb_videomode *fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
386 if (!video_get_video_mode(win_x, win_y, &depth, &freq,
390 /* Find the monitor port, which is a required option */
394 if (strncmp(options, "monitor=", 8) != 0)
397 switch (RESOLUTION(*win_x, *win_y)) {
398 case RESOLUTION(480, 272):
399 fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
401 case RESOLUTION(640, 480):
402 if (!strncmp(options, "monitor=hdmi", 12))
403 fsl_dcu_mode_db = &fsl_dcu_cea_mode_640_480;
405 fsl_dcu_mode_db = &fsl_dcu_mode_640_480;
407 case RESOLUTION(800, 480):
408 fsl_dcu_mode_db = &fsl_dcu_mode_800_480;
410 case RESOLUTION(1024, 600):
411 fsl_dcu_mode_db = &fsl_dcu_mode_1024_600;
414 printf("unsupported resolution %ux%u\n",
418 fbinfo->var.xres = fsl_dcu_mode_db->xres;
419 fbinfo->var.yres = fsl_dcu_mode_db->yres;
420 fbinfo->var.bits_per_pixel = 32;
421 fbinfo->var.pixclock = fsl_dcu_mode_db->pixclock;
422 fbinfo->var.left_margin = fsl_dcu_mode_db->left_margin;
423 fbinfo->var.right_margin = fsl_dcu_mode_db->right_margin;
424 fbinfo->var.upper_margin = fsl_dcu_mode_db->upper_margin;
425 fbinfo->var.lower_margin = fsl_dcu_mode_db->lower_margin;
426 fbinfo->var.hsync_len = fsl_dcu_mode_db->hsync_len;
427 fbinfo->var.vsync_len = fsl_dcu_mode_db->vsync_len;
428 fbinfo->var.sync = fsl_dcu_mode_db->sync;
429 fbinfo->var.vmode = fsl_dcu_mode_db->vmode;
430 fbinfo->fix.line_length = fbinfo->var.xres *
431 fbinfo->var.bits_per_pixel / 8;
433 return platform_dcu_init(fbinfo, *win_x, *win_y,
434 options + 8, fsl_dcu_mode_db);
437 #ifndef CONFIG_DM_VIDEO
438 static struct fb_info info;
440 #if defined(CONFIG_OF_BOARD_SETUP)
441 int fsl_dcu_fixedfb_setup(void *blob)
446 start = gd->bd->bi_dram[0].start;
447 size = gd->bd->bi_dram[0].size - info.screen_size;
450 * Align size on section size (1 MiB).
453 ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
455 eprintf("Cannot setup fb: Error reserving memory\n");
463 void *video_hw_init(void)
465 static GraphicDevice ctfb;
467 if (fsl_probe_common(&info, &ctfb.winSizeX, &ctfb.winSizeY) < 0)
470 ctfb.frameAdrs = (unsigned int)info.screen_base;
471 ctfb.plnSizeX = ctfb.winSizeX;
472 ctfb.plnSizeY = ctfb.winSizeY;
475 ctfb.gdfIndex = GDF_32BIT_X888RGB;
477 ctfb.memSize = info.screen_size;
482 #else /* ifndef CONFIG_DM_VIDEO */
484 static int fsl_dcu_video_probe(struct udevice *dev)
486 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
487 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
488 struct fb_info fbinfo = { 0 };
491 u32 fb_start, fb_end;
494 fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
495 fb_end = plat->base + plat->size;
496 fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
498 fbinfo.screen_base = (char *)fb_start;
499 fbinfo.screen_size = plat->size;
501 ret = fsl_probe_common(&fbinfo, &win_x, &win_y);
505 uc_priv->bpix = VIDEO_BPP32;
506 uc_priv->xsize = win_x;
507 uc_priv->ysize = win_y;
509 /* Enable dcache for the frame buffer */
510 mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
512 video_set_flush_dcache(dev, true);
516 static int fsl_dcu_video_bind(struct udevice *dev)
518 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
521 unsigned int depth = 0, freq = 0;
525 ret = video_get_video_mode(&win_x, &win_y, &depth, &freq, &options);
529 plat->size = win_x * win_y * 32;
534 static const struct udevice_id fsl_dcu_video_ids[] = {
535 { .compatible = "fsl,vf610-dcu" },
539 U_BOOT_DRIVER(fsl_dcu_video) = {
540 .name = "fsl_dcu_video",
542 .of_match = fsl_dcu_video_ids,
543 .bind = fsl_dcu_video_bind,
544 .probe = fsl_dcu_video_probe,
545 .flags = DM_FLAG_PRE_RELOC,
547 #endif /* ifndef CONFIG_DM_VIDEO */