1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/drivers/video/mmp/hw/mmp_ctrl.c
4 * Marvell MMP series Display Controller support
6 * Copyright (C) 2012 Marvell Technology Group Ltd.
7 * Authors: Guoqing Li <ligq@marvell.com>
8 * Lisa Du <cldu@marvell.com>
9 * Zhou Zhu <zzhu3@marvell.com>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/kernel.h>
14 #include <linux/errno.h>
15 #include <linux/string.h>
16 #include <linux/interrupt.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/platform_device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/clk.h>
22 #include <linux/err.h>
23 #include <linux/vmalloc.h>
24 #include <linux/uaccess.h>
25 #include <linux/kthread.h>
30 static irqreturn_t ctrl_handle_irq(int irq, void *dev_id)
32 struct mmphw_ctrl *ctrl = (struct mmphw_ctrl *)dev_id;
35 isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR);
36 imask = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA);
39 /* clear clock only */
40 tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR);
42 writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR);
43 } while ((isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR)) & imask);
48 static u32 fmt_to_reg(struct mmp_overlay *overlay, int pix_fmt)
50 u32 rbswap = 0, uvswap = 0, yuvswap = 0,
52 vid = overlay_is_vid(overlay);
57 case PIXFMT_RGB888PACK:
58 case PIXFMT_RGB888UNPACK:
82 case PIXFMT_RGB888PACK:
83 case PIXFMT_BGR888PACK:
86 case PIXFMT_RGB888UNPACK:
87 case PIXFMT_BGR888UNPACK:
114 return (dma_palette(0) | dma_fmt(vid, val) |
115 dma_swaprb(vid, rbswap) | dma_swapuv(vid, uvswap) |
116 dma_swapyuv(vid, yuvswap) | dma_csc(vid, csc_en));
119 static void dmafetch_set_fmt(struct mmp_overlay *overlay)
122 struct mmp_path *path = overlay->path;
123 tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
124 tmp &= ~dma_mask(overlay_is_vid(overlay));
125 tmp |= fmt_to_reg(overlay, overlay->win.pix_fmt);
126 writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
129 static void overlay_set_win(struct mmp_overlay *overlay, struct mmp_win *win)
131 struct lcd_regs *regs = path_regs(overlay->path);
133 /* assert win supported */
134 memcpy(&overlay->win, win, sizeof(struct mmp_win));
136 mutex_lock(&overlay->access_ok);
138 if (overlay_is_vid(overlay)) {
139 writel_relaxed(win->pitch[0], ®s->v_pitch_yc);
140 writel_relaxed(win->pitch[2] << 16 |
141 win->pitch[1], ®s->v_pitch_uv);
143 writel_relaxed((win->ysrc << 16) | win->xsrc, ®s->v_size);
144 writel_relaxed((win->ydst << 16) | win->xdst, ®s->v_size_z);
145 writel_relaxed(win->ypos << 16 | win->xpos, ®s->v_start);
147 writel_relaxed(win->pitch[0], ®s->g_pitch);
149 writel_relaxed((win->ysrc << 16) | win->xsrc, ®s->g_size);
150 writel_relaxed((win->ydst << 16) | win->xdst, ®s->g_size_z);
151 writel_relaxed(win->ypos << 16 | win->xpos, ®s->g_start);
154 dmafetch_set_fmt(overlay);
155 mutex_unlock(&overlay->access_ok);
158 static void dmafetch_onoff(struct mmp_overlay *overlay, int on)
160 u32 mask = overlay_is_vid(overlay) ? CFG_DMA_ENA_MASK :
162 u32 enable = overlay_is_vid(overlay) ? CFG_DMA_ENA(1) : CFG_GRA_ENA(1);
164 struct mmp_path *path = overlay->path;
166 mutex_lock(&overlay->access_ok);
167 tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
169 tmp |= (on ? enable : 0);
170 writel(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
171 mutex_unlock(&overlay->access_ok);
174 static void path_enabledisable(struct mmp_path *path, int on)
177 mutex_lock(&path->access_ok);
178 tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));
180 tmp &= ~SCLK_DISABLE;
183 writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
184 mutex_unlock(&path->access_ok);
187 static void path_onoff(struct mmp_path *path, int on)
189 if (path->status == on) {
190 dev_info(path->dev, "path %s is already %s\n",
191 path->name, stat_name(path->status));
196 path_enabledisable(path, 1);
198 if (path->panel && path->panel->set_onoff)
199 path->panel->set_onoff(path->panel, 1);
201 if (path->panel && path->panel->set_onoff)
202 path->panel->set_onoff(path->panel, 0);
204 path_enabledisable(path, 0);
209 static void overlay_set_onoff(struct mmp_overlay *overlay, int on)
211 if (overlay->status == on) {
212 dev_info(overlay_to_ctrl(overlay)->dev, "overlay %s is already %s\n",
213 overlay->path->name, stat_name(overlay->status));
216 overlay->status = on;
217 dmafetch_onoff(overlay, on);
218 if (overlay->path->ops.check_status(overlay->path)
219 != overlay->path->status)
220 path_onoff(overlay->path, on);
223 static void overlay_set_fetch(struct mmp_overlay *overlay, int fetch_id)
225 overlay->dmafetch_id = fetch_id;
228 static int overlay_set_addr(struct mmp_overlay *overlay, struct mmp_addr *addr)
230 struct lcd_regs *regs = path_regs(overlay->path);
232 /* FIXME: assert addr supported */
233 memcpy(&overlay->addr, addr, sizeof(struct mmp_addr));
235 if (overlay_is_vid(overlay)) {
236 writel_relaxed(addr->phys[0], ®s->v_y0);
237 writel_relaxed(addr->phys[1], ®s->v_u0);
238 writel_relaxed(addr->phys[2], ®s->v_v0);
240 writel_relaxed(addr->phys[0], ®s->g_0);
242 return overlay->addr.phys[0];
245 static void path_set_mode(struct mmp_path *path, struct mmp_mode *mode)
247 struct lcd_regs *regs = path_regs(path);
248 u32 total_x, total_y, vsync_ctrl, tmp, sclk_src, sclk_div,
249 link_config = path_to_path_plat(path)->link_config,
250 dsi_rbswap = path_to_path_plat(path)->link_config;
252 /* FIXME: assert videomode supported */
253 memcpy(&path->mode, mode, sizeof(struct mmp_mode));
255 mutex_lock(&path->access_ok);
257 /* polarity of timing signals */
258 tmp = readl_relaxed(ctrl_regs(path) + intf_ctrl(path->id)) & 0x1;
259 tmp |= mode->vsync_invert ? 0 : 0x8;
260 tmp |= mode->hsync_invert ? 0 : 0x4;
261 tmp |= link_config & CFG_DUMBMODE_MASK;
262 tmp |= CFG_DUMB_ENA(1);
263 writel_relaxed(tmp, ctrl_regs(path) + intf_ctrl(path->id));
265 /* interface rb_swap setting */
266 tmp = readl_relaxed(ctrl_regs(path) + intf_rbswap_ctrl(path->id)) &
267 (~(CFG_INTFRBSWAP_MASK));
268 tmp |= dsi_rbswap & CFG_INTFRBSWAP_MASK;
269 writel_relaxed(tmp, ctrl_regs(path) + intf_rbswap_ctrl(path->id));
271 writel_relaxed((mode->yres << 16) | mode->xres, ®s->screen_active);
272 writel_relaxed((mode->left_margin << 16) | mode->right_margin,
273 ®s->screen_h_porch);
274 writel_relaxed((mode->upper_margin << 16) | mode->lower_margin,
275 ®s->screen_v_porch);
276 total_x = mode->xres + mode->left_margin + mode->right_margin +
278 total_y = mode->yres + mode->upper_margin + mode->lower_margin +
280 writel_relaxed((total_y << 16) | total_x, ®s->screen_size);
283 if (path->output_type == PATH_OUT_DSI)
284 vsync_ctrl = 0x01330133;
286 vsync_ctrl = ((mode->xres + mode->right_margin) << 16)
287 | (mode->xres + mode->right_margin);
288 writel_relaxed(vsync_ctrl, ®s->vsync_ctrl);
290 /* set pixclock div */
291 sclk_src = clk_get_rate(path_to_ctrl(path)->clk);
292 sclk_div = sclk_src / mode->pixclock_freq;
293 if (sclk_div * mode->pixclock_freq < sclk_src)
296 dev_info(path->dev, "%s sclk_src %d sclk_div 0x%x pclk %d\n",
297 __func__, sclk_src, sclk_div, mode->pixclock_freq);
299 tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));
300 tmp &= ~CLK_INT_DIV_MASK;
302 writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
304 mutex_unlock(&path->access_ok);
307 static struct mmp_overlay_ops mmphw_overlay_ops = {
308 .set_fetch = overlay_set_fetch,
309 .set_onoff = overlay_set_onoff,
310 .set_win = overlay_set_win,
311 .set_addr = overlay_set_addr,
314 static void ctrl_set_default(struct mmphw_ctrl *ctrl)
319 * LCD Global control(LCD_TOP_CTRL) should be configed before
320 * any other LCD registers read/write, or there maybe issues.
322 tmp = readl_relaxed(ctrl->reg_base + LCD_TOP_CTRL);
324 writel_relaxed(tmp, ctrl->reg_base + LCD_TOP_CTRL);
327 /* disable all interrupts */
328 irq_mask = path_imasks(0) | err_imask(0) |
329 path_imasks(1) | err_imask(1);
330 tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA);
333 writel_relaxed(tmp, ctrl->reg_base + SPU_IRQ_ENA);
336 static void path_set_default(struct mmp_path *path)
338 struct lcd_regs *regs = path_regs(path);
339 u32 dma_ctrl1, mask, tmp, path_config;
341 path_config = path_to_path_plat(path)->path_config;
343 /* Configure IOPAD: should be parallel only */
344 if (PATH_OUT_PARALLEL == path->output_type) {
345 mask = CFG_IOPADMODE_MASK | CFG_BURST_MASK | CFG_BOUNDARY_MASK;
346 tmp = readl_relaxed(ctrl_regs(path) + SPU_IOPAD_CONTROL);
349 writel_relaxed(tmp, ctrl_regs(path) + SPU_IOPAD_CONTROL);
352 /* Select path clock source */
353 tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path));
354 tmp &= ~SCLK_SRC_SEL_MASK;
356 writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));
359 * Configure default bits: vsync triggers DMA,
360 * power save enable, configure alpha registers to
361 * display 100% graphics, and set pixel command.
363 dma_ctrl1 = 0x2032ff81;
365 dma_ctrl1 |= CFG_VSYNC_INV_MASK;
366 writel_relaxed(dma_ctrl1, ctrl_regs(path) + dma_ctrl(1, path->id));
368 /* Configure default register values */
369 writel_relaxed(0x00000000, ®s->blank_color);
370 writel_relaxed(0x00000000, ®s->g_1);
371 writel_relaxed(0x00000000, ®s->g_start);
374 * 1.enable multiple burst request in DMA AXI
375 * bus arbiter for faster read if not tv path;
376 * 2.enable horizontal smooth filter;
378 mask = CFG_GRA_HSMOOTH_MASK | CFG_DMA_HSMOOTH_MASK | CFG_ARBFAST_ENA(1);
379 tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
381 if (PATH_TV == path->id)
382 tmp &= ~CFG_ARBFAST_ENA(1);
383 writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
386 static int path_init(struct mmphw_path_plat *path_plat,
387 struct mmp_mach_path_config *config)
389 struct mmphw_ctrl *ctrl = path_plat->ctrl;
390 struct mmp_path_info *path_info;
391 struct mmp_path *path = NULL;
393 dev_info(ctrl->dev, "%s: %s\n", __func__, config->name);
395 /* init driver data */
396 path_info = kzalloc(sizeof(*path_info), GFP_KERNEL);
400 path_info->name = config->name;
401 path_info->id = path_plat->id;
402 path_info->dev = ctrl->dev;
403 path_info->overlay_num = config->overlay_num;
404 path_info->overlay_ops = &mmphw_overlay_ops;
405 path_info->set_mode = path_set_mode;
406 path_info->plat_data = path_plat;
408 /* create/register platform device */
409 path = mmp_register_path(path_info);
414 path_plat->path = path;
415 path_plat->path_config = config->path_config;
416 path_plat->link_config = config->link_config;
417 path_plat->dsi_rbswap = config->dsi_rbswap;
418 path_set_default(path);
424 static void path_deinit(struct mmphw_path_plat *path_plat)
429 mmp_unregister_path(path_plat->path);
432 static int mmphw_probe(struct platform_device *pdev)
434 struct mmp_mach_plat_info *mi;
435 struct resource *res;
437 struct mmphw_path_plat *path_plat;
438 struct mmphw_ctrl *ctrl = NULL;
440 /* get resources from platform data */
441 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
443 dev_err(&pdev->dev, "%s: no IO memory defined\n", __func__);
448 irq = platform_get_irq(pdev, 0);
450 dev_err(&pdev->dev, "%s: no IRQ defined\n", __func__);
455 /* get configs from platform data */
456 mi = pdev->dev.platform_data;
457 if (mi == NULL || !mi->path_num || !mi->paths) {
458 dev_err(&pdev->dev, "%s: no platform data defined\n", __func__);
464 ctrl = devm_kzalloc(&pdev->dev,
465 struct_size(ctrl, path_plats, mi->path_num),
472 ctrl->name = mi->name;
473 ctrl->path_num = mi->path_num;
474 ctrl->dev = &pdev->dev;
476 platform_set_drvdata(pdev, ctrl);
477 mutex_init(&ctrl->access_ok);
480 if (!devm_request_mem_region(ctrl->dev, res->start,
481 resource_size(res), ctrl->name)) {
483 "can't request region for resource %pR\n", res);
488 ctrl->reg_base = devm_ioremap_nocache(ctrl->dev,
489 res->start, resource_size(res));
490 if (ctrl->reg_base == NULL) {
491 dev_err(ctrl->dev, "%s: res %pR map failed\n", __func__, res);
497 ret = devm_request_irq(ctrl->dev, ctrl->irq, ctrl_handle_irq,
498 IRQF_SHARED, "lcd_controller", ctrl);
500 dev_err(ctrl->dev, "%s unable to request IRQ %d\n",
501 __func__, ctrl->irq);
507 ctrl->clk = devm_clk_get(ctrl->dev, mi->clk_name);
508 if (IS_ERR(ctrl->clk)) {
509 dev_err(ctrl->dev, "unable to get clk %s\n", mi->clk_name);
513 clk_prepare_enable(ctrl->clk);
515 /* init global regs */
516 ctrl_set_default(ctrl);
518 /* init pathes from machine info and register them */
519 for (i = 0; i < ctrl->path_num; i++) {
520 /* get from config and machine info */
521 path_plat = &ctrl->path_plats[i];
523 path_plat->ctrl = ctrl;
526 if (!path_init(path_plat, &mi->paths[i])) {
528 goto failed_path_init;
532 #ifdef CONFIG_MMP_DISP_SPI
533 ret = lcd_spi_register(ctrl);
535 goto failed_path_init;
538 dev_info(ctrl->dev, "device init done\n");
543 for (i = 0; i < ctrl->path_num; i++) {
544 path_plat = &ctrl->path_plats[i];
545 path_deinit(path_plat);
548 clk_disable_unprepare(ctrl->clk);
550 dev_err(&pdev->dev, "device init failed\n");
555 static struct platform_driver mmphw_driver = {
559 .probe = mmphw_probe,
562 static int mmphw_init(void)
564 return platform_driver_register(&mmphw_driver);
566 module_init(mmphw_init);
568 MODULE_AUTHOR("Li Guoqing<ligq@marvell.com>");
569 MODULE_DESCRIPTION("Framebuffer driver for mmp");
570 MODULE_LICENSE("GPL");