drivers/video/exynos_dp_lowlevel.c

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics
   3  *
   4  * Author: Donghwa Lee <dh09.lee@samsung.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include <config.h>
  23 #include <common.h>
  24 #include <linux/err.h>
  25 #include <asm/arch/cpu.h>
  26 #include <asm/arch/dp_info.h>
  27 #include <asm/arch/dp.h>
  28 #include <fdtdec.h>
  29 #include <libfdt.h>
  30
  31 /* Declare global data pointer */
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 struct exynos_dp *dp_regs;
  35
  36 void exynos_dp_set_base_addr(void)
  37 {
  38 #ifdef CONFIG_OF_CONTROL
  39         unsigned int node = fdtdec_next_compatible(gd->fdt_blob,
  40                                         0, COMPAT_SAMSUNG_EXYNOS5_DP);
  41         if (node <= 0)
  42                 debug("exynos_dp: Can't get device node for dp\n");
  43
  44         dp_regs = (struct exynos_dp *)fdtdec_get_addr(gd->fdt_blob,
  45                                                                 node, "reg");
  46         if (dp_regs == NULL)
  47                 debug("Can't get the DP base address\n");
  48 #else
  49         dp_regs = (struct exynos_dp *)samsung_get_base_dp();
  50 #endif
  51 }
  52
  53 static void exynos_dp_enable_video_input(unsigned int enable)
  54 {
  55         unsigned int reg;
  56
  57         reg = readl(&dp_regs->video_ctl1);
  58         reg &= ~VIDEO_EN_MASK;
  59
  60         /* enable video input*/
  61         if (enable)
  62                 reg |= VIDEO_EN_MASK;
  63
  64         writel(reg, &dp_regs->video_ctl1);
  65
  66         return;
  67 }
  68
  69 void exynos_dp_enable_video_bist(unsigned int enable)
  70 {
  71         /*enable video bist*/
  72         unsigned int reg;
  73
  74         reg = readl(&dp_regs->video_ctl4);
  75         reg &= ~VIDEO_BIST_MASK;
  76
  77         /*enable video bist*/
  78         if (enable)
  79                 reg |= VIDEO_BIST_MASK;
  80
  81         writel(reg, &dp_regs->video_ctl4);
  82
  83         return;
  84 }
  85
  86 void exynos_dp_enable_video_mute(unsigned int enable)
  87 {
  88         unsigned int reg;
  89
  90         reg = readl(&dp_regs->video_ctl1);
  91         reg &= ~(VIDEO_MUTE_MASK);
  92         if (enable)
  93                 reg |= VIDEO_MUTE_MASK;
  94
  95         writel(reg, &dp_regs->video_ctl1);
  96
  97         return;
  98 }
  99
 100
 101 static void exynos_dp_init_analog_param(void)
 102 {
 103         unsigned int reg;
 104
 105         /*
 106          * Set termination
 107          * Normal bandgap, Normal swing, Tx terminal registor 61 ohm
 108          * 24M Phy clock, TX digital logic power is 100:1.0625V
 109          */
 110         reg = SEL_BG_NEW_BANDGAP | TX_TERMINAL_CTRL_61_OHM |
 111                 SWING_A_30PER_G_NORMAL;
 112         writel(reg, &dp_regs->analog_ctl1);
 113
 114         reg = SEL_24M | TX_DVDD_BIT_1_0625V;
 115         writel(reg, &dp_regs->analog_ctl2);
 116
 117         /*
 118          * Set power source for internal clk driver to 1.0625v.
 119          * Select current reference of TX driver current to 00:Ipp/2+Ic/2.
 120          * Set VCO range of PLL +- 0uA
 121          */
 122         reg = DRIVE_DVDD_BIT_1_0625V | SEL_CURRENT_DEFAULT | VCO_BIT_000_MICRO;
 123         writel(reg, &dp_regs->analog_ctl3);
 124
 125         /*
 126          * Set AUX TX terminal resistor to 102 ohm
 127          * Set AUX channel amplitude control
 128         */
 129         reg = PD_RING_OSC | AUX_TERMINAL_CTRL_52_OHM | TX_CUR1_2X | TX_CUR_4_MA;
 130         writel(reg, &dp_regs->pll_filter_ctl1);
 131
 132         /*
 133          * PLL loop filter bandwidth
 134          * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
 135          * PLL digital power select: 1.2500V
 136          */
 137         reg = CH3_AMP_0_MV | CH2_AMP_0_MV | CH1_AMP_0_MV | CH0_AMP_0_MV;
 138
 139         writel(reg, &dp_regs->amp_tuning_ctl);
 140
 141         /*
 142          * PLL loop filter bandwidth
 143          * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
 144          * PLL digital power select: 1.1250V
 145          */
 146         reg = DP_PLL_LOOP_BIT_DEFAULT | DP_PLL_REF_BIT_1_1250V;
 147         writel(reg, &dp_regs->pll_ctl);
 148 }
 149
 150 static void exynos_dp_init_interrupt(void)
 151 {
 152         /* Set interrupt registers to initial states */
 153
 154         /*
 155          * Disable interrupt
 156          * INT pin assertion polarity. It must be configured
 157          * correctly according to ICU setting.
 158          * 1 = assert high, 0 = assert low
 159          */
 160         writel(INT_POL, &dp_regs->int_ctl);
 161
 162         /* Clear pending regisers */
 163         writel(0xff, &dp_regs->common_int_sta1);
 164         writel(0xff, &dp_regs->common_int_sta2);
 165         writel(0xff, &dp_regs->common_int_sta3);
 166         writel(0xff, &dp_regs->common_int_sta4);
 167         writel(0xff, &dp_regs->int_sta);
 168
 169         /* 0:mask,1: unmask */
 170         writel(0x00, &dp_regs->int_sta_mask1);
 171         writel(0x00, &dp_regs->int_sta_mask2);
 172         writel(0x00, &dp_regs->int_sta_mask3);
 173         writel(0x00, &dp_regs->int_sta_mask4);
 174         writel(0x00, &dp_regs->int_sta_mask);
 175 }
 176
 177 void exynos_dp_reset(void)
 178 {
 179         unsigned int reg_func_1;
 180
 181         /*dp tx sw reset*/
 182         writel(RESET_DP_TX, &dp_regs->tx_sw_reset);
 183
 184         exynos_dp_enable_video_input(DP_DISABLE);
 185         exynos_dp_enable_video_bist(DP_DISABLE);
 186         exynos_dp_enable_video_mute(DP_DISABLE);
 187
 188         /* software reset */
 189         reg_func_1 = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
 190                 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
 191                 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
 192
 193         writel(reg_func_1, &dp_regs->func_en1);
 194         writel(reg_func_1, &dp_regs->func_en2);
 195
 196         mdelay(1);
 197
 198         exynos_dp_init_analog_param();
 199         exynos_dp_init_interrupt();
 200
 201         return;
 202 }
 203
 204 void exynos_dp_enable_sw_func(unsigned int enable)
 205 {
 206         unsigned int reg;
 207
 208         reg = readl(&dp_regs->func_en1);
 209         reg &= ~(SW_FUNC_EN_N);
 210
 211         if (!enable)
 212                 reg |= SW_FUNC_EN_N;
 213
 214         writel(reg, &dp_regs->func_en1);
 215
 216         return;
 217 }
 218
 219 unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable)
 220 {
 221         unsigned int reg;
 222
 223         reg = readl(&dp_regs->phy_pd);
 224         switch (block) {
 225         case AUX_BLOCK:
 226                 reg &= ~(AUX_PD);
 227                 if (enable)
 228                         reg |= AUX_PD;
 229                 break;
 230         case CH0_BLOCK:
 231                 reg &= ~(CH0_PD);
 232                 if (enable)
 233                         reg |= CH0_PD;
 234                 break;
 235         case CH1_BLOCK:
 236                 reg &= ~(CH1_PD);
 237                 if (enable)
 238                         reg |= CH1_PD;
 239                 break;
 240         case CH2_BLOCK:
 241                 reg &= ~(CH2_PD);
 242                 if (enable)
 243                         reg |= CH2_PD;
 244                 break;
 245         case CH3_BLOCK:
 246                 reg &= ~(CH3_PD);
 247                 if (enable)
 248                         reg |= CH3_PD;
 249                 break;
 250         case ANALOG_TOTAL:
 251                 reg &= ~PHY_PD;
 252                 if (enable)
 253                         reg |= PHY_PD;
 254                 break;
 255         case POWER_ALL:
 256                 reg &= ~(PHY_PD | AUX_PD | CH0_PD | CH1_PD | CH2_PD |
 257                         CH3_PD);
 258                 if (enable)
 259                         reg |= (PHY_PD | AUX_PD | CH0_PD | CH1_PD |
 260                                 CH2_PD | CH3_PD);
 261                 break;
 262         default:
 263                 printf("DP undefined block number : %d\n",  block);
 264                 return -1;
 265         }
 266
 267         writel(reg, &dp_regs->phy_pd);
 268
 269         return 0;
 270 }
 271
 272 unsigned int exynos_dp_get_pll_lock_status(void)
 273 {
 274         unsigned int reg;
 275
 276         reg = readl(&dp_regs->debug_ctl);
 277
 278         if (reg & PLL_LOCK)
 279                 return PLL_LOCKED;
 280         else
 281                 return PLL_UNLOCKED;
 282 }
 283
 284 static void exynos_dp_set_pll_power(unsigned int enable)
 285 {
 286         unsigned int reg;
 287
 288         reg = readl(&dp_regs->pll_ctl);
 289         reg &= ~(DP_PLL_PD);
 290
 291         if (!enable)
 292                 reg |= DP_PLL_PD;
 293
 294         writel(reg, &dp_regs->pll_ctl);
 295 }
 296
 297 int exynos_dp_init_analog_func(void)
 298 {
 299         int ret = EXYNOS_DP_SUCCESS;
 300         unsigned int retry_cnt = 10;
 301         unsigned int reg;
 302
 303         /*Power On All Analog block */
 304         exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE);
 305
 306         reg = PLL_LOCK_CHG;
 307         writel(reg, &dp_regs->common_int_sta1);
 308
 309         reg = readl(&dp_regs->debug_ctl);
 310         reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
 311         writel(reg, &dp_regs->debug_ctl);
 312
 313         /*Assert DP PLL Reset*/
 314         reg = readl(&dp_regs->pll_ctl);
 315         reg |= DP_PLL_RESET;
 316         writel(reg, &dp_regs->pll_ctl);
 317
 318         mdelay(1);
 319
 320         /*Deassert DP PLL Reset*/
 321         reg = readl(&dp_regs->pll_ctl);
 322         reg &= ~(DP_PLL_RESET);
 323         writel(reg, &dp_regs->pll_ctl);
 324
 325         exynos_dp_set_pll_power(DP_ENABLE);
 326
 327         while (exynos_dp_get_pll_lock_status() == PLL_UNLOCKED) {
 328                 mdelay(1);
 329                 retry_cnt--;
 330                 if (retry_cnt == 0) {
 331                         printf("DP dp's pll lock failed : retry : %d\n",
 332                                         retry_cnt);
 333                         return -EINVAL;
 334                 }
 335         }
 336
 337         debug("dp's pll lock success(%d)\n", retry_cnt);
 338
 339         /* Enable Serdes FIFO function and Link symbol clock domain module */
 340         reg = readl(&dp_regs->func_en2);
 341         reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
 342                 | AUX_FUNC_EN_N);
 343         writel(reg, &dp_regs->func_en2);
 344
 345         return ret;
 346 }
 347
 348 void exynos_dp_init_hpd(void)
 349 {
 350         unsigned int reg;
 351
 352         /* Clear interrupts releated to Hot Plug Dectect */
 353         reg = HOTPLUG_CHG | HPD_LOST | PLUG;
 354         writel(reg, &dp_regs->common_int_sta4);
 355
 356         reg = INT_HPD;
 357         writel(reg, &dp_regs->int_sta);
 358
 359         reg = readl(&dp_regs->sys_ctl3);
 360         reg &= ~(F_HPD | HPD_CTRL);
 361         writel(reg, &dp_regs->sys_ctl3);
 362
 363         return;
 364 }
 365
 366 static inline void exynos_dp_reset_aux(void)
 367 {
 368         unsigned int reg;
 369
 370         /* Disable AUX channel module */
 371         reg = readl(&dp_regs->func_en2);
 372         reg |= AUX_FUNC_EN_N;
 373         writel(reg, &dp_regs->func_en2);
 374
 375         return;
 376 }
 377
 378 void exynos_dp_init_aux(void)
 379 {
 380         unsigned int reg;
 381
 382         /* Clear inerrupts related to AUX channel */
 383         reg = RPLY_RECEIV | AUX_ERR;
 384         writel(reg, &dp_regs->int_sta);
 385
 386         exynos_dp_reset_aux();
 387
 388         /* Disable AUX transaction H/W retry */
 389         reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(3)|
 390                 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 391         writel(reg, &dp_regs->aux_hw_retry_ctl);
 392
 393         /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
 394         reg = DEFER_CTRL_EN | DEFER_COUNT(1);
 395         writel(reg, &dp_regs->aux_ch_defer_ctl);
 396
 397         /* Enable AUX channel module */
 398         reg = readl(&dp_regs->func_en2);
 399         reg &= ~AUX_FUNC_EN_N;
 400         writel(reg, &dp_regs->func_en2);
 401
 402         return;
 403 }
 404
 405 void exynos_dp_config_interrupt(void)
 406 {
 407         unsigned int reg;
 408
 409         /* 0: mask, 1: unmask */
 410         reg = COMMON_INT_MASK_1;
 411         writel(reg, &dp_regs->common_int_mask1);
 412
 413         reg = COMMON_INT_MASK_2;
 414         writel(reg, &dp_regs->common_int_mask2);
 415
 416         reg = COMMON_INT_MASK_3;
 417         writel(reg, &dp_regs->common_int_mask3);
 418
 419         reg = COMMON_INT_MASK_4;
 420         writel(reg, &dp_regs->common_int_mask4);
 421
 422         reg = INT_STA_MASK;
 423         writel(reg, &dp_regs->int_sta_mask);
 424
 425         return;
 426 }
 427
 428 unsigned int exynos_dp_get_plug_in_status(void)
 429 {
 430         unsigned int reg;
 431
 432         reg = readl(&dp_regs->sys_ctl3);
 433         if (reg & HPD_STATUS)
 434                 return 0;
 435
 436         return -1;
 437 }
 438
 439 unsigned int exynos_dp_detect_hpd(void)
 440 {
 441         int timeout_loop = DP_TIMEOUT_LOOP_COUNT;
 442
 443         mdelay(2);
 444
 445         while (exynos_dp_get_plug_in_status() != 0) {
 446                 if (timeout_loop == 0)
 447                         return -EINVAL;
 448                 mdelay(10);
 449                 timeout_loop--;
 450         }
 451
 452         return EXYNOS_DP_SUCCESS;
 453 }
 454
 455 unsigned int exynos_dp_start_aux_transaction(void)
 456 {
 457         unsigned int reg;
 458         unsigned int ret = 0;
 459         unsigned int retry_cnt;
 460
 461         /* Enable AUX CH operation */
 462         reg = readl(&dp_regs->aux_ch_ctl2);
 463         reg |= AUX_EN;
 464         writel(reg, &dp_regs->aux_ch_ctl2);
 465
 466         retry_cnt = 10;
 467         while (retry_cnt) {
 468                 reg = readl(&dp_regs->int_sta);
 469                 if (!(reg & RPLY_RECEIV)) {
 470                         if (retry_cnt == 0) {
 471                                 printf("DP Reply Timeout!!\n");
 472                                 ret = -EAGAIN;
 473                                 return ret;
 474                         }
 475                         mdelay(1);
 476                         retry_cnt--;
 477                 } else
 478                         break;
 479         }
 480
 481         /* Clear interrupt source for AUX CH command reply */
 482         writel(reg, &dp_regs->int_sta);
 483
 484         /* Clear interrupt source for AUX CH access error */
 485         reg = readl(&dp_regs->int_sta);
 486         if (reg & AUX_ERR) {
 487                 printf("DP Aux Access Error\n");
 488                 writel(AUX_ERR, &dp_regs->int_sta);
 489                 ret = -EAGAIN;
 490                 return ret;
 491         }
 492
 493         /* Check AUX CH error access status */
 494         reg = readl(&dp_regs->aux_ch_sta);
 495         if ((reg & AUX_STATUS_MASK) != 0) {
 496                 debug("DP AUX CH error happens: %x\n", reg & AUX_STATUS_MASK);
 497                 ret = -EAGAIN;
 498                 return ret;
 499         }
 500
 501         return EXYNOS_DP_SUCCESS;
 502 }
 503
 504 unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr,
 505                                 unsigned char data)
 506 {
 507         unsigned int reg, ret;
 508
 509         /* Clear AUX CH data buffer */
 510         reg = BUF_CLR;
 511         writel(reg, &dp_regs->buffer_data_ctl);
 512
 513         /* Select DPCD device address */
 514         reg = AUX_ADDR_7_0(reg_addr);
 515         writel(reg, &dp_regs->aux_addr_7_0);
 516         reg = AUX_ADDR_15_8(reg_addr);
 517         writel(reg, &dp_regs->aux_addr_15_8);
 518         reg = AUX_ADDR_19_16(reg_addr);
 519         writel(reg, &dp_regs->aux_addr_19_16);
 520
 521         /* Write data buffer */
 522         reg = (unsigned int)data;
 523         writel(reg, &dp_regs->buf_data0);
 524
 525         /*
 526          * Set DisplayPort transaction and write 1 byte
 527          * If bit 3 is 1, DisplayPort transaction.
 528          * If Bit 3 is 0, I2C transaction.
 529          */
 530         reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 531         writel(reg, &dp_regs->aux_ch_ctl1);
 532
 533         /* Start AUX transaction */
 534         ret = exynos_dp_start_aux_transaction();
 535         if (ret != EXYNOS_DP_SUCCESS) {
 536                 printf("DP Aux transaction failed\n");
 537                 return ret;
 538         }
 539
 540         return ret;
 541 }
 542
 543 unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr,
 544                 unsigned char *data)
 545 {
 546         unsigned int reg;
 547         int retval;
 548
 549         /* Clear AUX CH data buffer */
 550         reg = BUF_CLR;
 551         writel(reg, &dp_regs->buffer_data_ctl);
 552
 553         /* Select DPCD device address */
 554         reg = AUX_ADDR_7_0(reg_addr);
 555         writel(reg, &dp_regs->aux_addr_7_0);
 556         reg = AUX_ADDR_15_8(reg_addr);
 557         writel(reg, &dp_regs->aux_addr_15_8);
 558         reg = AUX_ADDR_19_16(reg_addr);
 559         writel(reg, &dp_regs->aux_addr_19_16);
 560
 561         /*
 562          * Set DisplayPort transaction and read 1 byte
 563          * If bit 3 is 1, DisplayPort transaction.
 564          * If Bit 3 is 0, I2C transaction.
 565          */
 566         reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 567         writel(reg, &dp_regs->aux_ch_ctl1);
 568
 569         /* Start AUX transaction */
 570         retval = exynos_dp_start_aux_transaction();
 571         if (!retval)
 572                 debug("DP Aux Transaction fail!\n");
 573
 574         /* Read data buffer */
 575         reg = readl(&dp_regs->buf_data0);
 576         *data = (unsigned char)(reg & 0xff);
 577
 578         return retval;
 579 }
 580
 581 unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr,
 582                                 unsigned int count,
 583                                 unsigned char data[])
 584 {
 585         unsigned int reg;
 586         unsigned int start_offset;
 587         unsigned int cur_data_count;
 588         unsigned int cur_data_idx;
 589         unsigned int retry_cnt;
 590         unsigned int ret = 0;
 591
 592         /* Clear AUX CH data buffer */
 593         reg = BUF_CLR;
 594         writel(reg, &dp_regs->buffer_data_ctl);
 595
 596         start_offset = 0;
 597         while (start_offset < count) {
 598                 /* Buffer size of AUX CH is 16 * 4bytes */
 599                 if ((count - start_offset) > 16)
 600                         cur_data_count = 16;
 601                 else
 602                         cur_data_count = count - start_offset;
 603
 604                 retry_cnt = 5;
 605                 while (retry_cnt) {
 606                         /* Select DPCD device address */
 607                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 608                         writel(reg, &dp_regs->aux_addr_7_0);
 609                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 610                         writel(reg, &dp_regs->aux_addr_15_8);
 611                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 612                         writel(reg, &dp_regs->aux_addr_19_16);
 613
 614                         for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 615                                         cur_data_idx++) {
 616                                 reg = data[start_offset + cur_data_idx];
 617                                 writel(reg, (unsigned int)&dp_regs->buf_data0 +
 618                                                 (4 * cur_data_idx));
 619                         }
 620                         /*
 621                         * Set DisplayPort transaction and write
 622                         * If bit 3 is 1, DisplayPort transaction.
 623                         * If Bit 3 is 0, I2C transaction.
 624                         */
 625                         reg = AUX_LENGTH(cur_data_count) |
 626                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 627                         writel(reg, &dp_regs->aux_ch_ctl1);
 628
 629                         /* Start AUX transaction */
 630                         ret = exynos_dp_start_aux_transaction();
 631                         if (ret != EXYNOS_DP_SUCCESS) {
 632                                 if (retry_cnt == 0) {
 633                                         printf("DP Aux Transaction failed\n");
 634                                         return ret;
 635                                 }
 636                                 retry_cnt--;
 637                         } else
 638                                 break;
 639                 }
 640                 start_offset += cur_data_count;
 641         }
 642
 643         return ret;
 644 }
 645
 646 unsigned int exynos_dp_read_bytes_from_dpcd(unsigned int reg_addr,
 647                                 unsigned int count,
 648                                 unsigned char data[])
 649 {
 650         unsigned int reg;
 651         unsigned int start_offset;
 652         unsigned int cur_data_count;
 653         unsigned int cur_data_idx;
 654         unsigned int retry_cnt;
 655         unsigned int ret = 0;
 656
 657         /* Clear AUX CH data buffer */
 658         reg = BUF_CLR;
 659         writel(reg, &dp_regs->buffer_data_ctl);
 660
 661         start_offset = 0;
 662         while (start_offset < count) {
 663                 /* Buffer size of AUX CH is 16 * 4bytes */
 664                 if ((count - start_offset) > 16)
 665                         cur_data_count = 16;
 666                 else
 667                         cur_data_count = count - start_offset;
 668
 669                 retry_cnt = 5;
 670                 while (retry_cnt) {
 671                         /* Select DPCD device address */
 672                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 673                         writel(reg, &dp_regs->aux_addr_7_0);
 674                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 675                         writel(reg, &dp_regs->aux_addr_15_8);
 676                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 677                         writel(reg, &dp_regs->aux_addr_19_16);
 678                         /*
 679                          * Set DisplayPort transaction and read
 680                          * If bit 3 is 1, DisplayPort transaction.
 681                          * If Bit 3 is 0, I2C transaction.
 682                          */
 683                         reg = AUX_LENGTH(cur_data_count) |
 684                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 685                         writel(reg, &dp_regs->aux_ch_ctl1);
 686
 687                         /* Start AUX transaction */
 688                         ret = exynos_dp_start_aux_transaction();
 689                         if (ret != EXYNOS_DP_SUCCESS) {
 690                                 if (retry_cnt == 0) {
 691                                         printf("DP Aux Transaction failed\n");
 692                                         return ret;
 693                                 }
 694                                 retry_cnt--;
 695                         } else
 696                                 break;
 697                 }
 698
 699                 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 700                                 cur_data_idx++) {
 701                         reg = readl((unsigned int)&dp_regs->buf_data0 +
 702                                         4 * cur_data_idx);
 703                         data[start_offset + cur_data_idx] = (unsigned char)reg;
 704                 }
 705
 706                 start_offset += cur_data_count;
 707         }
 708
 709         return ret;
 710 }
 711
 712 int exynos_dp_select_i2c_device(unsigned int device_addr,
 713                                 unsigned int reg_addr)
 714 {
 715         unsigned int reg;
 716         int retval;
 717
 718         /* Set EDID device address */
 719         reg = device_addr;
 720         writel(reg, &dp_regs->aux_addr_7_0);
 721         writel(0x0, &dp_regs->aux_addr_15_8);
 722         writel(0x0, &dp_regs->aux_addr_19_16);
 723
 724         /* Set offset from base address of EDID device */
 725         writel(reg_addr, &dp_regs->buf_data0);
 726
 727         /*
 728          * Set I2C transaction and write address
 729          * If bit 3 is 1, DisplayPort transaction.
 730          * If Bit 3 is 0, I2C transaction.
 731          */
 732         reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
 733                 AUX_TX_COMM_WRITE;
 734         writel(reg, &dp_regs->aux_ch_ctl1);
 735
 736         /* Start AUX transaction */
 737         retval = exynos_dp_start_aux_transaction();
 738         if (retval != 0)
 739                 printf("%s: DP Aux Transaction fail!\n", __func__);
 740
 741         return retval;
 742 }
 743
 744 int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
 745                                 unsigned int reg_addr,
 746                                 unsigned int *data)
 747 {
 748         unsigned int reg;
 749         int i;
 750         int retval;
 751
 752         for (i = 0; i < 10; i++) {
 753                 /* Clear AUX CH data buffer */
 754                 reg = BUF_CLR;
 755                 writel(reg, &dp_regs->buffer_data_ctl);
 756
 757                 /* Select EDID device */
 758                 retval = exynos_dp_select_i2c_device(device_addr, reg_addr);
 759                 if (retval != 0) {
 760                         printf("DP Select EDID device fail. retry !\n");
 761                         continue;
 762                 }
 763
 764                 /*
 765                  * Set I2C transaction and read data
 766                  * If bit 3 is 1, DisplayPort transaction.
 767                  * If Bit 3 is 0, I2C transaction.
 768                  */
 769                 reg = AUX_TX_COMM_I2C_TRANSACTION |
 770                         AUX_TX_COMM_READ;
 771                 writel(reg, &dp_regs->aux_ch_ctl1);
 772
 773                 /* Start AUX transaction */
 774                 retval = exynos_dp_start_aux_transaction();
 775                 if (retval != EXYNOS_DP_SUCCESS)
 776                         printf("%s: DP Aux Transaction fail!\n", __func__);
 777         }
 778
 779         /* Read data */
 780         if (retval == 0)
 781                 *data = readl(&dp_regs->buf_data0);
 782
 783         return retval;
 784 }
 785
 786 int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
 787                 unsigned int reg_addr, unsigned int count, unsigned char edid[])
 788 {
 789         unsigned int reg;
 790         unsigned int i, j;
 791         unsigned int cur_data_idx;
 792         unsigned int defer = 0;
 793         int retval = 0;
 794
 795         for (i = 0; i < count; i += 16) { /* use 16 burst */
 796                 for (j = 0; j < 100; j++) {
 797                         /* Clear AUX CH data buffer */
 798                         reg = BUF_CLR;
 799                         writel(reg, &dp_regs->buffer_data_ctl);
 800
 801                         /* Set normal AUX CH command */
 802                         reg = readl(&dp_regs->aux_ch_ctl2);
 803                         reg &= ~ADDR_ONLY;
 804                         writel(reg, &dp_regs->aux_ch_ctl2);
 805
 806                         /*
 807                          * If Rx sends defer, Tx sends only reads
 808                          * request without sending addres
 809                          */
 810                         if (!defer)
 811                                 retval =
 812                                         exynos_dp_select_i2c_device(device_addr,
 813                                                         reg_addr + i);
 814                         else
 815                                 defer = 0;
 816
 817                         if (retval == EXYNOS_DP_SUCCESS) {
 818                                 /*
 819                                  * Set I2C transaction and write data
 820                                  * If bit 3 is 1, DisplayPort transaction.
 821                                  * If Bit 3 is 0, I2C transaction.
 822                                  */
 823                                 reg = AUX_LENGTH(16) |
 824                                         AUX_TX_COMM_I2C_TRANSACTION |
 825                                         AUX_TX_COMM_READ;
 826                                 writel(reg, &dp_regs->aux_ch_ctl1);
 827
 828                                 /* Start AUX transaction */
 829                                 retval = exynos_dp_start_aux_transaction();
 830                                 if (retval == 0)
 831                                         break;
 832                                 else
 833                                         printf("DP Aux Transaction fail!\n");
 834                         }
 835                         /* Check if Rx sends defer */
 836                         reg = readl(&dp_regs->aux_rx_comm);
 837                         if (reg == AUX_RX_COMM_AUX_DEFER ||
 838                                 reg == AUX_RX_COMM_I2C_DEFER) {
 839                                 printf("DP Defer: %d\n\n", reg);
 840                                 defer = 1;
 841                         }
 842                 }
 843
 844                 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
 845                         reg = readl((unsigned int)&dp_regs->buf_data0
 846                                                  + 4 * cur_data_idx);
 847                         edid[i + cur_data_idx] = (unsigned char)reg;
 848                 }
 849         }
 850
 851         return retval;
 852 }
 853
 854 void exynos_dp_reset_macro(void)
 855 {
 856         unsigned int reg;
 857
 858         reg = readl(&dp_regs->phy_test);
 859         reg |= MACRO_RST;
 860         writel(reg, &dp_regs->phy_test);
 861
 862         /* 10 us is the minimum Macro reset time. */
 863         mdelay(1);
 864
 865         reg &= ~MACRO_RST;
 866         writel(reg, &dp_regs->phy_test);
 867 }
 868
 869 void exynos_dp_set_link_bandwidth(unsigned char bwtype)
 870 {
 871         unsigned int reg;
 872
 873         reg = (unsigned int)bwtype;
 874
 875          /* Set bandwidth to 2.7G or 1.62G */
 876         if ((bwtype == DP_LANE_BW_1_62) || (bwtype == DP_LANE_BW_2_70))
 877                 writel(reg, &dp_regs->link_bw_set);
 878 }
 879
 880 unsigned char exynos_dp_get_link_bandwidth(void)
 881 {
 882         unsigned char ret;
 883         unsigned int reg;
 884
 885         reg = readl(&dp_regs->link_bw_set);
 886         ret = (unsigned char)reg;
 887
 888         return ret;
 889 }
 890
 891 void exynos_dp_set_lane_count(unsigned char count)
 892 {
 893         unsigned int reg;
 894
 895         reg = (unsigned int)count;
 896
 897         if ((count == DP_LANE_CNT_1) || (count == DP_LANE_CNT_2) ||
 898                         (count == DP_LANE_CNT_4))
 899                 writel(reg, &dp_regs->lane_count_set);
 900 }
 901
 902 unsigned int exynos_dp_get_lane_count(void)
 903 {
 904         unsigned int reg;
 905
 906         reg = readl(&dp_regs->lane_count_set);
 907
 908         return reg;
 909 }
 910
 911 unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt)
 912 {
 913         unsigned int reg_list[DP_LANE_CNT_4] = {
 914                 (unsigned int)&dp_regs->ln0_link_training_ctl,
 915                 (unsigned int)&dp_regs->ln1_link_training_ctl,
 916                 (unsigned int)&dp_regs->ln2_link_training_ctl,
 917                 (unsigned int)&dp_regs->ln3_link_training_ctl,
 918         };
 919
 920         return readl(reg_list[lanecnt]);
 921 }
 922
 923 void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,
 924                 unsigned char lanecnt)
 925 {
 926         unsigned int reg_list[DP_LANE_CNT_4] = {
 927                 (unsigned int)&dp_regs->ln0_link_training_ctl,
 928                 (unsigned int)&dp_regs->ln1_link_training_ctl,
 929                 (unsigned int)&dp_regs->ln2_link_training_ctl,
 930                 (unsigned int)&dp_regs->ln3_link_training_ctl,
 931         };
 932
 933         writel(request_val, reg_list[lanecnt]);
 934 }
 935
 936 void exynos_dp_set_lane_pre_emphasis(unsigned int level, unsigned char lanecnt)
 937 {
 938         unsigned char i;
 939         unsigned int reg;
 940         unsigned int reg_list[DP_LANE_CNT_4] = {
 941                 (unsigned int)&dp_regs->ln0_link_training_ctl,
 942                 (unsigned int)&dp_regs->ln1_link_training_ctl,
 943                 (unsigned int)&dp_regs->ln2_link_training_ctl,
 944                 (unsigned int)&dp_regs->ln3_link_training_ctl,
 945         };
 946         unsigned int reg_shift[DP_LANE_CNT_4] = {
 947                 PRE_EMPHASIS_SET_0_SHIFT,
 948                 PRE_EMPHASIS_SET_1_SHIFT,
 949                 PRE_EMPHASIS_SET_2_SHIFT,
 950                 PRE_EMPHASIS_SET_3_SHIFT
 951         };
 952
 953         for (i = 0; i < lanecnt; i++) {
 954                 reg = level << reg_shift[i];
 955                 writel(reg, reg_list[i]);
 956         }
 957 }
 958
 959 void exynos_dp_set_training_pattern(unsigned int pattern)
 960 {
 961         unsigned int reg = 0;
 962
 963         switch (pattern) {
 964         case PRBS7:
 965                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
 966                 break;
 967         case D10_2:
 968                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
 969                 break;
 970         case TRAINING_PTN1:
 971                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
 972                 break;
 973         case TRAINING_PTN2:
 974                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
 975                 break;
 976         case DP_NONE:
 977                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_DISABLE |
 978                         SW_TRAINING_PATTERN_SET_NORMAL;
 979                 break;
 980         default:
 981                 break;
 982         }
 983
 984         writel(reg, &dp_regs->training_ptn_set);
 985 }
 986
 987 void exynos_dp_enable_enhanced_mode(unsigned char enable)
 988 {
 989         unsigned int reg;
 990
 991         reg = readl(&dp_regs->sys_ctl4);
 992         reg &= ~ENHANCED;
 993
 994         if (enable)
 995                 reg |= ENHANCED;
 996
 997         writel(reg, &dp_regs->sys_ctl4);
 998 }
 999
1000 void exynos_dp_enable_scrambling(unsigned int enable)
1001 {
1002         unsigned int reg;
1003
1004         reg = readl(&dp_regs->training_ptn_set);
1005         reg &= ~(SCRAMBLING_DISABLE);
1006
1007         if (!enable)
1008                 reg |= SCRAMBLING_DISABLE;
1009
1010         writel(reg, &dp_regs->training_ptn_set);
1011 }
1012
1013 int exynos_dp_init_video(void)
1014 {
1015         unsigned int reg;
1016
1017         /* Clear VID_CLK_CHG[1] and VID_FORMAT_CHG[3] and VSYNC_DET[7] */
1018         reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
1019         writel(reg, &dp_regs->common_int_sta1);
1020
1021         /* I_STRM__CLK detect : DE_CTL : Auto detect */
1022         reg &= ~DET_CTRL;
1023         writel(reg, &dp_regs->sys_ctl1);
1024
1025         return 0;
1026 }
1027
1028 void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info)
1029 {
1030         unsigned int reg;
1031
1032         /* Video Slave mode setting */
1033         reg = readl(&dp_regs->func_en1);
1034         reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
1035         reg |= MASTER_VID_FUNC_EN_N;
1036         writel(reg, &dp_regs->func_en1);
1037
1038         /* Configure Interlaced for slave mode video */
1039         reg = readl(&dp_regs->video_ctl10);
1040         reg &= ~INTERACE_SCAN_CFG;
1041         reg |= (video_info->interlaced << INTERACE_SCAN_CFG_SHIFT);
1042         writel(reg, &dp_regs->video_ctl10);
1043
1044         /* Configure V sync polarity for slave mode video */
1045         reg = readl(&dp_regs->video_ctl10);
1046         reg &= ~VSYNC_POLARITY_CFG;
1047         reg |= (video_info->v_sync_polarity << V_S_POLARITY_CFG_SHIFT);
1048         writel(reg, &dp_regs->video_ctl10);
1049
1050         /* Configure H sync polarity for slave mode video */
1051         reg = readl(&dp_regs->video_ctl10);
1052         reg &= ~HSYNC_POLARITY_CFG;
1053         reg |= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
1054         writel(reg, &dp_regs->video_ctl10);
1055
1056         /*Set video mode to slave mode */
1057         reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1058         writel(reg, &dp_regs->soc_general_ctl);
1059 }
1060
1061 void exynos_dp_set_video_color_format(struct edp_video_info *video_info)
1062 {
1063         unsigned int reg;
1064
1065         /* Configure the input color depth, color space, dynamic range */
1066         reg = (video_info->dynamic_range << IN_D_RANGE_SHIFT) |
1067                 (video_info->color_depth << IN_BPC_SHIFT) |
1068                 (video_info->color_space << IN_COLOR_F_SHIFT);
1069         writel(reg, &dp_regs->video_ctl2);
1070
1071         /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1072         reg = readl(&dp_regs->video_ctl3);
1073         reg &= ~IN_YC_COEFFI_MASK;
1074         if (video_info->ycbcr_coeff)
1075                 reg |= IN_YC_COEFFI_ITU709;
1076         else
1077                 reg |= IN_YC_COEFFI_ITU601;
1078         writel(reg, &dp_regs->video_ctl3);
1079 }
1080
1081 int exynos_dp_config_video_bist(struct edp_device_info *edp_info)
1082 {
1083         unsigned int reg;
1084         unsigned int bist_type = 0;
1085         struct edp_video_info video_info = edp_info->video_info;
1086
1087         /* For master mode, you don't need to set the video format */
1088         if (video_info.master_mode == 0) {
1089                 writel(TOTAL_LINE_CFG_L(edp_info->disp_info.v_total),
1090                                 &dp_regs->total_ln_cfg_l);
1091                 writel(TOTAL_LINE_CFG_H(edp_info->disp_info.v_total),
1092                                 &dp_regs->total_ln_cfg_h);
1093                 writel(ACTIVE_LINE_CFG_L(edp_info->disp_info.v_res),
1094                                 &dp_regs->active_ln_cfg_l);
1095                 writel(ACTIVE_LINE_CFG_H(edp_info->disp_info.v_res),
1096                                 &dp_regs->active_ln_cfg_h);
1097                 writel(edp_info->disp_info.v_sync_width,
1098                                 &dp_regs->vsw_cfg);
1099                 writel(edp_info->disp_info.v_back_porch,
1100                                 &dp_regs->vbp_cfg);
1101                 writel(edp_info->disp_info.v_front_porch,
1102                                 &dp_regs->vfp_cfg);
1103
1104                 writel(TOTAL_PIXEL_CFG_L(edp_info->disp_info.h_total),
1105                                 &dp_regs->total_pix_cfg_l);
1106                 writel(TOTAL_PIXEL_CFG_H(edp_info->disp_info.h_total),
1107                                 &dp_regs->total_pix_cfg_h);
1108                 writel(ACTIVE_PIXEL_CFG_L(edp_info->disp_info.h_res),
1109                                 &dp_regs->active_pix_cfg_l);
1110                 writel(ACTIVE_PIXEL_CFG_H(edp_info->disp_info.h_res),
1111                                 &dp_regs->active_pix_cfg_h);
1112                 writel(H_F_PORCH_CFG_L(edp_info->disp_info.h_front_porch),
1113                                 &dp_regs->hfp_cfg_l);
1114                 writel(H_F_PORCH_CFG_H(edp_info->disp_info.h_front_porch),
1115                                 &dp_regs->hfp_cfg_h);
1116                 writel(H_SYNC_PORCH_CFG_L(edp_info->disp_info.h_sync_width),
1117                                 &dp_regs->hsw_cfg_l);
1118                 writel(H_SYNC_PORCH_CFG_H(edp_info->disp_info.h_sync_width),
1119                                 &dp_regs->hsw_cfg_h);
1120                 writel(H_B_PORCH_CFG_L(edp_info->disp_info.h_back_porch),
1121                                 &dp_regs->hbp_cfg_l);
1122                 writel(H_B_PORCH_CFG_H(edp_info->disp_info.h_back_porch),
1123                                 &dp_regs->hbp_cfg_h);
1124
1125                 /*
1126                  * Set SLAVE_I_SCAN_CFG[2], VSYNC_P_CFG[1],
1127                  * HSYNC_P_CFG[0] properly
1128                  */
1129                 reg = (video_info.interlaced << INTERACE_SCAN_CFG_SHIFT |
1130                         video_info.v_sync_polarity << V_S_POLARITY_CFG_SHIFT |
1131                         video_info.h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
1132                 writel(reg, &dp_regs->video_ctl10);
1133         }
1134
1135         /* BIST color bar width set--set to each bar is 32 pixel width */
1136         switch (video_info.bist_pattern) {
1137         case COLORBAR_32:
1138                 bist_type = BIST_WIDTH_BAR_32_PIXEL |
1139                           BIST_TYPE_COLOR_BAR;
1140                 break;
1141         case COLORBAR_64:
1142                 bist_type = BIST_WIDTH_BAR_64_PIXEL |
1143                           BIST_TYPE_COLOR_BAR;
1144                 break;
1145         case WHITE_GRAY_BALCKBAR_32:
1146                 bist_type = BIST_WIDTH_BAR_32_PIXEL |
1147                           BIST_TYPE_WHITE_GRAY_BLACK_BAR;
1148                 break;
1149         case WHITE_GRAY_BALCKBAR_64:
1150                 bist_type = BIST_WIDTH_BAR_64_PIXEL |
1151                           BIST_TYPE_WHITE_GRAY_BLACK_BAR;
1152                 break;
1153         case MOBILE_WHITEBAR_32:
1154                 bist_type = BIST_WIDTH_BAR_32_PIXEL |
1155                           BIST_TYPE_MOBILE_WHITE_BAR;
1156                 break;
1157         case MOBILE_WHITEBAR_64:
1158                 bist_type = BIST_WIDTH_BAR_64_PIXEL |
1159                           BIST_TYPE_MOBILE_WHITE_BAR;
1160                 break;
1161         default:
1162                 return -1;
1163         }
1164
1165         reg = bist_type;
1166         writel(reg, &dp_regs->video_ctl4);
1167
1168         return 0;
1169 }
1170
1171 unsigned int exynos_dp_is_slave_video_stream_clock_on(void)
1172 {
1173         unsigned int reg;
1174
1175         /* Update Video stream clk detect status */
1176         reg = readl(&dp_regs->sys_ctl1);
1177         writel(reg, &dp_regs->sys_ctl1);
1178
1179         reg = readl(&dp_regs->sys_ctl1);
1180
1181         if (!(reg & DET_STA)) {
1182                 debug("DP Input stream clock not detected.\n");
1183                 return -EIO;
1184         }
1185
1186         return EXYNOS_DP_SUCCESS;
1187 }
1188
1189 void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
1190                 unsigned int n_value)
1191 {
1192         unsigned int reg;
1193
1194         if (type == REGISTER_M) {
1195                 reg = readl(&dp_regs->sys_ctl4);
1196                 reg |= FIX_M_VID;
1197                 writel(reg, &dp_regs->sys_ctl4);
1198                 reg = M_VID0_CFG(m_value);
1199                 writel(reg, &dp_regs->m_vid0);
1200                 reg = M_VID1_CFG(m_value);
1201                 writel(reg, &dp_regs->m_vid1);
1202                 reg = M_VID2_CFG(m_value);
1203                 writel(reg, &dp_regs->m_vid2);
1204
1205                 reg = N_VID0_CFG(n_value);
1206                 writel(reg, &dp_regs->n_vid0);
1207                 reg = N_VID1_CFG(n_value);
1208                 writel(reg, &dp_regs->n_vid1);
1209                 reg = N_VID2_CFG(n_value);
1210                 writel(reg, &dp_regs->n_vid2);
1211         } else  {
1212                 reg = readl(&dp_regs->sys_ctl4);
1213                 reg &= ~FIX_M_VID;
1214                 writel(reg, &dp_regs->sys_ctl4);
1215         }
1216 }
1217
1218 void exynos_dp_set_video_timing_mode(unsigned int type)
1219 {
1220         unsigned int reg;
1221
1222         reg = readl(&dp_regs->video_ctl10);
1223         reg &= ~FORMAT_SEL;
1224
1225         if (type != VIDEO_TIMING_FROM_CAPTURE)
1226                 reg |= FORMAT_SEL;
1227
1228         writel(reg, &dp_regs->video_ctl10);
1229 }
1230
1231 void exynos_dp_enable_video_master(unsigned int enable)
1232 {
1233         unsigned int reg;
1234
1235         reg = readl(&dp_regs->soc_general_ctl);
1236         if (enable) {
1237                 reg &= ~VIDEO_MODE_MASK;
1238                 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1239         } else {
1240                 reg &= ~VIDEO_MODE_MASK;
1241                 reg |= VIDEO_MODE_SLAVE_MODE;
1242         }
1243
1244         writel(reg, &dp_regs->soc_general_ctl);
1245 }
1246
1247 void exynos_dp_start_video(void)
1248 {
1249         unsigned int reg;
1250
1251         /* Enable Video input and disable Mute */
1252         reg = readl(&dp_regs->video_ctl1);
1253         reg |= VIDEO_EN;
1254         writel(reg, &dp_regs->video_ctl1);
1255 }
1256
1257 unsigned int exynos_dp_is_video_stream_on(void)
1258 {
1259         unsigned int reg;
1260
1261         /* Update STRM_VALID */
1262         reg = readl(&dp_regs->sys_ctl3);
1263         writel(reg, &dp_regs->sys_ctl3);
1264
1265         reg = readl(&dp_regs->sys_ctl3);
1266         if (!(reg & STRM_VALID))
1267                 return -EIO;
1268
1269         return EXYNOS_DP_SUCCESS;
1270 }