2 * Copyright (C) 2012 Samsung Electronics
4 * Author: Donghwa Lee <dh09.lee@samsung.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/err.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/dp_info.h>
14 #include <asm/arch/dp.h>
16 #include <linux/libfdt.h>
17 #include "exynos_dp_lowlevel.h"
19 /* Declare global data pointer */
20 static void exynos_dp_enable_video_input(struct exynos_dp *dp_regs,
25 reg = readl(&dp_regs->video_ctl1);
26 reg &= ~VIDEO_EN_MASK;
28 /* enable video input */
32 writel(reg, &dp_regs->video_ctl1);
37 void exynos_dp_enable_video_bist(struct exynos_dp *dp_regs, unsigned int enable)
39 /* enable video bist */
42 reg = readl(&dp_regs->video_ctl4);
43 reg &= ~VIDEO_BIST_MASK;
45 /* enable video bist */
47 reg |= VIDEO_BIST_MASK;
49 writel(reg, &dp_regs->video_ctl4);
54 void exynos_dp_enable_video_mute(struct exynos_dp *dp_regs, unsigned int enable)
58 reg = readl(&dp_regs->video_ctl1);
59 reg &= ~(VIDEO_MUTE_MASK);
61 reg |= VIDEO_MUTE_MASK;
63 writel(reg, &dp_regs->video_ctl1);
69 static void exynos_dp_init_analog_param(struct exynos_dp *dp_regs)
75 * Normal bandgap, Normal swing, Tx terminal registor 61 ohm
76 * 24M Phy clock, TX digital logic power is 100:1.0625V
78 reg = SEL_BG_NEW_BANDGAP | TX_TERMINAL_CTRL_61_OHM |
79 SWING_A_30PER_G_NORMAL;
80 writel(reg, &dp_regs->analog_ctl1);
82 reg = SEL_24M | TX_DVDD_BIT_1_0625V;
83 writel(reg, &dp_regs->analog_ctl2);
86 * Set power source for internal clk driver to 1.0625v.
87 * Select current reference of TX driver current to 00:Ipp/2+Ic/2.
88 * Set VCO range of PLL +- 0uA
90 reg = DRIVE_DVDD_BIT_1_0625V | SEL_CURRENT_DEFAULT | VCO_BIT_000_MICRO;
91 writel(reg, &dp_regs->analog_ctl3);
94 * Set AUX TX terminal resistor to 102 ohm
95 * Set AUX channel amplitude control
97 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_52_OHM | TX_CUR1_2X | TX_CUR_4_MA;
98 writel(reg, &dp_regs->pll_filter_ctl1);
101 * PLL loop filter bandwidth
102 * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
103 * PLL digital power select: 1.2500V
105 reg = CH3_AMP_0_MV | CH2_AMP_0_MV | CH1_AMP_0_MV | CH0_AMP_0_MV;
107 writel(reg, &dp_regs->amp_tuning_ctl);
110 * PLL loop filter bandwidth
111 * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz
112 * PLL digital power select: 1.1250V
114 reg = DP_PLL_LOOP_BIT_DEFAULT | DP_PLL_REF_BIT_1_1250V;
115 writel(reg, &dp_regs->pll_ctl);
118 static void exynos_dp_init_interrupt(struct exynos_dp *dp_regs)
120 /* Set interrupt registers to initial states */
124 * INT pin assertion polarity. It must be configured
125 * correctly according to ICU setting.
126 * 1 = assert high, 0 = assert low
128 writel(INT_POL, &dp_regs->int_ctl);
130 /* Clear pending registers */
131 writel(0xff, &dp_regs->common_int_sta1);
132 writel(0xff, &dp_regs->common_int_sta2);
133 writel(0xff, &dp_regs->common_int_sta3);
134 writel(0xff, &dp_regs->common_int_sta4);
135 writel(0xff, &dp_regs->int_sta);
137 /* 0:mask,1: unmask */
138 writel(0x00, &dp_regs->int_sta_mask1);
139 writel(0x00, &dp_regs->int_sta_mask2);
140 writel(0x00, &dp_regs->int_sta_mask3);
141 writel(0x00, &dp_regs->int_sta_mask4);
142 writel(0x00, &dp_regs->int_sta_mask);
145 void exynos_dp_reset(struct exynos_dp *dp_regs)
147 unsigned int reg_func_1;
150 writel(RESET_DP_TX, &dp_regs->tx_sw_reset);
152 exynos_dp_enable_video_input(dp_regs, DP_DISABLE);
153 exynos_dp_enable_video_bist(dp_regs, DP_DISABLE);
154 exynos_dp_enable_video_mute(dp_regs, DP_DISABLE);
157 reg_func_1 = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
158 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
159 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
161 writel(reg_func_1, &dp_regs->func_en1);
162 writel(reg_func_1, &dp_regs->func_en2);
166 exynos_dp_init_analog_param(dp_regs);
167 exynos_dp_init_interrupt(dp_regs);
172 void exynos_dp_enable_sw_func(struct exynos_dp *dp_regs, unsigned int enable)
176 reg = readl(&dp_regs->func_en1);
177 reg &= ~(SW_FUNC_EN_N);
182 writel(reg, &dp_regs->func_en1);
187 unsigned int exynos_dp_set_analog_power_down(struct exynos_dp *dp_regs,
188 unsigned int block, u32 enable)
192 reg = readl(&dp_regs->phy_pd);
225 reg &= ~(PHY_PD | AUX_PD | CH0_PD | CH1_PD | CH2_PD |
228 reg |= (PHY_PD | AUX_PD | CH0_PD | CH1_PD |
232 printf("DP undefined block number : %d\n", block);
236 writel(reg, &dp_regs->phy_pd);
241 unsigned int exynos_dp_get_pll_lock_status(struct exynos_dp *dp_regs)
245 reg = readl(&dp_regs->debug_ctl);
253 static void exynos_dp_set_pll_power(struct exynos_dp *dp_regs,
258 reg = readl(&dp_regs->pll_ctl);
264 writel(reg, &dp_regs->pll_ctl);
267 int exynos_dp_init_analog_func(struct exynos_dp *dp_regs)
269 int ret = EXYNOS_DP_SUCCESS;
270 unsigned int retry_cnt = 10;
273 /* Power On All Analog block */
274 exynos_dp_set_analog_power_down(dp_regs, POWER_ALL, DP_DISABLE);
277 writel(reg, &dp_regs->common_int_sta1);
279 reg = readl(&dp_regs->debug_ctl);
280 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
281 writel(reg, &dp_regs->debug_ctl);
283 /* Assert DP PLL Reset */
284 reg = readl(&dp_regs->pll_ctl);
286 writel(reg, &dp_regs->pll_ctl);
290 /* Deassert DP PLL Reset */
291 reg = readl(&dp_regs->pll_ctl);
292 reg &= ~(DP_PLL_RESET);
293 writel(reg, &dp_regs->pll_ctl);
295 exynos_dp_set_pll_power(dp_regs, DP_ENABLE);
297 while (exynos_dp_get_pll_lock_status(dp_regs) == PLL_UNLOCKED) {
300 if (retry_cnt == 0) {
301 printf("DP dp's pll lock failed : retry : %d\n",
307 debug("dp's pll lock success(%d)\n", retry_cnt);
309 /* Enable Serdes FIFO function and Link symbol clock domain module */
310 reg = readl(&dp_regs->func_en2);
311 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
313 writel(reg, &dp_regs->func_en2);
318 void exynos_dp_init_hpd(struct exynos_dp *dp_regs)
322 /* Clear interrupts related to Hot Plug Detect */
323 reg = HOTPLUG_CHG | HPD_LOST | PLUG;
324 writel(reg, &dp_regs->common_int_sta4);
327 writel(reg, &dp_regs->int_sta);
329 reg = readl(&dp_regs->sys_ctl3);
330 reg &= ~(F_HPD | HPD_CTRL);
331 writel(reg, &dp_regs->sys_ctl3);
336 static inline void exynos_dp_reset_aux(struct exynos_dp *dp_regs)
340 /* Disable AUX channel module */
341 reg = readl(&dp_regs->func_en2);
342 reg |= AUX_FUNC_EN_N;
343 writel(reg, &dp_regs->func_en2);
348 void exynos_dp_init_aux(struct exynos_dp *dp_regs)
352 /* Clear interrupts related to AUX channel */
353 reg = RPLY_RECEIV | AUX_ERR;
354 writel(reg, &dp_regs->int_sta);
356 exynos_dp_reset_aux(dp_regs);
358 /* Disable AUX transaction H/W retry */
359 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(3)|
360 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
361 writel(reg, &dp_regs->aux_hw_retry_ctl);
363 /* Receive AUX Channel DEFER commands equal to DEFER_COUNT*64 */
364 reg = DEFER_CTRL_EN | DEFER_COUNT(1);
365 writel(reg, &dp_regs->aux_ch_defer_ctl);
367 /* Enable AUX channel module */
368 reg = readl(&dp_regs->func_en2);
369 reg &= ~AUX_FUNC_EN_N;
370 writel(reg, &dp_regs->func_en2);
375 void exynos_dp_config_interrupt(struct exynos_dp *dp_regs)
379 /* 0: mask, 1: unmask */
380 reg = COMMON_INT_MASK_1;
381 writel(reg, &dp_regs->common_int_mask1);
383 reg = COMMON_INT_MASK_2;
384 writel(reg, &dp_regs->common_int_mask2);
386 reg = COMMON_INT_MASK_3;
387 writel(reg, &dp_regs->common_int_mask3);
389 reg = COMMON_INT_MASK_4;
390 writel(reg, &dp_regs->common_int_mask4);
393 writel(reg, &dp_regs->int_sta_mask);
398 unsigned int exynos_dp_get_plug_in_status(struct exynos_dp *dp_regs)
402 reg = readl(&dp_regs->sys_ctl3);
403 if (reg & HPD_STATUS)
409 unsigned int exynos_dp_detect_hpd(struct exynos_dp *dp_regs)
411 int timeout_loop = DP_TIMEOUT_LOOP_COUNT;
415 while (exynos_dp_get_plug_in_status(dp_regs) != 0) {
416 if (timeout_loop == 0)
422 return EXYNOS_DP_SUCCESS;
425 unsigned int exynos_dp_start_aux_transaction(struct exynos_dp *dp_regs)
428 unsigned int ret = 0;
429 unsigned int retry_cnt;
431 /* Enable AUX CH operation */
432 reg = readl(&dp_regs->aux_ch_ctl2);
434 writel(reg, &dp_regs->aux_ch_ctl2);
438 reg = readl(&dp_regs->int_sta);
439 if (!(reg & RPLY_RECEIV)) {
440 if (retry_cnt == 0) {
441 printf("DP Reply Timeout!!\n");
451 /* Clear interrupt source for AUX CH command reply */
452 writel(reg, &dp_regs->int_sta);
454 /* Clear interrupt source for AUX CH access error */
455 reg = readl(&dp_regs->int_sta);
457 printf("DP Aux Access Error\n");
458 writel(AUX_ERR, &dp_regs->int_sta);
463 /* Check AUX CH error access status */
464 reg = readl(&dp_regs->aux_ch_sta);
465 if ((reg & AUX_STATUS_MASK) != 0) {
466 debug("DP AUX CH error happens: %x\n", reg & AUX_STATUS_MASK);
471 return EXYNOS_DP_SUCCESS;
474 unsigned int exynos_dp_write_byte_to_dpcd(struct exynos_dp *dp_regs,
475 unsigned int reg_addr,
478 unsigned int reg, ret;
480 /* Clear AUX CH data buffer */
482 writel(reg, &dp_regs->buffer_data_ctl);
484 /* Select DPCD device address */
485 reg = AUX_ADDR_7_0(reg_addr);
486 writel(reg, &dp_regs->aux_addr_7_0);
487 reg = AUX_ADDR_15_8(reg_addr);
488 writel(reg, &dp_regs->aux_addr_15_8);
489 reg = AUX_ADDR_19_16(reg_addr);
490 writel(reg, &dp_regs->aux_addr_19_16);
492 /* Write data buffer */
493 reg = (unsigned int)data;
494 writel(reg, &dp_regs->buf_data0);
497 * Set DisplayPort transaction and write 1 byte
498 * If bit 3 is 1, DisplayPort transaction.
499 * If Bit 3 is 0, I2C transaction.
501 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
502 writel(reg, &dp_regs->aux_ch_ctl1);
504 /* Start AUX transaction */
505 ret = exynos_dp_start_aux_transaction(dp_regs);
506 if (ret != EXYNOS_DP_SUCCESS) {
507 printf("DP Aux transaction failed\n");
514 unsigned int exynos_dp_read_byte_from_dpcd(struct exynos_dp *dp_regs,
515 unsigned int reg_addr,
521 /* Clear AUX CH data buffer */
523 writel(reg, &dp_regs->buffer_data_ctl);
525 /* Select DPCD device address */
526 reg = AUX_ADDR_7_0(reg_addr);
527 writel(reg, &dp_regs->aux_addr_7_0);
528 reg = AUX_ADDR_15_8(reg_addr);
529 writel(reg, &dp_regs->aux_addr_15_8);
530 reg = AUX_ADDR_19_16(reg_addr);
531 writel(reg, &dp_regs->aux_addr_19_16);
534 * Set DisplayPort transaction and read 1 byte
535 * If bit 3 is 1, DisplayPort transaction.
536 * If Bit 3 is 0, I2C transaction.
538 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
539 writel(reg, &dp_regs->aux_ch_ctl1);
541 /* Start AUX transaction */
542 retval = exynos_dp_start_aux_transaction(dp_regs);
544 debug("DP Aux Transaction fail!\n");
546 /* Read data buffer */
547 reg = readl(&dp_regs->buf_data0);
548 *data = (unsigned char)(reg & 0xff);
553 unsigned int exynos_dp_write_bytes_to_dpcd(struct exynos_dp *dp_regs,
554 unsigned int reg_addr,
556 unsigned char data[])
559 unsigned int start_offset;
560 unsigned int cur_data_count;
561 unsigned int cur_data_idx;
562 unsigned int retry_cnt;
563 unsigned int ret = 0;
565 /* Clear AUX CH data buffer */
567 writel(reg, &dp_regs->buffer_data_ctl);
570 while (start_offset < count) {
571 /* Buffer size of AUX CH is 16 * 4bytes */
572 if ((count - start_offset) > 16)
575 cur_data_count = count - start_offset;
579 /* Select DPCD device address */
580 reg = AUX_ADDR_7_0(reg_addr + start_offset);
581 writel(reg, &dp_regs->aux_addr_7_0);
582 reg = AUX_ADDR_15_8(reg_addr + start_offset);
583 writel(reg, &dp_regs->aux_addr_15_8);
584 reg = AUX_ADDR_19_16(reg_addr + start_offset);
585 writel(reg, &dp_regs->aux_addr_19_16);
587 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
589 reg = data[start_offset + cur_data_idx];
590 writel(reg, (unsigned int)&dp_regs->buf_data0 +
594 * Set DisplayPort transaction and write
595 * If bit 3 is 1, DisplayPort transaction.
596 * If Bit 3 is 0, I2C transaction.
598 reg = AUX_LENGTH(cur_data_count) |
599 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
600 writel(reg, &dp_regs->aux_ch_ctl1);
602 /* Start AUX transaction */
603 ret = exynos_dp_start_aux_transaction(dp_regs);
604 if (ret != EXYNOS_DP_SUCCESS) {
605 if (retry_cnt == 0) {
606 printf("DP Aux Transaction failed\n");
613 start_offset += cur_data_count;
619 unsigned int exynos_dp_read_bytes_from_dpcd(struct exynos_dp *dp_regs,
620 unsigned int reg_addr,
622 unsigned char data[])
625 unsigned int start_offset;
626 unsigned int cur_data_count;
627 unsigned int cur_data_idx;
628 unsigned int retry_cnt;
629 unsigned int ret = 0;
631 /* Clear AUX CH data buffer */
633 writel(reg, &dp_regs->buffer_data_ctl);
636 while (start_offset < count) {
637 /* Buffer size of AUX CH is 16 * 4bytes */
638 if ((count - start_offset) > 16)
641 cur_data_count = count - start_offset;
645 /* Select DPCD device address */
646 reg = AUX_ADDR_7_0(reg_addr + start_offset);
647 writel(reg, &dp_regs->aux_addr_7_0);
648 reg = AUX_ADDR_15_8(reg_addr + start_offset);
649 writel(reg, &dp_regs->aux_addr_15_8);
650 reg = AUX_ADDR_19_16(reg_addr + start_offset);
651 writel(reg, &dp_regs->aux_addr_19_16);
653 * Set DisplayPort transaction and read
654 * If bit 3 is 1, DisplayPort transaction.
655 * If Bit 3 is 0, I2C transaction.
657 reg = AUX_LENGTH(cur_data_count) |
658 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
659 writel(reg, &dp_regs->aux_ch_ctl1);
661 /* Start AUX transaction */
662 ret = exynos_dp_start_aux_transaction(dp_regs);
663 if (ret != EXYNOS_DP_SUCCESS) {
664 if (retry_cnt == 0) {
665 printf("DP Aux Transaction failed\n");
673 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
675 reg = readl((unsigned int)&dp_regs->buf_data0 +
677 data[start_offset + cur_data_idx] = (unsigned char)reg;
680 start_offset += cur_data_count;
686 int exynos_dp_select_i2c_device(struct exynos_dp *dp_regs,
687 unsigned int device_addr, unsigned int reg_addr)
692 /* Set EDID device address */
694 writel(reg, &dp_regs->aux_addr_7_0);
695 writel(0x0, &dp_regs->aux_addr_15_8);
696 writel(0x0, &dp_regs->aux_addr_19_16);
698 /* Set offset from base address of EDID device */
699 writel(reg_addr, &dp_regs->buf_data0);
702 * Set I2C transaction and write address
703 * If bit 3 is 1, DisplayPort transaction.
704 * If Bit 3 is 0, I2C transaction.
706 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
708 writel(reg, &dp_regs->aux_ch_ctl1);
710 /* Start AUX transaction */
711 retval = exynos_dp_start_aux_transaction(dp_regs);
713 printf("%s: DP Aux Transaction fail!\n", __func__);
718 int exynos_dp_read_byte_from_i2c(struct exynos_dp *dp_regs,
719 unsigned int device_addr,
720 unsigned int reg_addr, unsigned int *data)
726 for (i = 0; i < 10; i++) {
727 /* Clear AUX CH data buffer */
729 writel(reg, &dp_regs->buffer_data_ctl);
731 /* Select EDID device */
732 retval = exynos_dp_select_i2c_device(dp_regs, device_addr,
735 printf("DP Select EDID device fail. retry !\n");
740 * Set I2C transaction and read data
741 * If bit 3 is 1, DisplayPort transaction.
742 * If Bit 3 is 0, I2C transaction.
744 reg = AUX_TX_COMM_I2C_TRANSACTION |
746 writel(reg, &dp_regs->aux_ch_ctl1);
748 /* Start AUX transaction */
749 retval = exynos_dp_start_aux_transaction(dp_regs);
750 if (retval != EXYNOS_DP_SUCCESS)
751 printf("%s: DP Aux Transaction fail!\n", __func__);
756 *data = readl(&dp_regs->buf_data0);
761 int exynos_dp_read_bytes_from_i2c(struct exynos_dp *dp_regs,
762 unsigned int device_addr,
763 unsigned int reg_addr, unsigned int count,
764 unsigned char edid[])
768 unsigned int cur_data_idx;
769 unsigned int defer = 0;
772 for (i = 0; i < count; i += 16) { /* use 16 burst */
773 for (j = 0; j < 100; j++) {
774 /* Clear AUX CH data buffer */
776 writel(reg, &dp_regs->buffer_data_ctl);
778 /* Set normal AUX CH command */
779 reg = readl(&dp_regs->aux_ch_ctl2);
781 writel(reg, &dp_regs->aux_ch_ctl2);
784 * If Rx sends defer, Tx sends only reads
785 * request without sending addres
788 retval = exynos_dp_select_i2c_device(
789 dp_regs, device_addr, reg_addr + i);
793 if (retval == EXYNOS_DP_SUCCESS) {
795 * Set I2C transaction and write data
796 * If bit 3 is 1, DisplayPort transaction.
797 * If Bit 3 is 0, I2C transaction.
799 reg = AUX_LENGTH(16) |
800 AUX_TX_COMM_I2C_TRANSACTION |
802 writel(reg, &dp_regs->aux_ch_ctl1);
804 /* Start AUX transaction */
805 retval = exynos_dp_start_aux_transaction(
810 printf("DP Aux Transaction fail!\n");
812 /* Check if Rx sends defer */
813 reg = readl(&dp_regs->aux_rx_comm);
814 if (reg == AUX_RX_COMM_AUX_DEFER ||
815 reg == AUX_RX_COMM_I2C_DEFER) {
816 printf("DP Defer: %d\n", reg);
821 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
822 reg = readl((unsigned int)&dp_regs->buf_data0
824 edid[i + cur_data_idx] = (unsigned char)reg;
831 void exynos_dp_reset_macro(struct exynos_dp *dp_regs)
835 reg = readl(&dp_regs->phy_test);
837 writel(reg, &dp_regs->phy_test);
839 /* 10 us is the minimum Macro reset time. */
843 writel(reg, &dp_regs->phy_test);
846 void exynos_dp_set_link_bandwidth(struct exynos_dp *dp_regs,
847 unsigned char bwtype)
851 reg = (unsigned int)bwtype;
853 /* Set bandwidth to 2.7G or 1.62G */
854 if ((bwtype == DP_LANE_BW_1_62) || (bwtype == DP_LANE_BW_2_70))
855 writel(reg, &dp_regs->link_bw_set);
858 unsigned char exynos_dp_get_link_bandwidth(struct exynos_dp *dp_regs)
863 reg = readl(&dp_regs->link_bw_set);
864 ret = (unsigned char)reg;
869 void exynos_dp_set_lane_count(struct exynos_dp *dp_regs, unsigned char count)
873 reg = (unsigned int)count;
875 if ((count == DP_LANE_CNT_1) || (count == DP_LANE_CNT_2) ||
876 (count == DP_LANE_CNT_4))
877 writel(reg, &dp_regs->lane_count_set);
880 unsigned int exynos_dp_get_lane_count(struct exynos_dp *dp_regs)
882 return readl(&dp_regs->lane_count_set);
885 unsigned char exynos_dp_get_lanex_pre_emphasis(struct exynos_dp *dp_regs,
886 unsigned char lanecnt)
888 unsigned int reg_list[DP_LANE_CNT_4] = {
889 (unsigned int)&dp_regs->ln0_link_training_ctl,
890 (unsigned int)&dp_regs->ln1_link_training_ctl,
891 (unsigned int)&dp_regs->ln2_link_training_ctl,
892 (unsigned int)&dp_regs->ln3_link_training_ctl,
895 return readl(reg_list[lanecnt]);
898 void exynos_dp_set_lanex_pre_emphasis(struct exynos_dp *dp_regs,
899 unsigned char request_val,
900 unsigned char lanecnt)
902 unsigned int reg_list[DP_LANE_CNT_4] = {
903 (unsigned int)&dp_regs->ln0_link_training_ctl,
904 (unsigned int)&dp_regs->ln1_link_training_ctl,
905 (unsigned int)&dp_regs->ln2_link_training_ctl,
906 (unsigned int)&dp_regs->ln3_link_training_ctl,
909 writel(request_val, reg_list[lanecnt]);
912 void exynos_dp_set_lane_pre_emphasis(struct exynos_dp *dp_regs,
913 unsigned int level, unsigned char lanecnt)
917 unsigned int reg_list[DP_LANE_CNT_4] = {
918 (unsigned int)&dp_regs->ln0_link_training_ctl,
919 (unsigned int)&dp_regs->ln1_link_training_ctl,
920 (unsigned int)&dp_regs->ln2_link_training_ctl,
921 (unsigned int)&dp_regs->ln3_link_training_ctl,
923 unsigned int reg_shift[DP_LANE_CNT_4] = {
924 PRE_EMPHASIS_SET_0_SHIFT,
925 PRE_EMPHASIS_SET_1_SHIFT,
926 PRE_EMPHASIS_SET_2_SHIFT,
927 PRE_EMPHASIS_SET_3_SHIFT
930 for (i = 0; i < lanecnt; i++) {
931 reg = level << reg_shift[i];
932 writel(reg, reg_list[i]);
936 void exynos_dp_set_training_pattern(struct exynos_dp *dp_regs,
937 unsigned int pattern)
939 unsigned int reg = 0;
943 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
946 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
949 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
952 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
955 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_DISABLE |
956 SW_TRAINING_PATTERN_SET_NORMAL;
962 writel(reg, &dp_regs->training_ptn_set);
965 void exynos_dp_enable_enhanced_mode(struct exynos_dp *dp_regs,
966 unsigned char enable)
970 reg = readl(&dp_regs->sys_ctl4);
976 writel(reg, &dp_regs->sys_ctl4);
979 void exynos_dp_enable_scrambling(struct exynos_dp *dp_regs, unsigned int enable)
983 reg = readl(&dp_regs->training_ptn_set);
984 reg &= ~(SCRAMBLING_DISABLE);
987 reg |= SCRAMBLING_DISABLE;
989 writel(reg, &dp_regs->training_ptn_set);
992 int exynos_dp_init_video(struct exynos_dp *dp_regs)
996 /* Clear VID_CLK_CHG[1] and VID_FORMAT_CHG[3] and VSYNC_DET[7] */
997 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
998 writel(reg, &dp_regs->common_int_sta1);
1000 /* I_STRM__CLK detect : DE_CTL : Auto detect */
1002 writel(reg, &dp_regs->sys_ctl1);
1007 void exynos_dp_config_video_slave_mode(struct exynos_dp *dp_regs,
1008 struct edp_video_info *video_info)
1012 /* Video Slave mode setting */
1013 reg = readl(&dp_regs->func_en1);
1014 reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
1015 reg |= MASTER_VID_FUNC_EN_N;
1016 writel(reg, &dp_regs->func_en1);
1018 /* Configure Interlaced for slave mode video */
1019 reg = readl(&dp_regs->video_ctl10);
1020 reg &= ~INTERACE_SCAN_CFG;
1021 reg |= (video_info->interlaced << INTERACE_SCAN_CFG_SHIFT);
1022 writel(reg, &dp_regs->video_ctl10);
1024 /* Configure V sync polarity for slave mode video */
1025 reg = readl(&dp_regs->video_ctl10);
1026 reg &= ~VSYNC_POLARITY_CFG;
1027 reg |= (video_info->v_sync_polarity << V_S_POLARITY_CFG_SHIFT);
1028 writel(reg, &dp_regs->video_ctl10);
1030 /* Configure H sync polarity for slave mode video */
1031 reg = readl(&dp_regs->video_ctl10);
1032 reg &= ~HSYNC_POLARITY_CFG;
1033 reg |= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
1034 writel(reg, &dp_regs->video_ctl10);
1036 /* Set video mode to slave mode */
1037 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1038 writel(reg, &dp_regs->soc_general_ctl);
1041 void exynos_dp_set_video_color_format(struct exynos_dp *dp_regs,
1042 struct edp_video_info *video_info)
1046 /* Configure the input color depth, color space, dynamic range */
1047 reg = (video_info->dynamic_range << IN_D_RANGE_SHIFT) |
1048 (video_info->color_depth << IN_BPC_SHIFT) |
1049 (video_info->color_space << IN_COLOR_F_SHIFT);
1050 writel(reg, &dp_regs->video_ctl2);
1052 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1053 reg = readl(&dp_regs->video_ctl3);
1054 reg &= ~IN_YC_COEFFI_MASK;
1055 if (video_info->ycbcr_coeff)
1056 reg |= IN_YC_COEFFI_ITU709;
1058 reg |= IN_YC_COEFFI_ITU601;
1059 writel(reg, &dp_regs->video_ctl3);
1062 int exynos_dp_config_video_bist(struct exynos_dp *dp_regs,
1063 struct exynos_dp_priv *priv)
1066 unsigned int bist_type = 0;
1067 struct edp_video_info video_info = priv->video_info;
1069 /* For master mode, you don't need to set the video format */
1070 if (video_info.master_mode == 0) {
1071 writel(TOTAL_LINE_CFG_L(priv->disp_info.v_total),
1072 &dp_regs->total_ln_cfg_l);
1073 writel(TOTAL_LINE_CFG_H(priv->disp_info.v_total),
1074 &dp_regs->total_ln_cfg_h);
1075 writel(ACTIVE_LINE_CFG_L(priv->disp_info.v_res),
1076 &dp_regs->active_ln_cfg_l);
1077 writel(ACTIVE_LINE_CFG_H(priv->disp_info.v_res),
1078 &dp_regs->active_ln_cfg_h);
1079 writel(priv->disp_info.v_sync_width, &dp_regs->vsw_cfg);
1080 writel(priv->disp_info.v_back_porch, &dp_regs->vbp_cfg);
1081 writel(priv->disp_info.v_front_porch, &dp_regs->vfp_cfg);
1083 writel(TOTAL_PIXEL_CFG_L(priv->disp_info.h_total),
1084 &dp_regs->total_pix_cfg_l);
1085 writel(TOTAL_PIXEL_CFG_H(priv->disp_info.h_total),
1086 &dp_regs->total_pix_cfg_h);
1087 writel(ACTIVE_PIXEL_CFG_L(priv->disp_info.h_res),
1088 &dp_regs->active_pix_cfg_l);
1089 writel(ACTIVE_PIXEL_CFG_H(priv->disp_info.h_res),
1090 &dp_regs->active_pix_cfg_h);
1091 writel(H_F_PORCH_CFG_L(priv->disp_info.h_front_porch),
1092 &dp_regs->hfp_cfg_l);
1093 writel(H_F_PORCH_CFG_H(priv->disp_info.h_front_porch),
1094 &dp_regs->hfp_cfg_h);
1095 writel(H_SYNC_PORCH_CFG_L(priv->disp_info.h_sync_width),
1096 &dp_regs->hsw_cfg_l);
1097 writel(H_SYNC_PORCH_CFG_H(priv->disp_info.h_sync_width),
1098 &dp_regs->hsw_cfg_h);
1099 writel(H_B_PORCH_CFG_L(priv->disp_info.h_back_porch),
1100 &dp_regs->hbp_cfg_l);
1101 writel(H_B_PORCH_CFG_H(priv->disp_info.h_back_porch),
1102 &dp_regs->hbp_cfg_h);
1105 * Set SLAVE_I_SCAN_CFG[2], VSYNC_P_CFG[1],
1106 * HSYNC_P_CFG[0] properly
1108 reg = (video_info.interlaced << INTERACE_SCAN_CFG_SHIFT |
1109 video_info.v_sync_polarity << V_S_POLARITY_CFG_SHIFT |
1110 video_info.h_sync_polarity << H_S_POLARITY_CFG_SHIFT);
1111 writel(reg, &dp_regs->video_ctl10);
1114 /* BIST color bar width set--set to each bar is 32 pixel width */
1115 switch (video_info.bist_pattern) {
1117 bist_type = BIST_WIDTH_BAR_32_PIXEL |
1118 BIST_TYPE_COLOR_BAR;
1121 bist_type = BIST_WIDTH_BAR_64_PIXEL |
1122 BIST_TYPE_COLOR_BAR;
1124 case WHITE_GRAY_BALCKBAR_32:
1125 bist_type = BIST_WIDTH_BAR_32_PIXEL |
1126 BIST_TYPE_WHITE_GRAY_BLACK_BAR;
1128 case WHITE_GRAY_BALCKBAR_64:
1129 bist_type = BIST_WIDTH_BAR_64_PIXEL |
1130 BIST_TYPE_WHITE_GRAY_BLACK_BAR;
1132 case MOBILE_WHITEBAR_32:
1133 bist_type = BIST_WIDTH_BAR_32_PIXEL |
1134 BIST_TYPE_MOBILE_WHITE_BAR;
1136 case MOBILE_WHITEBAR_64:
1137 bist_type = BIST_WIDTH_BAR_64_PIXEL |
1138 BIST_TYPE_MOBILE_WHITE_BAR;
1145 writel(reg, &dp_regs->video_ctl4);
1150 unsigned int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp *dp_regs)
1154 /* Update Video stream clk detect status */
1155 reg = readl(&dp_regs->sys_ctl1);
1156 writel(reg, &dp_regs->sys_ctl1);
1158 reg = readl(&dp_regs->sys_ctl1);
1160 if (!(reg & DET_STA)) {
1161 debug("DP Input stream clock not detected.\n");
1165 return EXYNOS_DP_SUCCESS;
1168 void exynos_dp_set_video_cr_mn(struct exynos_dp *dp_regs, unsigned int type,
1169 unsigned int m_value, unsigned int n_value)
1173 if (type == REGISTER_M) {
1174 reg = readl(&dp_regs->sys_ctl4);
1176 writel(reg, &dp_regs->sys_ctl4);
1177 reg = M_VID0_CFG(m_value);
1178 writel(reg, &dp_regs->m_vid0);
1179 reg = M_VID1_CFG(m_value);
1180 writel(reg, &dp_regs->m_vid1);
1181 reg = M_VID2_CFG(m_value);
1182 writel(reg, &dp_regs->m_vid2);
1184 reg = N_VID0_CFG(n_value);
1185 writel(reg, &dp_regs->n_vid0);
1186 reg = N_VID1_CFG(n_value);
1187 writel(reg, &dp_regs->n_vid1);
1188 reg = N_VID2_CFG(n_value);
1189 writel(reg, &dp_regs->n_vid2);
1191 reg = readl(&dp_regs->sys_ctl4);
1193 writel(reg, &dp_regs->sys_ctl4);
1197 void exynos_dp_set_video_timing_mode(struct exynos_dp *dp_regs,
1202 reg = readl(&dp_regs->video_ctl10);
1205 if (type != VIDEO_TIMING_FROM_CAPTURE)
1208 writel(reg, &dp_regs->video_ctl10);
1211 void exynos_dp_enable_video_master(struct exynos_dp *dp_regs,
1212 unsigned int enable)
1216 reg = readl(&dp_regs->soc_general_ctl);
1218 reg &= ~VIDEO_MODE_MASK;
1219 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1221 reg &= ~VIDEO_MODE_MASK;
1222 reg |= VIDEO_MODE_SLAVE_MODE;
1225 writel(reg, &dp_regs->soc_general_ctl);
1228 void exynos_dp_start_video(struct exynos_dp *dp_regs)
1232 /* Enable Video input and disable Mute */
1233 reg = readl(&dp_regs->video_ctl1);
1235 writel(reg, &dp_regs->video_ctl1);
1238 unsigned int exynos_dp_is_video_stream_on(struct exynos_dp *dp_regs)
1242 /* Update STRM_VALID */
1243 reg = readl(&dp_regs->sys_ctl3);
1244 writel(reg, &dp_regs->sys_ctl3);
1246 reg = readl(&dp_regs->sys_ctl3);
1247 if (!(reg & STRM_VALID))
1250 return EXYNOS_DP_SUCCESS;