1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016, Fuzhou Rockchip Electronics Co., Ltd
4 * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
5 * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
6 * Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
8 * This generic Synopsys DesignWare MIPI DSI host driver is inspired from
9 * the Linux Kernel driver drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c.
20 #include <asm/arch/gpio.h>
21 #include <dm/device-internal.h>
22 #include <linux/iopoll.h>
23 #include <video_bridge.h>
25 #define HWVER_131 0x31333100 /* IP version 1.31 */
27 #define DSI_VERSION 0x00
28 #define VERSION GENMASK(31, 8)
30 #define DSI_PWR_UP 0x04
32 #define POWERUP BIT(0)
34 #define DSI_CLKMGR_CFG 0x08
35 #define TO_CLK_DIVISION(div) (((div) & 0xff) << 8)
36 #define TX_ESC_CLK_DIVISION(div) ((div) & 0xff)
38 #define DSI_DPI_VCID 0x0c
39 #define DPI_VCID(vcid) ((vcid) & 0x3)
41 #define DSI_DPI_COLOR_CODING 0x10
42 #define LOOSELY18_EN BIT(8)
43 #define DPI_COLOR_CODING_16BIT_1 0x0
44 #define DPI_COLOR_CODING_16BIT_2 0x1
45 #define DPI_COLOR_CODING_16BIT_3 0x2
46 #define DPI_COLOR_CODING_18BIT_1 0x3
47 #define DPI_COLOR_CODING_18BIT_2 0x4
48 #define DPI_COLOR_CODING_24BIT 0x5
50 #define DSI_DPI_CFG_POL 0x14
51 #define COLORM_ACTIVE_LOW BIT(4)
52 #define SHUTD_ACTIVE_LOW BIT(3)
53 #define HSYNC_ACTIVE_LOW BIT(2)
54 #define VSYNC_ACTIVE_LOW BIT(1)
55 #define DATAEN_ACTIVE_LOW BIT(0)
57 #define DSI_DPI_LP_CMD_TIM 0x18
58 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16)
59 #define INVACT_LPCMD_TIME(p) ((p) & 0xff)
61 #define DSI_DBI_VCID 0x1c
62 #define DSI_DBI_CFG 0x20
63 #define DSI_DBI_PARTITIONING_EN 0x24
64 #define DSI_DBI_CMDSIZE 0x28
66 #define DSI_PCKHDL_CFG 0x2c
67 #define CRC_RX_EN BIT(4)
68 #define ECC_RX_EN BIT(3)
70 #define EOTP_RX_EN BIT(1)
71 #define EOTP_TX_EN BIT(0)
73 #define DSI_GEN_VCID 0x30
75 #define DSI_MODE_CFG 0x34
76 #define ENABLE_VIDEO_MODE 0
77 #define ENABLE_CMD_MODE BIT(0)
79 #define DSI_VID_MODE_CFG 0x38
80 #define ENABLE_LOW_POWER (0x3f << 8)
81 #define ENABLE_LOW_POWER_MASK (0x3f << 8)
82 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0
83 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1
84 #define VID_MODE_TYPE_BURST 0x2
85 #define VID_MODE_TYPE_MASK 0x3
87 #define DSI_VID_PKT_SIZE 0x3c
88 #define VID_PKT_SIZE(p) ((p) & 0x3fff)
90 #define DSI_VID_NUM_CHUNKS 0x40
91 #define VID_NUM_CHUNKS(c) ((c) & 0x1fff)
93 #define DSI_VID_NULL_SIZE 0x44
94 #define VID_NULL_SIZE(b) ((b) & 0x1fff)
96 #define DSI_VID_HSA_TIME 0x48
97 #define DSI_VID_HBP_TIME 0x4c
98 #define DSI_VID_HLINE_TIME 0x50
99 #define DSI_VID_VSA_LINES 0x54
100 #define DSI_VID_VBP_LINES 0x58
101 #define DSI_VID_VFP_LINES 0x5c
102 #define DSI_VID_VACTIVE_LINES 0x60
103 #define DSI_EDPI_CMD_SIZE 0x64
105 #define DSI_CMD_MODE_CFG 0x68
106 #define MAX_RD_PKT_SIZE_LP BIT(24)
107 #define DCS_LW_TX_LP BIT(19)
108 #define DCS_SR_0P_TX_LP BIT(18)
109 #define DCS_SW_1P_TX_LP BIT(17)
110 #define DCS_SW_0P_TX_LP BIT(16)
111 #define GEN_LW_TX_LP BIT(14)
112 #define GEN_SR_2P_TX_LP BIT(13)
113 #define GEN_SR_1P_TX_LP BIT(12)
114 #define GEN_SR_0P_TX_LP BIT(11)
115 #define GEN_SW_2P_TX_LP BIT(10)
116 #define GEN_SW_1P_TX_LP BIT(9)
117 #define GEN_SW_0P_TX_LP BIT(8)
118 #define ACK_RQST_EN BIT(1)
119 #define TEAR_FX_EN BIT(0)
121 #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
134 #define DSI_GEN_HDR 0x6c
135 #define DSI_GEN_PLD_DATA 0x70
137 #define DSI_CMD_PKT_STATUS 0x74
138 #define GEN_RD_CMD_BUSY BIT(6)
139 #define GEN_PLD_R_FULL BIT(5)
140 #define GEN_PLD_R_EMPTY BIT(4)
141 #define GEN_PLD_W_FULL BIT(3)
142 #define GEN_PLD_W_EMPTY BIT(2)
143 #define GEN_CMD_FULL BIT(1)
144 #define GEN_CMD_EMPTY BIT(0)
146 #define DSI_TO_CNT_CFG 0x78
147 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16)
148 #define LPRX_TO_CNT(p) ((p) & 0xffff)
150 #define DSI_HS_RD_TO_CNT 0x7c
151 #define DSI_LP_RD_TO_CNT 0x80
152 #define DSI_HS_WR_TO_CNT 0x84
153 #define DSI_LP_WR_TO_CNT 0x88
154 #define DSI_BTA_TO_CNT 0x8c
156 #define DSI_LPCLK_CTRL 0x94
157 #define AUTO_CLKLANE_CTRL BIT(1)
158 #define PHY_TXREQUESTCLKHS BIT(0)
160 #define DSI_PHY_TMR_LPCLK_CFG 0x98
161 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
162 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
164 #define DSI_PHY_TMR_CFG 0x9c
165 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24)
166 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16)
167 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
168 #define PHY_HS2LP_TIME_V131(lbcc) (((lbcc) & 0x3ff) << 16)
169 #define PHY_LP2HS_TIME_V131(lbcc) ((lbcc) & 0x3ff)
171 #define DSI_PHY_RSTZ 0xa0
172 #define PHY_DISFORCEPLL 0
173 #define PHY_ENFORCEPLL BIT(3)
174 #define PHY_DISABLECLK 0
175 #define PHY_ENABLECLK BIT(2)
177 #define PHY_UNRSTZ BIT(1)
178 #define PHY_SHUTDOWNZ 0
179 #define PHY_UNSHUTDOWNZ BIT(0)
181 #define DSI_PHY_IF_CFG 0xa4
182 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
183 #define N_LANES(n) (((n) - 1) & 0x3)
185 #define DSI_PHY_ULPS_CTRL 0xa8
186 #define DSI_PHY_TX_TRIGGERS 0xac
188 #define DSI_PHY_STATUS 0xb0
189 #define PHY_STOP_STATE_CLK_LANE BIT(2)
190 #define PHY_LOCK BIT(0)
192 #define DSI_PHY_TST_CTRL0 0xb4
193 #define PHY_TESTCLK BIT(1)
194 #define PHY_UNTESTCLK 0
195 #define PHY_TESTCLR BIT(0)
196 #define PHY_UNTESTCLR 0
198 #define DSI_PHY_TST_CTRL1 0xb8
199 #define PHY_TESTEN BIT(16)
200 #define PHY_UNTESTEN 0
201 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
202 #define PHY_TESTDIN(n) ((n) & 0xff)
204 #define DSI_INT_ST0 0xbc
205 #define DSI_INT_ST1 0xc0
206 #define DSI_INT_MSK0 0xc4
207 #define DSI_INT_MSK1 0xc8
209 #define DSI_PHY_TMR_RD_CFG 0xf4
210 #define MAX_RD_TIME_V131(lbcc) ((lbcc) & 0x7fff)
212 #define PHY_STATUS_TIMEOUT_US 10000
213 #define CMD_PKT_STATUS_TIMEOUT_US 20000
215 #define MSEC_PER_SEC 1000
218 struct mipi_dsi_host dsi_host;
219 struct mipi_dsi_device *device;
221 unsigned int lane_mbps; /* per lane */
223 unsigned int max_data_lanes;
224 const struct mipi_dsi_phy_ops *phy_ops;
227 static int dsi_mode_vrefresh(struct display_timing *timings)
230 unsigned int calc_val;
231 u32 htotal = timings->hactive.typ + timings->hfront_porch.typ +
232 timings->hback_porch.typ + timings->hsync_len.typ;
233 u32 vtotal = timings->vactive.typ + timings->vfront_porch.typ +
234 timings->vback_porch.typ + timings->vsync_len.typ;
236 if (htotal > 0 && vtotal > 0) {
237 calc_val = timings->pixelclock.typ;
239 refresh = (calc_val + vtotal / 2) / vtotal;
246 * The controller should generate 2 frames before
247 * preparing the peripheral.
249 static void dw_mipi_dsi_wait_for_two_frames(struct display_timing *timings)
251 int refresh, two_frames;
253 refresh = dsi_mode_vrefresh(timings);
254 two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
258 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
260 return container_of(host, struct dw_mipi_dsi, dsi_host);
263 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
265 writel(val, dsi->base + reg);
268 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
270 return readl(dsi->base + reg);
273 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
274 struct mipi_dsi_device *device)
276 struct dw_mipi_dsi *dsi = host_to_dsi(host);
278 if (device->lanes > dsi->max_data_lanes) {
280 "the number of data lanes(%u) is too many\n",
285 dsi->channel = device->channel;
290 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
291 const struct mipi_dsi_msg *msg)
293 bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
296 if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
299 val |= CMD_MODE_ALL_LP;
301 dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
302 dsi_write(dsi, DSI_CMD_MODE_CFG, val);
305 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
310 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
311 val, !(val & GEN_CMD_FULL),
312 CMD_PKT_STATUS_TIMEOUT_US);
314 dev_err(dsi->dev, "failed to get available command FIFO\n");
318 dsi_write(dsi, DSI_GEN_HDR, hdr_val);
320 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
321 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
322 val, (val & mask) == mask,
323 CMD_PKT_STATUS_TIMEOUT_US);
325 dev_err(dsi->dev, "failed to write command FIFO\n");
332 static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
333 const struct mipi_dsi_packet *packet)
335 const u8 *tx_buf = packet->payload;
336 int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
341 if (len < pld_data_bytes) {
343 memcpy(&word, tx_buf, len);
344 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
347 memcpy(&word, tx_buf, pld_data_bytes);
348 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
349 tx_buf += pld_data_bytes;
350 len -= pld_data_bytes;
353 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
354 val, !(val & GEN_PLD_W_FULL),
355 CMD_PKT_STATUS_TIMEOUT_US);
358 "failed to get available write payload FIFO\n");
364 memcpy(&word, packet->header, sizeof(packet->header));
365 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word));
368 static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
369 const struct mipi_dsi_msg *msg)
371 int i, j, ret, len = msg->rx_len;
372 u8 *buf = msg->rx_buf;
375 /* Wait end of the read operation */
376 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
377 val, !(val & GEN_RD_CMD_BUSY),
378 CMD_PKT_STATUS_TIMEOUT_US);
380 dev_err(dsi->dev, "Timeout during read operation\n");
384 for (i = 0; i < len; i += 4) {
385 /* Read fifo must not be empty before all bytes are read */
386 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
387 val, !(val & GEN_PLD_R_EMPTY),
388 CMD_PKT_STATUS_TIMEOUT_US);
390 dev_err(dsi->dev, "Read payload FIFO is empty\n");
394 val = dsi_read(dsi, DSI_GEN_PLD_DATA);
395 for (j = 0; j < 4 && j + i < len; j++)
396 buf[i + j] = val >> (8 * j);
402 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
403 const struct mipi_dsi_msg *msg)
405 struct dw_mipi_dsi *dsi = host_to_dsi(host);
406 struct mipi_dsi_packet packet;
409 ret = mipi_dsi_create_packet(&packet, msg);
411 dev_err(dsi->dev, "failed to create packet: %d\n", ret);
415 dw_mipi_message_config(dsi, msg);
417 ret = dw_mipi_dsi_write(dsi, &packet);
421 if (msg->rx_buf && msg->rx_len) {
422 ret = dw_mipi_dsi_read(dsi, msg);
425 nb_bytes = msg->rx_len;
427 nb_bytes = packet.size;
433 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
434 .attach = dw_mipi_dsi_host_attach,
435 .transfer = dw_mipi_dsi_host_transfer,
438 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
440 struct mipi_dsi_device *device = dsi->device;
444 * TODO dw drv improvements
445 * enabling low power is panel-dependent, we should use the
446 * panel configuration here...
448 val = ENABLE_LOW_POWER;
450 if (device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
451 val |= VID_MODE_TYPE_BURST;
452 else if (device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
453 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
455 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
457 dsi_write(dsi, DSI_VID_MODE_CFG, val);
460 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
461 unsigned long mode_flags)
463 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
465 dsi_write(dsi, DSI_PWR_UP, RESET);
467 if (mode_flags & MIPI_DSI_MODE_VIDEO) {
468 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
469 dw_mipi_dsi_video_mode_config(dsi);
470 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
472 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
475 if (phy_ops->post_set_mode)
476 phy_ops->post_set_mode(dsi->device, mode_flags);
478 dsi_write(dsi, DSI_PWR_UP, POWERUP);
481 static void dw_mipi_dsi_init_pll(struct dw_mipi_dsi *dsi)
484 * The maximum permitted escape clock is 20MHz and it is derived from
485 * lanebyteclk, which is running at "lane_mbps / 8". Thus we want:
487 * (lane_mbps >> 3) / esc_clk_division < 20
489 * (lane_mbps >> 3) / 20 > esc_clk_division
491 u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
493 dsi_write(dsi, DSI_PWR_UP, RESET);
496 * TODO dw drv improvements
497 * timeout clock division should be computed with the
498 * high speed transmission counter timeout and byte lane...
500 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
501 TX_ESC_CLK_DIVISION(esc_clk_division));
504 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
505 struct display_timing *timings)
507 struct mipi_dsi_device *device = dsi->device;
508 u32 val = 0, color = 0;
510 switch (device->format) {
511 case MIPI_DSI_FMT_RGB888:
512 color = DPI_COLOR_CODING_24BIT;
514 case MIPI_DSI_FMT_RGB666:
515 color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN;
517 case MIPI_DSI_FMT_RGB666_PACKED:
518 color = DPI_COLOR_CODING_18BIT_1;
520 case MIPI_DSI_FMT_RGB565:
521 color = DPI_COLOR_CODING_16BIT_1;
525 if (device->mode_flags & DISPLAY_FLAGS_VSYNC_HIGH)
526 val |= VSYNC_ACTIVE_LOW;
527 if (device->mode_flags & DISPLAY_FLAGS_HSYNC_HIGH)
528 val |= HSYNC_ACTIVE_LOW;
530 dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
531 dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
532 dsi_write(dsi, DSI_DPI_CFG_POL, val);
534 * TODO dw drv improvements
535 * largest packet sizes during hfp or during vsa/vpb/vfp
536 * should be computed according to byte lane, lane number and only
537 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
539 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
540 | INVACT_LPCMD_TIME(4));
543 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
545 dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
548 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
549 struct display_timing *timings)
552 * TODO dw drv improvements
553 * only burst mode is supported here. For non-burst video modes,
554 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
555 * DSI_VNPCR.NPSIZE... especially because this driver supports
556 * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
558 dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(timings->hactive.typ));
561 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
563 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
566 * TODO dw drv improvements
567 * compute high speed transmission counter timeout according
568 * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
570 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
572 * TODO dw drv improvements
573 * the Bus-Turn-Around Timeout Counter should be computed
574 * according to byte lane...
576 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
577 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
579 if (phy_ops->post_set_mode)
580 phy_ops->post_set_mode(dsi->device, 0);
583 /* Get lane byte clock cycles. */
584 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
585 struct display_timing *timings,
590 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
592 frac = lbcc % (timings->pixelclock.typ / 1000);
593 lbcc = lbcc / (timings->pixelclock.typ / 1000);
600 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
601 struct display_timing *timings)
603 u32 htotal, hsa, hbp, lbcc;
605 htotal = timings->hactive.typ + timings->hfront_porch.typ +
606 timings->hback_porch.typ + timings->hsync_len.typ;
608 hsa = timings->hback_porch.typ;
609 hbp = timings->hsync_len.typ;
612 * TODO dw drv improvements
613 * computations below may be improved...
615 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, htotal);
616 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
618 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, hsa);
619 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
621 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, hbp);
622 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
625 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
626 struct display_timing *timings)
628 u32 vactive, vsa, vfp, vbp;
630 vactive = timings->vactive.typ;
631 vsa = timings->vback_porch.typ;
632 vfp = timings->vfront_porch.typ;
633 vbp = timings->vsync_len.typ;
635 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
636 dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
637 dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
638 dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
641 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
646 * TODO dw drv improvements
647 * data & clock lane timers should be computed according to panel
648 * blankings and to the automatic clock lane control mode...
649 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
650 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
653 hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
655 if (hw_version >= HWVER_131) {
656 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(0x40) |
657 PHY_LP2HS_TIME_V131(0x40));
658 dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
660 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) |
661 PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
664 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
665 | PHY_CLKLP2HS_TIME(0x40));
668 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
670 struct mipi_dsi_device *device = dsi->device;
673 * TODO dw drv improvements
674 * stop wait time should be the maximum between host dsi
675 * and panel stop wait times
677 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
678 N_LANES(device->lanes));
681 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
683 /* Clear PHY state */
684 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
685 | PHY_RSTZ | PHY_SHUTDOWNZ);
686 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
687 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
688 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
691 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
696 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
697 PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
699 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
700 val & PHY_LOCK, PHY_STATUS_TIMEOUT_US);
702 dev_warn(dsi->dev, "failed to wait phy lock state\n");
704 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
705 val, val & PHY_STOP_STATE_CLK_LANE,
706 PHY_STATUS_TIMEOUT_US);
708 dev_warn(dsi->dev, "failed to wait phy clk lane stop state\n");
711 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
713 dsi_read(dsi, DSI_INT_ST0);
714 dsi_read(dsi, DSI_INT_ST1);
715 dsi_write(dsi, DSI_INT_MSK0, 0);
716 dsi_write(dsi, DSI_INT_MSK1, 0);
719 static void dw_mipi_dsi_bridge_set(struct dw_mipi_dsi *dsi,
720 struct display_timing *timings)
722 const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
723 struct mipi_dsi_device *device = dsi->device;
726 ret = phy_ops->get_lane_mbps(dsi->device, timings, device->lanes,
727 device->format, &dsi->lane_mbps);
729 dev_warn(dsi->dev, "Phy get_lane_mbps() failed\n");
731 dw_mipi_dsi_init_pll(dsi);
732 dw_mipi_dsi_dpi_config(dsi, timings);
733 dw_mipi_dsi_packet_handler_config(dsi);
734 dw_mipi_dsi_video_mode_config(dsi);
735 dw_mipi_dsi_video_packet_config(dsi, timings);
736 dw_mipi_dsi_command_mode_config(dsi);
737 dw_mipi_dsi_line_timer_config(dsi, timings);
738 dw_mipi_dsi_vertical_timing_config(dsi, timings);
740 dw_mipi_dsi_dphy_init(dsi);
741 dw_mipi_dsi_dphy_timing_config(dsi);
742 dw_mipi_dsi_dphy_interface_config(dsi);
744 dw_mipi_dsi_clear_err(dsi);
746 ret = phy_ops->init(dsi->device);
748 dev_warn(dsi->dev, "Phy init() failed\n");
750 dw_mipi_dsi_dphy_enable(dsi);
752 dw_mipi_dsi_wait_for_two_frames(timings);
754 /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
755 dw_mipi_dsi_set_mode(dsi, 0);
758 static int dw_mipi_dsi_init(struct udevice *dev,
759 struct mipi_dsi_device *device,
760 struct display_timing *timings,
761 unsigned int max_data_lanes,
762 const struct mipi_dsi_phy_ops *phy_ops)
764 struct dw_mipi_dsi *dsi = dev_get_priv(dev);
768 if (!phy_ops->init || !phy_ops->get_lane_mbps) {
769 dev_err(device->dev, "Phy not properly configured\n");
773 dsi->phy_ops = phy_ops;
774 dsi->max_data_lanes = max_data_lanes;
775 dsi->device = device;
776 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
777 device->host = &dsi->dsi_host;
779 dsi->base = (void *)dev_read_addr(device->dev);
780 if ((fdt_addr_t)dsi->base == FDT_ADDR_T_NONE) {
781 dev_err(device->dev, "dsi dt register address error\n");
785 ret = clk_get_by_name(device->dev, "px_clk", &clk);
787 dev_err(device->dev, "peripheral clock get error %d\n", ret);
791 /* get the pixel clock set by the clock framework */
792 timings->pixelclock.typ = clk_get_rate(&clk);
794 dw_mipi_dsi_bridge_set(dsi, timings);
799 static int dw_mipi_dsi_enable(struct udevice *dev)
801 struct dw_mipi_dsi *dsi = dev_get_priv(dev);
803 /* Switch to video mode for panel-bridge enable & panel enable */
804 dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
809 struct dsi_host_ops dw_mipi_dsi_ops = {
810 .init = dw_mipi_dsi_init,
811 .enable = dw_mipi_dsi_enable,
814 static int dw_mipi_dsi_probe(struct udevice *dev)
819 U_BOOT_DRIVER(dw_mipi_dsi) = {
820 .name = "dw_mipi_dsi",
821 .id = UCLASS_DSI_HOST,
822 .probe = dw_mipi_dsi_probe,
823 .ops = &dw_mipi_dsi_ops,
824 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi),
827 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
828 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
829 MODULE_AUTHOR("Yannick Fertré <yannick.fertre@st.com>");
830 MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
831 MODULE_LICENSE("GPL");
832 MODULE_ALIAS("platform:dw-mipi-dsi");