5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
7 * Copyright (C) 2008-2009 MontaVista Software Inc.
8 * Copyright (C) 2008-2009 Texas Instruments Inc
10 * Based on the LCD driver for TI Avalanche processors written by
11 * Ajay Singh and Shalom Hai.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option)any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 #include <linux/list.h>
34 #include <asm/errno.h>
36 #include <asm/arch/hardware.h>
38 #include "videomodes.h"
39 #include <asm/arch/da8xx-fb.h>
41 #define DRIVER_NAME "da8xx_lcdc"
43 /* LCD Status Register */
44 #define LCD_END_OF_FRAME1 (1 << 9)
45 #define LCD_END_OF_FRAME0 (1 << 8)
46 #define LCD_PL_LOAD_DONE (1 << 6)
47 #define LCD_FIFO_UNDERFLOW (1 << 5)
48 #define LCD_SYNC_LOST (1 << 2)
50 /* LCD DMA Control Register */
51 #define LCD_DMA_BURST_SIZE(x) ((x) << 4)
52 #define LCD_DMA_BURST_1 0x0
53 #define LCD_DMA_BURST_2 0x1
54 #define LCD_DMA_BURST_4 0x2
55 #define LCD_DMA_BURST_8 0x3
56 #define LCD_DMA_BURST_16 0x4
57 #define LCD_END_OF_FRAME_INT_ENA (1 << 2)
58 #define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0)
60 /* LCD Control Register */
61 #define LCD_CLK_DIVISOR(x) ((x) << 8)
62 #define LCD_RASTER_MODE 0x01
64 /* LCD Raster Control Register */
65 #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
66 #define PALETTE_AND_DATA 0x00
67 #define PALETTE_ONLY 0x01
68 #define DATA_ONLY 0x02
70 #define LCD_MONO_8BIT_MODE (1 << 9)
71 #define LCD_RASTER_ORDER (1 << 8)
72 #define LCD_TFT_MODE (1 << 7)
73 #define LCD_UNDERFLOW_INT_ENA (1 << 6)
74 #define LCD_PL_ENABLE (1 << 4)
75 #define LCD_MONOCHROME_MODE (1 << 1)
76 #define LCD_RASTER_ENABLE (1 << 0)
77 #define LCD_TFT_ALT_ENABLE (1 << 23)
78 #define LCD_STN_565_ENABLE (1 << 24)
80 /* LCD Raster Timing 2 Register */
81 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
82 #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
83 #define LCD_SYNC_CTRL (1 << 25)
84 #define LCD_SYNC_EDGE (1 << 24)
85 #define LCD_INVERT_PIXEL_CLOCK (1 << 22)
86 #define LCD_INVERT_LINE_CLOCK (1 << 21)
87 #define LCD_INVERT_FRAME_CLOCK (1 << 20)
90 struct da8xx_lcd_regs {
108 u32 dma_frm_buf_base_addr_0;
109 u32 dma_frm_buf_ceiling_addr_0;
110 u32 dma_frm_buf_base_addr_1;
111 u32 dma_frm_buf_ceiling_addr_1;
114 #define LCD_NUM_BUFFERS 1
116 #define WSI_TIMEOUT 50
117 #define PALETTE_SIZE 256
118 #define LEFT_MARGIN 64
119 #define RIGHT_MARGIN 64
120 #define UPPER_MARGIN 32
121 #define LOWER_MARGIN 32
123 #define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP)
124 #define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); })
126 static struct da8xx_lcd_regs *da8xx_fb_reg_base;
128 DECLARE_GLOBAL_DATA_PTR;
131 static GraphicDevice gpanel;
132 static const struct da8xx_panel *lcd_panel;
133 static struct fb_info *da8xx_fb_info;
134 static int bits_x_pixel;
136 static inline unsigned int lcdc_read(u32 *addr)
138 return (unsigned int)readl(addr);
141 static inline void lcdc_write(unsigned int val, u32 *addr)
146 struct da8xx_fb_par {
148 unsigned char *v_palette_base;
149 dma_addr_t vram_phys;
150 unsigned long vram_size;
152 unsigned int dma_start;
153 unsigned int dma_end;
154 struct clk *lcdc_clk;
156 unsigned short pseudo_palette[16];
157 unsigned int palette_sz;
158 unsigned int pxl_clk;
165 /* Variable Screen Information */
166 static struct fb_var_screeninfo da8xx_fb_var = {
174 .pixclock = 46666, /* 46us - AUO display */
176 .left_margin = LEFT_MARGIN,
177 .right_margin = RIGHT_MARGIN,
178 .upper_margin = UPPER_MARGIN,
179 .lower_margin = LOWER_MARGIN,
181 .vmode = FB_VMODE_NONINTERLACED
184 static struct fb_fix_screeninfo da8xx_fb_fix = {
185 .id = "DA8xx FB Drv",
186 .type = FB_TYPE_PACKED_PIXELS,
188 .visual = FB_VISUAL_PSEUDOCOLOR,
192 .accel = FB_ACCEL_NONE
195 static const struct display_panel disp_panel = {
202 static const struct lcd_ctrl_config lcd_cfg = {
212 .invert_line_clock = 1,
213 .invert_frm_clock = 1,
219 /* Enable the Raster Engine of the LCD Controller */
220 static inline void lcd_enable_raster(void)
224 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
225 if (!(reg & LCD_RASTER_ENABLE))
226 lcdc_write(reg | LCD_RASTER_ENABLE,
227 &da8xx_fb_reg_base->raster_ctrl);
230 /* Disable the Raster Engine of the LCD Controller */
231 static inline void lcd_disable_raster(void)
235 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
236 if (reg & LCD_RASTER_ENABLE)
237 lcdc_write(reg & ~LCD_RASTER_ENABLE,
238 &da8xx_fb_reg_base->raster_ctrl);
241 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
248 /* init reg to clear PLM (loading mode) fields */
249 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
250 reg_ras &= ~(3 << 20);
252 reg_dma = lcdc_read(&da8xx_fb_reg_base->dma_ctrl);
254 if (load_mode == LOAD_DATA) {
255 start = par->dma_start;
258 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
259 reg_dma |= LCD_END_OF_FRAME_INT_ENA;
261 #if (LCD_NUM_BUFFERS == 2)
262 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
263 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
264 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
265 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
266 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
268 reg_dma &= ~LCD_DUAL_FRAME_BUFFER_ENABLE;
269 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
270 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
271 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
272 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
275 } else if (load_mode == LOAD_PALETTE) {
276 start = par->p_palette_base;
277 end = start + par->palette_sz - 1;
279 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
280 reg_ras |= LCD_PL_ENABLE;
282 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
283 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
286 lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl);
287 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
290 * The Raster enable bit must be set after all other control fields are
296 /* Configure the Burst Size of DMA */
297 static int lcd_cfg_dma(int burst_size)
301 reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001;
302 switch (burst_size) {
304 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
307 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
310 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
313 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
316 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
321 lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl);
326 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
330 /* Set the AC Bias Period and Number of Transisitons per Interrupt */
331 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000;
332 reg |= LCD_AC_BIAS_FREQUENCY(period) |
333 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
334 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
337 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
342 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf;
343 reg |= ((back_porch & 0xff) << 24)
344 | ((front_porch & 0xff) << 16)
345 | ((pulse_width & 0x3f) << 10);
346 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
349 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
354 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff;
355 reg |= ((back_porch & 0xff) << 24)
356 | ((front_porch & 0xff) << 16)
357 | ((pulse_width & 0x3f) << 10);
358 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
361 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
365 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
367 LCD_MONOCHROME_MODE);
369 switch (cfg->p_disp_panel->panel_shade) {
371 reg |= LCD_MONOCHROME_MODE;
372 if (cfg->mono_8bit_mode)
373 reg |= LCD_MONO_8BIT_MODE;
377 if (cfg->tft_alt_mode)
378 reg |= LCD_TFT_ALT_ENABLE;
382 if (cfg->stn_565_mode)
383 reg |= LCD_STN_565_ENABLE;
390 /* enable additional interrupts here */
391 reg |= LCD_UNDERFLOW_INT_ENA;
393 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
395 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
398 reg |= LCD_SYNC_CTRL;
400 reg &= ~LCD_SYNC_CTRL;
403 reg |= LCD_SYNC_EDGE;
405 reg &= ~LCD_SYNC_EDGE;
407 if (cfg->invert_line_clock)
408 reg |= LCD_INVERT_LINE_CLOCK;
410 reg &= ~LCD_INVERT_LINE_CLOCK;
412 if (cfg->invert_frm_clock)
413 reg |= LCD_INVERT_FRAME_CLOCK;
415 reg &= ~LCD_INVERT_FRAME_CLOCK;
417 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
422 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
423 u32 bpp, u32 raster_order)
427 /* Set the Panel Width */
428 /* Pixels per line = (PPL + 1)*16 */
429 /*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/
431 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
433 reg |= ((width >> 4) - 1) << 4;
434 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
436 /* Set the Panel Height */
437 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1);
438 reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
439 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
441 /* Set the Raster Order of the Frame Buffer */
442 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8);
444 reg |= LCD_RASTER_ORDER;
445 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
452 par->palette_sz = 16 * 2;
456 par->palette_sz = 256 * 2;
466 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
467 unsigned blue, unsigned transp,
468 struct fb_info *info)
470 struct da8xx_fb_par *par = info->par;
471 unsigned short *palette = (unsigned short *) par->v_palette_base;
478 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
481 if (info->var.bits_per_pixel == 8) {
486 pal = (red & 0x0f00);
487 pal |= (green & 0x00f0);
488 pal |= (blue & 0x000f);
490 if (palette[regno] != pal) {
492 palette[regno] = pal;
494 } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
495 red >>= (16 - info->var.red.length);
496 red <<= info->var.red.offset;
498 green >>= (16 - info->var.green.length);
499 green <<= info->var.green.offset;
501 blue >>= (16 - info->var.blue.length);
502 blue <<= info->var.blue.offset;
504 par->pseudo_palette[regno] = red | green | blue;
506 if (palette[0] != 0x4000) {
512 /* Update the palette in the h/w as needed. */
514 lcd_blit(LOAD_PALETTE, par);
519 static void lcd_reset(struct da8xx_fb_par *par)
521 /* Disable the Raster if previously Enabled */
522 lcd_disable_raster();
524 /* DMA has to be disabled */
525 lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);
526 lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
529 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
531 unsigned int lcd_clk, div;
533 /* Get clock from sysclk2 */
534 lcd_clk = clk_get(2);
536 div = lcd_clk / par->pxl_clk;
537 debug("LCD Clock: 0x%x Divider: 0x%x PixClk: 0x%x\n",
538 lcd_clk, div, par->pxl_clk);
540 /* Configure the LCD clock divisor. */
541 lcdc_write(LCD_CLK_DIVISOR(div) |
542 (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl);
545 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
546 const struct da8xx_panel *panel)
553 /* Calculate the divider */
554 lcd_calc_clk_divider(par);
556 if (panel->invert_pxl_clk)
557 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) |
558 LCD_INVERT_PIXEL_CLOCK),
559 &da8xx_fb_reg_base->raster_timing_2);
561 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) &
562 ~LCD_INVERT_PIXEL_CLOCK),
563 &da8xx_fb_reg_base->raster_timing_2);
565 /* Configure the DMA burst size. */
566 ret = lcd_cfg_dma(cfg->dma_burst_sz);
570 /* Configure the AC bias properties. */
571 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
573 /* Configure the vertical and horizontal sync properties. */
574 lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
575 lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
577 /* Configure for disply */
578 ret = lcd_cfg_display(cfg);
582 if (QVGA != cfg->p_disp_panel->panel_type)
585 if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
586 cfg->bpp >= cfg->p_disp_panel->min_bpp)
589 bpp = cfg->p_disp_panel->max_bpp;
592 ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
593 (unsigned int)panel->height, bpp,
599 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) |
600 (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl);
605 static void lcdc_dma_start(void)
607 struct da8xx_fb_par *par = da8xx_fb_info->par;
608 lcdc_write(par->dma_start,
609 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
610 lcdc_write(par->dma_end,
611 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
613 &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
615 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
618 static u32 lcdc_irq_handler(void)
620 struct da8xx_fb_par *par = da8xx_fb_info->par;
621 u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
624 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
625 debug("LCD_SYNC_LOST\n");
626 lcd_disable_raster();
627 lcdc_write(stat, &da8xx_fb_reg_base->stat);
629 return LCD_SYNC_LOST;
630 } else if (stat & LCD_PL_LOAD_DONE) {
631 debug("LCD_PL_LOAD_DONE\n");
633 * Must disable raster before changing state of any control bit.
634 * And also must be disabled before clearing the PL loading
635 * interrupt via the following write to the status register. If
636 * this is done after then one gets multiple PL done interrupts.
638 lcd_disable_raster();
640 lcdc_write(stat, &da8xx_fb_reg_base->stat);
642 /* Disable PL completion inerrupt */
643 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
644 reg_ras &= ~LCD_PL_ENABLE;
645 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
647 /* Setup and start data loading mode */
648 lcd_blit(LOAD_DATA, par);
649 return LCD_PL_LOAD_DONE;
651 lcdc_write(stat, &da8xx_fb_reg_base->stat);
653 if (stat & LCD_END_OF_FRAME0)
654 debug("LCD_END_OF_FRAME0\n");
656 lcdc_write(par->dma_start,
657 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
658 lcdc_write(par->dma_end,
659 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
661 return LCD_END_OF_FRAME0;
666 static u32 wait_for_event(u32 event)
672 ret = lcdc_irq_handler();
674 } while (!(ret & event));
677 printf("%s: event %d not hit\n", __func__, event);
685 void *video_hw_init(void)
687 struct da8xx_fb_par *par;
693 printf("Display not initialized\n");
696 gpanel.winSizeX = lcd_panel->width;
697 gpanel.winSizeY = lcd_panel->height;
698 gpanel.plnSizeX = lcd_panel->width;
699 gpanel.plnSizeY = lcd_panel->height;
701 switch (bits_x_pixel) {
703 gpanel.gdfBytesPP = 4;
704 gpanel.gdfIndex = GDF_32BIT_X888RGB;
707 gpanel.gdfBytesPP = 2;
708 gpanel.gdfIndex = GDF_16BIT_565RGB;
711 gpanel.gdfBytesPP = 1;
712 gpanel.gdfIndex = GDF__8BIT_INDEX;
716 da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DAVINCI_LCD_CNTL_BASE;
718 debug("Resolution: %dx%d %x\n",
723 size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
724 da8xx_fb_info = malloc(size);
725 debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info);
727 if (!da8xx_fb_info) {
728 printf("Memory allocation failed for fb_info\n");
731 memset(da8xx_fb_info, 0, size);
732 p = (char *)da8xx_fb_info;
733 da8xx_fb_info->par = p + sizeof(struct fb_info);
734 debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par);
736 par = da8xx_fb_info->par;
737 par->pxl_clk = lcd_panel->pxl_clk;
739 if (lcd_init(par, &lcd_cfg, lcd_panel) < 0) {
740 printf("lcd_init failed\n");
745 /* allocate frame buffer */
746 par->vram_size = lcd_panel->width * lcd_panel->height * lcd_cfg.bpp;
747 par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
749 par->vram_virt = malloc(par->vram_size);
751 par->vram_phys = (dma_addr_t) par->vram_virt;
752 debug("Requesting 0x%x bytes for framebuffer at 0x%x\n",
753 (unsigned int)par->vram_size,
754 (unsigned int)par->vram_virt);
755 if (!par->vram_virt) {
756 printf("GLCD: malloc for frame buffer failed\n");
761 gpanel.frameAdrs = (unsigned int)par->vram_virt;
762 da8xx_fb_info->screen_base = (char *) par->vram_virt;
763 da8xx_fb_fix.smem_start = gpanel.frameAdrs;
764 da8xx_fb_fix.smem_len = par->vram_size;
765 da8xx_fb_fix.line_length = (lcd_panel->width * lcd_cfg.bpp) / 8;
767 par->dma_start = par->vram_phys;
768 par->dma_end = par->dma_start + lcd_panel->height *
769 da8xx_fb_fix.line_length - 1;
771 /* allocate palette buffer */
772 par->v_palette_base = malloc(PALETTE_SIZE);
773 if (!par->v_palette_base) {
774 printf("GLCD: malloc for palette buffer failed\n");
775 goto err_release_fb_mem;
777 memset(par->v_palette_base, 0, PALETTE_SIZE);
778 par->p_palette_base = (unsigned int)par->v_palette_base;
781 da8xx_fb_info->var.bits_per_pixel = lcd_cfg.bpp;
783 da8xx_fb_var.xres = lcd_panel->width;
784 da8xx_fb_var.xres_virtual = lcd_panel->width;
786 da8xx_fb_var.yres = lcd_panel->height;
787 da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS;
789 da8xx_fb_var.grayscale =
790 lcd_cfg.p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
791 da8xx_fb_var.bits_per_pixel = lcd_cfg.bpp;
793 da8xx_fb_var.hsync_len = lcd_panel->hsw;
794 da8xx_fb_var.vsync_len = lcd_panel->vsw;
796 /* Initialize fbinfo */
797 da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
798 da8xx_fb_info->fix = da8xx_fb_fix;
799 da8xx_fb_info->var = da8xx_fb_var;
800 da8xx_fb_info->pseudo_palette = par->pseudo_palette;
801 da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
802 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
804 /* Clear interrupt */
805 memset((void *)par->vram_virt, 0, par->vram_size);
806 lcd_disable_raster();
807 lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
808 debug("Palette at 0x%x size %d\n", par->p_palette_base,
812 /* Load a default palette */
813 fb_setcolreg(0, 0, 0, 0, 0xffff, da8xx_fb_info);
815 /* Check that the palette is loaded */
816 wait_for_event(LCD_PL_LOAD_DONE);
818 /* Wait until DMA is working */
819 wait_for_event(LCD_END_OF_FRAME0);
821 return (void *)&gpanel;
824 free(par->vram_virt);
832 void video_set_lut(unsigned int index, /* color number */
833 unsigned char r, /* red */
834 unsigned char g, /* green */
835 unsigned char b /* blue */
842 void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel)
845 bits_x_pixel = bits_pixel;