1 // SPDX-License-Identifier: GPL-2.0
3 * From coreboot src/soc/intel/broadwell/igd.c
5 * Copyright (C) 2016 Google, Inc
10 #include <bootstage.h>
17 #include <asm/intel_regs.h>
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/iomap.h>
22 #include <asm/arch/pch.h>
23 #include <linux/delay.h>
26 struct broadwell_igd_priv {
30 struct broadwell_igd_plat {
35 int power_backlight_on_delay;
37 int power_backlight_off_delay;
38 int power_cycle_delay;
42 int pre_graphics_delay;
46 #define GT_CDCLK_337 0
47 #define GT_CDCLK_450 1
48 #define GT_CDCLK_540 2
49 #define GT_CDCLK_675 3
51 u32 board_map_oprom_vendev(u32 vendev)
53 return SA_IGD_OPROM_VENDEV;
56 static int poll32(u8 *addr, uint mask, uint value)
61 debug("%s: addr %p = %x\n", __func__, addr, readl(addr));
62 while ((readl(addr) & mask) != value) {
63 if (get_timer(start) > GT_RETRY) {
64 debug("poll32: timeout: %x\n", readl(addr));
72 static int haswell_early_init(struct udevice *dev)
74 struct broadwell_igd_priv *priv = dev_get_priv(dev);
75 u8 *regs = priv->regs;
78 /* Enable Force Wake */
79 writel(0x00000020, regs + 0xa180);
80 writel(0x00010001, regs + 0xa188);
81 ret = poll32(regs + 0x130044, 1, 1);
86 setbits_le32(regs + 0xa248, 0x00000016);
88 /* GFXPAUSE settings */
89 writel(0x00070020, regs + 0xa000);
92 clrsetbits_le32(regs + 0xa180, ~0xff3fffff, 0x15000000);
94 /* Enable DOP Clock Gating */
95 writel(0x000003fd, regs + 0x9424);
97 /* Enable Unit Level Clock Gating */
98 writel(0x00000080, regs + 0x9400);
99 writel(0x40401000, regs + 0x9404);
100 writel(0x00000000, regs + 0x9408);
101 writel(0x02000001, regs + 0x940c);
107 /* Wake Rate Limits */
108 setbits_le32(regs + 0xa090, 0x00000000);
109 setbits_le32(regs + 0xa098, 0x03e80000);
110 setbits_le32(regs + 0xa09c, 0x00280000);
111 setbits_le32(regs + 0xa0a8, 0x0001e848);
112 setbits_le32(regs + 0xa0ac, 0x00000019);
114 /* Render/Video/Blitter Idle Max Count */
115 writel(0x0000000a, regs + 0x02054);
116 writel(0x0000000a, regs + 0x12054);
117 writel(0x0000000a, regs + 0x22054);
118 writel(0x0000000a, regs + 0x1a054);
120 /* RC Sleep / RCx Thresholds */
121 setbits_le32(regs + 0xa0b0, 0x00000000);
122 setbits_le32(regs + 0xa0b4, 0x000003e8);
123 setbits_le32(regs + 0xa0b8, 0x0000c350);
126 setbits_le32(regs + 0xa010, 0x000f4240);
127 setbits_le32(regs + 0xa014, 0x12060000);
128 setbits_le32(regs + 0xa02c, 0x0000e808);
129 setbits_le32(regs + 0xa030, 0x0003bd08);
130 setbits_le32(regs + 0xa068, 0x000101d0);
131 setbits_le32(regs + 0xa06c, 0x00055730);
132 setbits_le32(regs + 0xa070, 0x0000000a);
135 writel(0x00000b92, regs + 0xa024);
138 writel(0x88040000, regs + 0xa090);
140 /* Video Frequency Request */
141 writel(0x08000000, regs + 0xa00c);
144 ret = poll32(regs + 0x138124, (1 << 31), 0);
147 writel(0, regs + 0x138128);
148 writel(0x80000004, regs + 0x138124);
149 ret = poll32(regs + 0x138124, (1 << 31), 0);
153 /* Enable PM Interrupts */
154 writel(0x03000076, regs + 0x4402c);
156 /* Enable RC6 in idle */
157 writel(0x00040000, regs + 0xa094);
161 debug("%s: ret=%d\n", __func__, ret);
165 static int haswell_late_init(struct udevice *dev)
167 struct broadwell_igd_priv *priv = dev_get_priv(dev);
168 u8 *regs = priv->regs;
172 setbits_le32(regs + 0x0a248, (1 << 31));
173 setbits_le32(regs + 0x0a004, (1 << 4));
174 setbits_le32(regs + 0x0a080, (1 << 2));
175 setbits_le32(regs + 0x0a180, (1 << 31));
177 /* Disable Force Wake */
178 writel(0x00010000, regs + 0xa188);
179 ret = poll32(regs + 0x130044, 1, 0);
182 writel(0x00000001, regs + 0xa188);
184 /* Enable power well for DP and Audio */
185 setbits_le32(regs + 0x45400, (1 << 31));
186 ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);
192 debug("%s: ret=%d\n", __func__, ret);
196 static int broadwell_early_init(struct udevice *dev)
198 struct broadwell_igd_priv *priv = dev_get_priv(dev);
199 u8 *regs = priv->regs;
202 /* Enable Force Wake */
203 writel(0x00010001, regs + 0xa188);
204 ret = poll32(regs + 0x130044, 1, 1);
208 /* Enable push bus metric control and shift */
209 writel(0x00000004, regs + 0xa248);
210 writel(0x000000ff, regs + 0xa250);
211 writel(0x00000010, regs + 0xa25c);
213 /* GFXPAUSE settings (set based on stepping) */
216 writel(0x45200000, regs + 0xa180);
218 /* Enable DOP Clock Gating */
219 writel(0x000000fd, regs + 0x9424);
221 /* Enable Unit Level Clock Gating */
222 writel(0x00000000, regs + 0x9400);
223 writel(0x40401000, regs + 0x9404);
224 writel(0x00000000, regs + 0x9408);
225 writel(0x02000001, regs + 0x940c);
226 writel(0x0000000a, regs + 0x1a054);
228 /* Video Frequency Request */
229 writel(0x08000000, regs + 0xa00c);
231 writel(0x00000009, regs + 0x138158);
232 writel(0x0000000d, regs + 0x13815c);
238 /* Wake Rate Limits */
239 clrsetbits_le32(regs + 0x0a090, ~0, 0);
240 setbits_le32(regs + 0x0a098, 0x03e80000);
241 setbits_le32(regs + 0x0a09c, 0x00280000);
242 setbits_le32(regs + 0x0a0a8, 0x0001e848);
243 setbits_le32(regs + 0x0a0ac, 0x00000019);
245 /* Render/Video/Blitter Idle Max Count */
246 writel(0x0000000a, regs + 0x02054);
247 writel(0x0000000a, regs + 0x12054);
248 writel(0x0000000a, regs + 0x22054);
250 /* RC Sleep / RCx Thresholds */
251 setbits_le32(regs + 0x0a0b0, 0x00000000);
252 setbits_le32(regs + 0x0a0b8, 0x00000271);
255 setbits_le32(regs + 0x0a010, 0x000f4240);
256 setbits_le32(regs + 0x0a014, 0x12060000);
257 setbits_le32(regs + 0x0a02c, 0x0000e808);
258 setbits_le32(regs + 0x0a030, 0x0003bd08);
259 setbits_le32(regs + 0x0a068, 0x000101d0);
260 setbits_le32(regs + 0x0a06c, 0x00055730);
261 setbits_le32(regs + 0x0a070, 0x0000000a);
262 setbits_le32(regs + 0x0a168, 0x00000006);
265 writel(0x00000b92, regs + 0xa024);
268 writel(0x90040000, regs + 0xa090);
271 ret = poll32(regs + 0x138124, (1 << 31), 0);
274 writel(0, regs + 0x138128);
275 writel(0x80000004, regs + 0x138124);
276 ret = poll32(regs + 0x138124, (1 << 31), 0);
280 /* Enable PM Interrupts */
281 writel(0x03000076, regs + 0x4402c);
283 /* Enable RC6 in idle */
284 writel(0x00040000, regs + 0xa094);
288 debug("%s: ret=%d\n", __func__, ret);
292 static int broadwell_late_init(struct udevice *dev)
294 struct broadwell_igd_priv *priv = dev_get_priv(dev);
295 u8 *regs = priv->regs;
299 setbits_le32(regs + 0x0a248, 1 << 31);
300 setbits_le32(regs + 0x0a000, 1 << 18);
301 setbits_le32(regs + 0x0a180, 1 << 31);
303 /* Disable Force Wake */
304 writel(0x00010000, regs + 0xa188);
305 ret = poll32(regs + 0x130044, 1, 0);
309 /* Enable power well for DP and Audio */
310 setbits_le32(regs + 0x45400, 1 << 31);
311 ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);
317 debug("%s: ret=%d\n", __func__, ret);
322 static unsigned long gtt_read(struct broadwell_igd_priv *priv,
325 return readl(priv->regs + reg);
328 static void gtt_write(struct broadwell_igd_priv *priv, unsigned long reg,
331 writel(data, priv->regs + reg);
334 static inline void gtt_clrsetbits(struct broadwell_igd_priv *priv, u32 reg,
337 clrsetbits_le32(priv->regs + reg, bic, or);
340 static int gtt_poll(struct broadwell_igd_priv *priv, u32 reg, u32 mask,
343 unsigned try = GT_RETRY;
347 data = gtt_read(priv, reg);
348 if ((data & mask) == value)
353 debug("GT init timeout\n");
357 static void igd_setup_panel(struct udevice *dev)
359 struct broadwell_igd_plat *plat = dev_get_platdata(dev);
360 struct broadwell_igd_priv *priv = dev_get_priv(dev);
363 /* Setup Digital Port Hotplug */
364 reg32 = (plat->dp_hotplug[0] & 0x7) << 2;
365 reg32 |= (plat->dp_hotplug[1] & 0x7) << 10;
366 reg32 |= (plat->dp_hotplug[2] & 0x7) << 18;
367 gtt_write(priv, PCH_PORT_HOTPLUG, reg32);
369 /* Setup Panel Power On Delays */
370 reg32 = (plat->port_select & 0x3) << 30;
371 reg32 |= (plat->power_up_delay & 0x1fff) << 16;
372 reg32 |= (plat->power_backlight_on_delay & 0x1fff);
373 gtt_write(priv, PCH_PP_ON_DELAYS, reg32);
375 /* Setup Panel Power Off Delays */
376 reg32 = (plat->power_down_delay & 0x1fff) << 16;
377 reg32 |= (plat->power_backlight_off_delay & 0x1fff);
378 gtt_write(priv, PCH_PP_OFF_DELAYS, reg32);
380 /* Setup Panel Power Cycle Delay */
381 if (plat->power_cycle_delay) {
382 reg32 = gtt_read(priv, PCH_PP_DIVISOR);
384 reg32 |= plat->power_cycle_delay & 0xff;
385 gtt_write(priv, PCH_PP_DIVISOR, reg32);
388 /* Enable Backlight if needed */
389 if (plat->cpu_backlight) {
390 gtt_write(priv, BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE);
391 gtt_write(priv, BLC_PWM_CPU_CTL, plat->cpu_backlight);
393 if (plat->pch_backlight) {
394 gtt_write(priv, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE);
395 gtt_write(priv, BLC_PWM_PCH_CTL2, plat->pch_backlight);
399 static int igd_cdclk_init_haswell(struct udevice *dev)
401 struct broadwell_igd_plat *plat = dev_get_platdata(dev);
402 struct broadwell_igd_priv *priv = dev_get_priv(dev);
403 int cdclk = plat->cdclk;
409 dm_pci_read_config16(dev, PCI_DEVICE_ID, &devid);
411 /* Check for ULX GT1 or GT2 */
412 if (devid == 0x0a0e || devid == 0x0a1e)
415 /* 675MHz is not supported on haswell */
416 if (cdclk == GT_CDCLK_675)
417 cdclk = GT_CDCLK_337;
419 /* If CD clock is fixed or ULT then set to 450MHz */
420 if ((gtt_read(priv, 0x42014) & 0x1000000) || cpu_is_ult())
421 cdclk = GT_CDCLK_450;
423 /* 540MHz is not supported on ULX */
424 if (gpu_is_ulx && cdclk == GT_CDCLK_540)
425 cdclk = GT_CDCLK_337;
427 /* 337.5MHz is not supported on non-ULT/ULX */
428 if (!gpu_is_ulx && !cpu_is_ult() && cdclk == GT_CDCLK_337)
429 cdclk = GT_CDCLK_450;
431 /* Set variables based on CD Clock setting */
450 /* Set LPCLL_CTL CD Clock Frequency Select */
451 gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);
453 /* ULX: Inform power controller of selected frequency */
455 if (cdclk == GT_CDCLK_450)
456 gtt_write(priv, 0x138128, 0x00000000); /* 450MHz */
458 gtt_write(priv, 0x138128, 0x00000001); /* 337.5MHz */
459 gtt_write(priv, 0x13812c, 0x00000000);
460 gtt_write(priv, 0x138124, 0x80000017);
463 /* Set CPU DP AUX 2X bit clock dividers */
464 gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);
465 gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);
469 debug("%s: ret=%d\n", __func__, ret);
473 static int igd_cdclk_init_broadwell(struct udevice *dev)
475 struct broadwell_igd_plat *plat = dev_get_platdata(dev);
476 struct broadwell_igd_priv *priv = dev_get_priv(dev);
477 int cdclk = plat->cdclk;
478 u32 dpdiv, lpcll, pwctl, cdset;
481 /* Inform power controller of upcoming frequency change */
482 gtt_write(priv, 0x138128, 0);
483 gtt_write(priv, 0x13812c, 0);
484 gtt_write(priv, 0x138124, 0x80000018);
486 /* Poll GT driver mailbox for run/busy clear */
487 if (gtt_poll(priv, 0x138124, 1 << 31, 0 << 31))
488 cdclk = GT_CDCLK_450;
490 if (gtt_read(priv, 0x42014) & 0x1000000) {
491 /* If CD clock is fixed then set to 450MHz */
492 cdclk = GT_CDCLK_450;
494 /* Program CD clock to highest supported freq */
496 cdclk = GT_CDCLK_540;
498 cdclk = GT_CDCLK_675;
501 /* CD clock frequency 675MHz not supported on ULT */
502 if (cpu_is_ult() && cdclk == GT_CDCLK_675)
503 cdclk = GT_CDCLK_540;
505 /* Set variables based on CD Clock setting */
527 lpcll = (1 << 26) | (1 << 27);
535 debug("%s: frequency = %d\n", __func__, cdclk);
537 /* Set LPCLL_CTL CD Clock Frequency Select */
538 gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);
540 /* Inform power controller of selected frequency */
541 gtt_write(priv, 0x138128, pwctl);
542 gtt_write(priv, 0x13812c, 0);
543 gtt_write(priv, 0x138124, 0x80000017);
545 /* Program CD Clock Frequency */
546 gtt_clrsetbits(priv, 0x46200, ~0xfffffc00, cdset);
548 /* Set CPU DP AUX 2X bit clock dividers */
549 gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);
550 gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);
554 debug("%s: ret=%d\n", __func__, ret);
558 u8 systemagent_revision(struct udevice *bus)
562 pci_bus_read_config(bus, PCI_BDF(0, 0, 0), PCI_REVISION_ID, &val,
568 static int igd_pre_init(struct udevice *dev, bool is_broadwell)
570 struct broadwell_igd_plat *plat = dev_get_platdata(dev);
571 struct broadwell_igd_priv *priv = dev_get_priv(dev);
575 mdelay(plat->pre_graphics_delay);
577 /* Early init steps */
579 ret = broadwell_early_init(dev);
583 /* Set GFXPAUSE based on stepping */
584 if (cpu_get_stepping() <= (CPUID_BROADWELL_E0 & 0xf) &&
585 systemagent_revision(pci_get_controller(dev)) <= 9) {
586 gtt_write(priv, 0xa000, 0x300ff);
588 gtt_write(priv, 0xa000, 0x30020);
591 ret = haswell_early_init(dev);
596 /* Set RP1 graphics frequency */
597 rp1_gfx_freq = (readl(MCHBAR_REG(0x5998)) >> 8) & 0xff;
598 gtt_write(priv, 0xa008, rp1_gfx_freq << 24);
600 /* Post VBIOS panel setup */
601 igd_setup_panel(dev);
605 debug("%s: ret=%d\n", __func__, ret);
609 static int igd_post_init(struct udevice *dev, bool is_broadwell)
613 /* Late init steps */
615 ret = igd_cdclk_init_broadwell(dev);
618 ret = broadwell_late_init(dev);
622 igd_cdclk_init_haswell(dev);
623 ret = haswell_late_init(dev);
631 static int broadwell_igd_int15_handler(void)
635 debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
637 switch (M.x86.R_AX) {
640 * Boot Display Device Hook:
651 M.x86.R_CX = 0x0000; /* Use video bios default */
655 debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
662 static int broadwell_igd_probe(struct udevice *dev)
664 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
665 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
669 if (!ll_boot_init()) {
671 * If we are running from EFI or coreboot, this driver can't
674 printf("Not available (previous bootloader prevents it)\n");
677 is_broadwell = cpu_get_family_model() == BROADWELL_FAMILY_ULT;
678 bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
679 debug("%s: is_broadwell=%d\n", __func__, is_broadwell);
680 ret = igd_pre_init(dev, is_broadwell);
682 ret = vbe_setup_video(dev, broadwell_igd_int15_handler);
684 debug("failed to run video BIOS: %d\n", ret);
687 ret = igd_post_init(dev, is_broadwell);
688 bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
692 /* Use write-combining for the graphics memory, 256MB */
693 ret = mtrr_add_request(MTRR_TYPE_WRCOMB, plat->base, 256 << 20);
695 ret = mtrr_commit(true);
696 if (ret && ret != -ENOSYS) {
697 printf("Failed to add MTRR: Display will be slow (err %d)\n",
701 debug("fb=%lx, size %x, display size=%d %d %d\n", plat->base,
702 plat->size, uc_priv->xsize, uc_priv->ysize, uc_priv->bpix);
707 static int broadwell_igd_ofdata_to_platdata(struct udevice *dev)
709 struct broadwell_igd_plat *plat = dev_get_platdata(dev);
710 struct broadwell_igd_priv *priv = dev_get_priv(dev);
711 int node = dev_of_offset(dev);
712 const void *blob = gd->fdt_blob;
714 if (fdtdec_get_int_array(blob, node, "intel,dp-hotplug",
716 ARRAY_SIZE(plat->dp_hotplug)))
718 plat->port_select = fdtdec_get_int(blob, node, "intel,port-select", 0);
719 plat->power_cycle_delay = fdtdec_get_int(blob, node,
720 "intel,power-cycle-delay", 0);
721 plat->power_up_delay = fdtdec_get_int(blob, node,
722 "intel,power-up-delay", 0);
723 plat->power_down_delay = fdtdec_get_int(blob, node,
724 "intel,power-down-delay", 0);
725 plat->power_backlight_on_delay = fdtdec_get_int(blob, node,
726 "intel,power-backlight-on-delay", 0);
727 plat->power_backlight_off_delay = fdtdec_get_int(blob, node,
728 "intel,power-backlight-off-delay", 0);
729 plat->cpu_backlight = fdtdec_get_int(blob, node,
730 "intel,cpu-backlight", 0);
731 plat->pch_backlight = fdtdec_get_int(blob, node,
732 "intel,pch-backlight", 0);
733 plat->pre_graphics_delay = fdtdec_get_int(blob, node,
734 "intel,pre-graphics-delay", 0);
735 priv->regs = (u8 *)dm_pci_read_bar32(dev, 0);
736 debug("%s: regs at %p\n", __func__, priv->regs);
737 debug("dp_hotplug %d %d %d\n", plat->dp_hotplug[0], plat->dp_hotplug[1],
738 plat->dp_hotplug[2]);
739 debug("port_select = %d\n", plat->port_select);
740 debug("power_up_delay = %d\n", plat->power_up_delay);
741 debug("power_backlight_on_delay = %d\n",
742 plat->power_backlight_on_delay);
743 debug("power_down_delay = %d\n", plat->power_down_delay);
744 debug("power_backlight_off_delay = %d\n",
745 plat->power_backlight_off_delay);
746 debug("power_cycle_delay = %d\n", plat->power_cycle_delay);
747 debug("cpu_backlight = %x\n", plat->cpu_backlight);
748 debug("pch_backlight = %x\n", plat->pch_backlight);
749 debug("cdclk = %d\n", plat->cdclk);
750 debug("pre_graphics_delay = %d\n", plat->pre_graphics_delay);
755 static const struct video_ops broadwell_igd_ops = {
758 static const struct udevice_id broadwell_igd_ids[] = {
759 { .compatible = "intel,broadwell-igd" },
763 U_BOOT_DRIVER(broadwell_igd) = {
764 .name = "broadwell_igd",
766 .of_match = broadwell_igd_ids,
767 .ops = &broadwell_igd_ops,
768 .ofdata_to_platdata = broadwell_igd_ofdata_to_platdata,
769 .probe = broadwell_igd_probe,
770 .priv_auto_alloc_size = sizeof(struct broadwell_igd_priv),
771 .platdata_auto_alloc_size = sizeof(struct broadwell_igd_plat),