1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Vasily Khoruzhick <anarsoul@gmail.com>
12 #include <video_bridge.h>
13 #include <linux/delay.h>
14 #include "../anx98xx-edp.h"
16 #define DP_MAX_LINK_RATE 0x001
17 #define DP_MAX_LANE_COUNT 0x002
18 #define DP_MAX_LANE_COUNT_MASK 0x1f
24 static int anx6345_write(struct udevice *dev, unsigned int addr_off,
25 unsigned char reg_addr, unsigned char value)
37 ret = dm_i2c_xfer(dev, &msg, 1);
39 debug("%s: write failed, reg=%#x, value=%#x, ret=%d\n",
40 __func__, reg_addr, value, ret);
47 static int anx6345_read(struct udevice *dev, unsigned int addr_off,
48 unsigned char reg_addr, unsigned char *value)
51 struct i2c_msg msg[2];
54 msg[0].addr = addr_off;
59 msg[1].addr = addr_off;
60 msg[1].flags = I2C_M_RD;
63 ret = dm_i2c_xfer(dev, msg, 2);
65 debug("%s: read failed, reg=%.2x, value=%p, ret=%d\n",
66 __func__, (int)reg_addr, value, ret);
74 static int anx6345_write_r0(struct udevice *dev, unsigned char reg_addr,
77 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
79 return anx6345_write(dev, chip->chip_addr, reg_addr, value);
82 static int anx6345_read_r0(struct udevice *dev, unsigned char reg_addr,
85 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
87 return anx6345_read(dev, chip->chip_addr, reg_addr, value);
90 static int anx6345_write_r1(struct udevice *dev, unsigned char reg_addr,
93 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
95 return anx6345_write(dev, chip->chip_addr + 1, reg_addr, value);
98 static int anx6345_read_r1(struct udevice *dev, unsigned char reg_addr,
101 struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
103 return anx6345_read(dev, chip->chip_addr + 1, reg_addr, value);
106 static int anx6345_set_backlight(struct udevice *dev, int percent)
111 static int anx6345_aux_wait(struct udevice *dev)
113 int ret = -ETIMEDOUT;
118 anx6345_read_r0(dev, ANX9804_DP_AUX_CH_CTL_2, &v);
119 if (!(v & ANX9804_AUX_EN)) {
127 debug("%s: timed out waiting for AUX_EN to clear\n", __func__);
134 anx6345_read_r1(dev, ANX9804_DP_INT_STA, &v);
135 if (v & ANX9804_RPLY_RECEIV) {
143 debug("%s: timed out waiting to receive reply\n", __func__);
147 /* Clear RPLY_RECEIV bit */
148 anx6345_write_r1(dev, ANX9804_DP_INT_STA, v);
150 anx6345_read_r0(dev, ANX9804_AUX_CH_STA, &v);
151 if ((v & ANX9804_AUX_STATUS_MASK) != 0) {
152 debug("AUX status: %d\n", v & ANX9804_AUX_STATUS_MASK);
159 static void anx6345_aux_addr(struct udevice *dev, u32 addr)
164 anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_7_0, val);
165 val = (addr >> 8) & 0xff;
166 anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_15_8, val);
167 val = (addr >> 16) & 0x0f;
168 anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_19_16, val);
171 static int anx6345_aux_transfer(struct udevice *dev, u8 req,
172 u32 addr, u8 *buf, size_t len)
176 u8 ctrl2 = ANX9804_AUX_EN;
182 ctrl1 |= ANX9804_AUX_LENGTH(len);
184 ctrl2 |= ANX9804_ADDR_ONLY;
186 if (len && !(req & ANX9804_AUX_TX_COMM_READ)) {
187 for (i = 0; i < len; i++)
188 anx6345_write_r0(dev, ANX9804_BUF_DATA_0 + i, buf[i]);
191 anx6345_aux_addr(dev, addr);
192 anx6345_write_r0(dev, ANX9804_DP_AUX_CH_CTL_1, ctrl1);
193 anx6345_write_r0(dev, ANX9804_DP_AUX_CH_CTL_2, ctrl2);
194 ret = anx6345_aux_wait(dev);
196 debug("AUX transaction timed out\n");
200 if (len && (req & ANX9804_AUX_TX_COMM_READ)) {
201 for (i = 0; i < len; i++)
202 anx6345_read_r0(dev, ANX9804_BUF_DATA_0 + i, &buf[i]);
208 static int anx6345_read_aux_i2c(struct udevice *dev, u8 chip_addr,
209 u8 offset, size_t count, u8 *buf)
215 for (i = 0; i < count; i += 16) {
216 cur_cnt = (count - i) > 16 ? 16 : count - i;
217 cur_offset = offset + i;
218 ret = anx6345_aux_transfer(dev, ANX9804_AUX_TX_COMM_MOT,
219 chip_addr, &cur_offset, 1);
221 debug("%s: failed to set i2c offset: %d\n",
225 ret = anx6345_aux_transfer(dev, ANX9804_AUX_TX_COMM_READ,
226 chip_addr, buf + i, cur_cnt);
228 debug("%s: failed to read from i2c device: %d\n",
237 static int anx6345_read_dpcd(struct udevice *dev, u32 reg, u8 *val)
241 ret = anx6345_aux_transfer(dev,
242 ANX9804_AUX_TX_COMM_READ |
243 ANX9804_AUX_TX_COMM_DP_TRANSACTION,
246 debug("Failed to read DPCD\n");
253 static int anx6345_read_edid(struct udevice *dev, u8 *buf, int size)
255 struct anx6345_priv *priv = dev_get_priv(dev);
257 if (size > EDID_SIZE)
259 memcpy(buf, priv->edid, size);
264 static int anx6345_attach(struct udevice *dev)
270 static int anx6345_enable(struct udevice *dev)
272 u8 chipid, colordepth, lanes, data_rate, c;
274 struct display_timing timing;
275 struct anx6345_priv *priv = dev_get_priv(dev);
277 /* Deassert reset and enable power */
278 ret = video_bridge_set_active(dev, true);
283 anx6345_write_r1(dev, ANX9804_RST_CTRL_REG, 1);
285 anx6345_write_r1(dev, ANX9804_RST_CTRL_REG, 0);
287 /* Write 0 to the powerdown reg (powerup everything) */
288 anx6345_write_r1(dev, ANX9804_POWERD_CTRL_REG, 0);
290 ret = anx6345_read_r1(dev, ANX9804_DEV_IDH_REG, &chipid);
292 debug("%s: read id failed: %d\n", __func__, ret);
296 debug("ANX63xx detected.\n");
299 debug("Error anx6345 chipid mismatch: %.2x\n", (int)chipid);
303 for (i = 0; i < 100; i++) {
304 anx6345_read_r0(dev, ANX9804_SYS_CTRL2_REG, &c);
305 anx6345_write_r0(dev, ANX9804_SYS_CTRL2_REG, c);
306 anx6345_read_r0(dev, ANX9804_SYS_CTRL2_REG, &c);
307 if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
313 debug("Error anx6345 clock is not stable\n");
315 /* Set a bunch of analog related register values */
316 anx6345_write_r0(dev, ANX9804_PLL_CTRL_REG, 0x00);
317 anx6345_write_r1(dev, ANX9804_ANALOG_DEBUG_REG1, 0x70);
318 anx6345_write_r0(dev, ANX9804_LINK_DEBUG_REG, 0x30);
321 anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG,
322 ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
324 /* Power up and configure lanes */
325 anx6345_write_r0(dev, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
326 anx6345_write_r0(dev, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
327 anx6345_write_r0(dev, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
328 anx6345_write_r0(dev, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
329 anx6345_write_r0(dev, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
332 anx6345_write_r1(dev, ANX9804_RST_CTRL2_REG,
333 ANX9804_RST_CTRL2_AUX);
334 anx6345_write_r1(dev, ANX9804_RST_CTRL2_REG, 0);
336 /* Powerdown audio and some other unused bits */
337 anx6345_write_r1(dev, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
338 anx6345_write_r0(dev, ANX9804_HDCP_CONTROL_0_REG, 0x00);
339 anx6345_write_r0(dev, 0xa7, 0x00);
341 anx6345_read_aux_i2c(dev, 0x50, 0x0, EDID_SIZE, priv->edid);
342 if (edid_get_timing(priv->edid, EDID_SIZE, &timing, &bpp) != 0) {
343 debug("Failed to parse EDID\n");
346 debug("%s: panel found: %dx%d, bpp %d\n", __func__,
347 timing.hactive.typ, timing.vactive.typ, bpp);
349 colordepth = 0x00; /* 6 bit */
351 colordepth = 0x10; /* 8 bit */
352 anx6345_write_r1(dev, ANX9804_VID_CTRL2_REG, colordepth);
354 if (anx6345_read_dpcd(dev, DP_MAX_LINK_RATE, &data_rate)) {
355 debug("%s: Failed to DP_MAX_LINK_RATE\n", __func__);
358 debug("%s: data_rate: %d\n", __func__, (int)data_rate);
359 if (anx6345_read_dpcd(dev, DP_MAX_LANE_COUNT, &lanes)) {
360 debug("%s: Failed to read DP_MAX_LANE_COUNT\n", __func__);
363 lanes &= DP_MAX_LANE_COUNT_MASK;
364 debug("%s: lanes: %d\n", __func__, (int)lanes);
366 /* Set data-rate / lanes */
367 anx6345_write_r0(dev, ANX9804_LINK_BW_SET_REG, data_rate);
368 anx6345_write_r0(dev, ANX9804_LANE_COUNT_SET_REG, lanes);
371 anx6345_write_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG,
372 ANX9804_LINK_TRAINING_CTRL_EN);
374 for (i = 0; i < 100; i++) {
375 anx6345_read_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG, &c);
376 if ((chipid == 0x63) && (c & 0x80) == 0)
382 debug("Error anx6345 link training timeout\n");
387 anx6345_write_r1(dev, ANX9804_VID_CTRL1_REG,
388 ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
389 /* Force stream valid */
390 anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG,
391 ANX9804_SYS_CTRL3_F_HPD |
392 ANX9804_SYS_CTRL3_HPD_CTRL |
393 ANX9804_SYS_CTRL3_F_VALID |
394 ANX9804_SYS_CTRL3_VALID_CTRL);
399 static int anx6345_probe(struct udevice *dev)
401 if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
402 return -EPROTONOSUPPORT;
404 return anx6345_enable(dev);
407 struct video_bridge_ops anx6345_ops = {
408 .attach = anx6345_attach,
409 .set_backlight = anx6345_set_backlight,
410 .read_edid = anx6345_read_edid,
413 static const struct udevice_id anx6345_ids[] = {
414 { .compatible = "analogix,anx6345", },
418 U_BOOT_DRIVER(analogix_anx6345) = {
419 .name = "analogix_anx6345",
420 .id = UCLASS_VIDEO_BRIDGE,
421 .of_match = anx6345_ids,
422 .probe = anx6345_probe,
424 .priv_auto_alloc_size = sizeof(struct anx6345_priv),