1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for AT91/AT32 MULTI LAYER LCD Controller
5 * Copyright (C) 2012 Atmel Corporation
12 #include <asm/arch/gpio.h>
13 #include <asm/arch/clk.h>
20 #include <atmel_hlcdc.h>
22 #if defined(CONFIG_LCD_LOGO)
26 DECLARE_GLOBAL_DATA_PTR;
28 #ifndef CONFIG_DM_VIDEO
30 /* configurable parameters */
31 #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
32 #define ATMEL_LCDC_DMA_BURST_LEN 8
33 #ifndef ATMEL_LCDC_GUARD_TIME
34 #define ATMEL_LCDC_GUARD_TIME 1
37 #define ATMEL_LCDC_FIFO_SIZE 512
40 * the CLUT register map as following
41 * RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0)
43 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
45 writel(panel_info.mmio + ATMEL_LCDC_LUT(regno),
46 ((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk)
47 | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk)
48 | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk));
51 ushort *configuration_get_cmap(void)
53 #if defined(CONFIG_LCD_LOGO)
54 return bmp_logo_palette;
60 void lcd_ctrl_init(void *lcdbase)
63 struct lcd_dma_desc *desc;
64 struct atmel_hlcd_regs *regs;
70 regs = (struct atmel_hlcd_regs *)panel_info.mmio;
72 /* Disable DISP signal */
73 writel(LCDC_LCDDIS_DISPDIS, ®s->lcdc_lcddis);
74 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
77 printf("%s: %d: Timeout!\n", __func__, __LINE__);
78 /* Disable synchronization */
79 writel(LCDC_LCDDIS_SYNCDIS, ®s->lcdc_lcddis);
80 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
83 printf("%s: %d: Timeout!\n", __func__, __LINE__);
84 /* Disable pixel clock */
85 writel(LCDC_LCDDIS_CLKDIS, ®s->lcdc_lcddis);
86 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
89 printf("%s: %d: Timeout!\n", __func__, __LINE__);
91 writel(LCDC_LCDDIS_PWMDIS, ®s->lcdc_lcddis);
92 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
95 printf("%s: %d: Timeout!\n", __func__, __LINE__);
98 value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
99 if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
103 /* Using system clock as pixel clock */
104 writel(LCDC_LCDCFG0_CLKDIV(0)
105 | LCDC_LCDCFG0_CGDISHCR
106 | LCDC_LCDCFG0_CGDISHEO
107 | LCDC_LCDCFG0_CGDISOVR1
108 | LCDC_LCDCFG0_CGDISBASE
109 | panel_info.vl_clk_pol
110 | LCDC_LCDCFG0_CLKSEL,
111 ®s->lcdc_lcdcfg0);
114 writel(LCDC_LCDCFG0_CLKDIV(value - 2)
115 | LCDC_LCDCFG0_CGDISHCR
116 | LCDC_LCDCFG0_CGDISHEO
117 | LCDC_LCDCFG0_CGDISOVR1
118 | LCDC_LCDCFG0_CGDISBASE
119 | panel_info.vl_clk_pol,
120 ®s->lcdc_lcdcfg0);
123 /* Initialize control register 5 */
126 value |= panel_info.vl_sync;
128 #ifndef LCD_OUTPUT_BPP
129 /* Output is 24bpp */
130 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
132 switch (LCD_OUTPUT_BPP) {
134 value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
137 value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
140 value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
143 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
151 value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME);
152 value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
153 writel(value, ®s->lcdc_lcdcfg5);
155 /* Vertical & Horizontal Timing */
156 value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1);
157 value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
158 writel(value, ®s->lcdc_lcdcfg1);
160 value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin);
161 value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1);
162 writel(value, ®s->lcdc_lcdcfg2);
164 value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1);
165 value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1);
166 writel(value, ®s->lcdc_lcdcfg3);
169 value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1);
170 value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1);
171 writel(value, ®s->lcdc_lcdcfg4);
173 writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
174 ®s->lcdc_basecfg0);
176 switch (NBITS(panel_info.vl_bpix)) {
178 writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
179 ®s->lcdc_basecfg1);
182 writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
183 ®s->lcdc_basecfg1);
190 writel(LCDC_BASECFG2_XSTRIDE(0), ®s->lcdc_basecfg2);
191 writel(0, ®s->lcdc_basecfg3);
192 writel(LCDC_BASECFG4_DMA, ®s->lcdc_basecfg4);
194 /* Disable all interrupts */
195 writel(~0UL, ®s->lcdc_lcdidr);
196 writel(~0UL, ®s->lcdc_baseidr);
198 /* Setup the DMA descriptor, this descriptor will loop to itself */
199 desc = (struct lcd_dma_desc *)(lcdbase - 16);
201 desc->address = (u32)lcdbase;
202 /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
203 desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
204 | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
205 desc->next = (u32)desc;
207 /* Flush the DMA descriptor if we enabled dcache */
208 flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
210 writel(desc->address, ®s->lcdc_baseaddr);
211 writel(desc->control, ®s->lcdc_basectrl);
212 writel(desc->next, ®s->lcdc_basenext);
213 writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
214 ®s->lcdc_basecher);
217 value = readl(®s->lcdc_lcden);
218 writel(value | LCDC_LCDEN_CLKEN, ®s->lcdc_lcden);
219 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
222 printf("%s: %d: Timeout!\n", __func__, __LINE__);
223 value = readl(®s->lcdc_lcden);
224 writel(value | LCDC_LCDEN_SYNCEN, ®s->lcdc_lcden);
225 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
228 printf("%s: %d: Timeout!\n", __func__, __LINE__);
229 value = readl(®s->lcdc_lcden);
230 writel(value | LCDC_LCDEN_DISPEN, ®s->lcdc_lcden);
231 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
234 printf("%s: %d: Timeout!\n", __func__, __LINE__);
235 value = readl(®s->lcdc_lcden);
236 writel(value | LCDC_LCDEN_PWMEN, ®s->lcdc_lcden);
237 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
240 printf("%s: %d: Timeout!\n", __func__, __LINE__);
242 /* Enable flushing if we enabled dcache */
243 lcd_set_flush_dcache(1);
249 LCD_MAX_WIDTH = 1024,
250 LCD_MAX_HEIGHT = 768,
251 LCD_MAX_LOG2_BPP = VIDEO_BPP16,
254 struct atmel_hlcdc_priv {
255 struct atmel_hlcd_regs *regs;
256 struct display_timing timing;
257 unsigned int vl_bpix;
258 unsigned int output_mode;
259 unsigned int guard_time;
263 static int at91_hlcdc_enable_clk(struct udevice *dev)
265 struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
270 ret = clk_get_by_index(dev, 0, &clk);
274 ret = clk_enable(&clk);
278 clk_rate = clk_get_rate(&clk);
284 priv->clk_rate = clk_rate;
291 static void atmel_hlcdc_init(struct udevice *dev)
293 struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
294 struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
295 struct atmel_hlcd_regs *regs = priv->regs;
296 struct display_timing *timing = &priv->timing;
297 struct lcd_dma_desc *desc;
298 unsigned long value, vl_clk_pol;
301 /* Disable DISP signal */
302 writel(LCDC_LCDDIS_DISPDIS, ®s->lcdc_lcddis);
303 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
306 printf("%s: %d: Timeout!\n", __func__, __LINE__);
307 /* Disable synchronization */
308 writel(LCDC_LCDDIS_SYNCDIS, ®s->lcdc_lcddis);
309 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
312 printf("%s: %d: Timeout!\n", __func__, __LINE__);
313 /* Disable pixel clock */
314 writel(LCDC_LCDDIS_CLKDIS, ®s->lcdc_lcddis);
315 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
318 printf("%s: %d: Timeout!\n", __func__, __LINE__);
320 writel(LCDC_LCDDIS_PWMDIS, ®s->lcdc_lcddis);
321 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
324 printf("%s: %d: Timeout!\n", __func__, __LINE__);
326 /* Set pixel clock */
327 value = priv->clk_rate / timing->pixelclock.typ;
328 if (priv->clk_rate % timing->pixelclock.typ)
332 if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
333 vl_clk_pol = LCDC_LCDCFG0_CLKPOL;
336 /* Using system clock as pixel clock */
337 writel(LCDC_LCDCFG0_CLKDIV(0)
338 | LCDC_LCDCFG0_CGDISHCR
339 | LCDC_LCDCFG0_CGDISHEO
340 | LCDC_LCDCFG0_CGDISOVR1
341 | LCDC_LCDCFG0_CGDISBASE
343 | LCDC_LCDCFG0_CLKSEL,
344 ®s->lcdc_lcdcfg0);
347 writel(LCDC_LCDCFG0_CLKDIV(value - 2)
348 | LCDC_LCDCFG0_CGDISHCR
349 | LCDC_LCDCFG0_CGDISHEO
350 | LCDC_LCDCFG0_CGDISOVR1
351 | LCDC_LCDCFG0_CGDISBASE
353 ®s->lcdc_lcdcfg0);
356 /* Initialize control register 5 */
359 if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
360 value |= LCDC_LCDCFG5_HSPOL;
361 if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
362 value |= LCDC_LCDCFG5_VSPOL;
364 switch (priv->output_mode) {
366 value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
369 value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
372 value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
375 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
382 value |= LCDC_LCDCFG5_GUARDTIME(priv->guard_time);
383 value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
384 writel(value, ®s->lcdc_lcdcfg5);
386 /* Vertical & Horizontal Timing */
387 value = LCDC_LCDCFG1_VSPW(timing->vsync_len.typ - 1);
388 value |= LCDC_LCDCFG1_HSPW(timing->hsync_len.typ - 1);
389 writel(value, ®s->lcdc_lcdcfg1);
391 value = LCDC_LCDCFG2_VBPW(timing->vback_porch.typ);
392 value |= LCDC_LCDCFG2_VFPW(timing->vfront_porch.typ - 1);
393 writel(value, ®s->lcdc_lcdcfg2);
395 value = LCDC_LCDCFG3_HBPW(timing->hback_porch.typ - 1);
396 value |= LCDC_LCDCFG3_HFPW(timing->hfront_porch.typ - 1);
397 writel(value, ®s->lcdc_lcdcfg3);
400 value = LCDC_LCDCFG4_RPF(timing->vactive.typ - 1);
401 value |= LCDC_LCDCFG4_PPL(timing->hactive.typ - 1);
402 writel(value, ®s->lcdc_lcdcfg4);
404 writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
405 ®s->lcdc_basecfg0);
407 switch (VNBITS(priv->vl_bpix)) {
409 writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
410 ®s->lcdc_basecfg1);
413 writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
414 ®s->lcdc_basecfg1);
421 writel(LCDC_BASECFG2_XSTRIDE(0), ®s->lcdc_basecfg2);
422 writel(0, ®s->lcdc_basecfg3);
423 writel(LCDC_BASECFG4_DMA, ®s->lcdc_basecfg4);
425 /* Disable all interrupts */
426 writel(~0UL, ®s->lcdc_lcdidr);
427 writel(~0UL, ®s->lcdc_baseidr);
429 /* Setup the DMA descriptor, this descriptor will loop to itself */
430 desc = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*desc));
434 desc->address = (u32)uc_plat->base;
436 /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
437 desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
438 | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
439 desc->next = (u32)desc;
441 /* Flush the DMA descriptor if we enabled dcache */
442 flush_dcache_range((u32)desc,
443 ALIGN(((u32)desc + sizeof(*desc)),
444 CONFIG_SYS_CACHELINE_SIZE));
446 writel(desc->address, ®s->lcdc_baseaddr);
447 writel(desc->control, ®s->lcdc_basectrl);
448 writel(desc->next, ®s->lcdc_basenext);
449 writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
450 ®s->lcdc_basecher);
453 value = readl(®s->lcdc_lcden);
454 writel(value | LCDC_LCDEN_CLKEN, ®s->lcdc_lcden);
455 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
458 printf("%s: %d: Timeout!\n", __func__, __LINE__);
459 value = readl(®s->lcdc_lcden);
460 writel(value | LCDC_LCDEN_SYNCEN, ®s->lcdc_lcden);
461 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
464 printf("%s: %d: Timeout!\n", __func__, __LINE__);
465 value = readl(®s->lcdc_lcden);
466 writel(value | LCDC_LCDEN_DISPEN, ®s->lcdc_lcden);
467 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
470 printf("%s: %d: Timeout!\n", __func__, __LINE__);
471 value = readl(®s->lcdc_lcden);
472 writel(value | LCDC_LCDEN_PWMEN, ®s->lcdc_lcden);
473 ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
476 printf("%s: %d: Timeout!\n", __func__, __LINE__);
479 static int atmel_hlcdc_probe(struct udevice *dev)
481 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
482 struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
485 ret = at91_hlcdc_enable_clk(dev);
489 atmel_hlcdc_init(dev);
491 uc_priv->xsize = priv->timing.hactive.typ;
492 uc_priv->ysize = priv->timing.vactive.typ;
493 uc_priv->bpix = priv->vl_bpix;
495 /* Enable flushing if we enabled dcache */
496 video_set_flush_dcache(dev, true);
501 static int atmel_hlcdc_ofdata_to_platdata(struct udevice *dev)
503 struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
504 const void *blob = gd->fdt_blob;
505 int node = dev_of_offset(dev);
507 priv->regs = (struct atmel_hlcd_regs *)devfdt_get_addr(dev);
509 debug("%s: No display controller address\n", __func__);
513 if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
515 debug("%s: Failed to decode display timing\n", __func__);
519 if (priv->timing.hactive.typ > LCD_MAX_WIDTH)
520 priv->timing.hactive.typ = LCD_MAX_WIDTH;
522 if (priv->timing.vactive.typ > LCD_MAX_HEIGHT)
523 priv->timing.vactive.typ = LCD_MAX_HEIGHT;
525 priv->vl_bpix = fdtdec_get_int(blob, node, "atmel,vl-bpix", 0);
526 if (!priv->vl_bpix) {
527 debug("%s: Failed to get bits per pixel\n", __func__);
531 priv->output_mode = fdtdec_get_int(blob, node, "atmel,output-mode", 24);
532 priv->guard_time = fdtdec_get_int(blob, node, "atmel,guard-time", 1);
537 static int atmel_hlcdc_bind(struct udevice *dev)
539 struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
541 uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
542 (1 << LCD_MAX_LOG2_BPP) / 8;
544 debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
549 static const struct udevice_id atmel_hlcdc_ids[] = {
550 { .compatible = "atmel,sama5d2-hlcdc" },
551 { .compatible = "atmel,at91sam9x5-hlcdc" },
555 U_BOOT_DRIVER(atmel_hlcdfb) = {
556 .name = "atmel_hlcdfb",
558 .of_match = atmel_hlcdc_ids,
559 .bind = atmel_hlcdc_bind,
560 .probe = atmel_hlcdc_probe,
561 .ofdata_to_platdata = atmel_hlcdc_ofdata_to_platdata,
562 .priv_auto_alloc_size = sizeof(struct atmel_hlcdc_priv),