2 * Driver for AT91/AT32 MULTI LAYER LCD Controller
4 * Copyright (C) 2012 Atmel Corporation
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/gpio.h>
28 #include <asm/arch/clk.h>
30 #include <atmel_hlcdc.h>
32 void *lcd_base; /* Start of framebuffer memory */
34 /* configurable parameters */
35 #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
36 #define ATMEL_LCDC_DMA_BURST_LEN 8
37 #ifndef ATMEL_LCDC_GUARD_TIME
38 #define ATMEL_LCDC_GUARD_TIME 1
41 #define ATMEL_LCDC_FIFO_SIZE 512
43 #define lcdc_readl(reg) __raw_readl((reg))
44 #define lcdc_writel(reg, val) __raw_writel((val), (reg))
47 * the CLUT register map as following
48 * RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0)
50 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
52 lcdc_writel(((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk)
53 | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk)
54 | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk),
55 panel_info.mmio + ATMEL_LCDC_LUT(regno));
58 void lcd_ctrl_init(void *lcdbase)
61 struct lcd_dma_desc *desc;
62 struct atmel_hlcd_regs *regs;
67 regs = (struct atmel_hlcd_regs *)panel_info.mmio;
69 /* Disable DISP signal */
70 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_DISPDIS);
71 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS))
73 /* Disable synchronization */
74 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_SYNCDIS);
75 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS))
77 /* Disable pixel clock */
78 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_CLKDIS);
79 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS))
82 lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_PWMDIS);
83 while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS))
87 value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
88 if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
92 /* Using system clock as pixel clock */
93 lcdc_writel(®s->lcdc_lcdcfg0,
94 LCDC_LCDCFG0_CLKDIV(0)
95 | LCDC_LCDCFG0_CGDISHCR
96 | LCDC_LCDCFG0_CGDISHEO
97 | LCDC_LCDCFG0_CGDISOVR1
98 | LCDC_LCDCFG0_CGDISBASE
99 | panel_info.vl_clk_pol
100 | LCDC_LCDCFG0_CLKSEL);
103 lcdc_writel(®s->lcdc_lcdcfg0,
104 LCDC_LCDCFG0_CLKDIV(value - 2)
105 | LCDC_LCDCFG0_CGDISHCR
106 | LCDC_LCDCFG0_CGDISHEO
107 | LCDC_LCDCFG0_CGDISOVR1
108 | LCDC_LCDCFG0_CGDISBASE
109 | panel_info.vl_clk_pol);
112 /* Initialize control register 5 */
115 value |= panel_info.vl_sync;
117 #ifndef LCD_OUTPUT_BPP
118 /* Output is 24bpp */
119 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
121 switch (LCD_OUTPUT_BPP) {
123 value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
126 value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
129 value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
132 value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
140 value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME);
141 value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
142 lcdc_writel(®s->lcdc_lcdcfg5, value);
144 /* Vertical & Horizontal Timing */
145 value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1);
146 value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
147 lcdc_writel(®s->lcdc_lcdcfg1, value);
149 value = LCDC_LCDCFG2_VBPW(panel_info.vl_lower_margin);
150 value |= LCDC_LCDCFG2_VFPW(panel_info.vl_upper_margin - 1);
151 lcdc_writel(®s->lcdc_lcdcfg2, value);
153 value = LCDC_LCDCFG3_HBPW(panel_info.vl_right_margin - 1);
154 value |= LCDC_LCDCFG3_HFPW(panel_info.vl_left_margin - 1);
155 lcdc_writel(®s->lcdc_lcdcfg3, value);
158 value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1);
159 value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1);
160 lcdc_writel(®s->lcdc_lcdcfg4, value);
162 lcdc_writel(®s->lcdc_basecfg0,
163 LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO);
165 switch (NBITS(panel_info.vl_bpix)) {
167 lcdc_writel(®s->lcdc_basecfg1,
168 LCDC_BASECFG1_RGBMODE_16BPP_RGB_565);
175 lcdc_writel(®s->lcdc_basecfg2, LCDC_BASECFG2_XSTRIDE(0));
176 lcdc_writel(®s->lcdc_basecfg3, 0);
177 lcdc_writel(®s->lcdc_basecfg4, LCDC_BASECFG4_DMA);
179 /* Disable all interrupts */
180 lcdc_writel(®s->lcdc_lcdidr, ~0UL);
181 lcdc_writel(®s->lcdc_baseidr, ~0UL);
183 /* Setup the DMA descriptor, this descriptor will loop to itself */
184 desc = (struct lcd_dma_desc *)(lcdbase - 16);
186 desc->address = (u32)lcdbase;
187 /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
188 desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
189 | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
190 desc->next = (u32)desc;
192 lcdc_writel(®s->lcdc_baseaddr, desc->address);
193 lcdc_writel(®s->lcdc_basectrl, desc->control);
194 lcdc_writel(®s->lcdc_basenext, desc->next);
195 lcdc_writel(®s->lcdc_basecher, LCDC_BASECHER_CHEN |
196 LCDC_BASECHER_UPDATEEN);
199 value = lcdc_readl(®s->lcdc_lcden);
200 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_CLKEN);
201 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS))
203 value = lcdc_readl(®s->lcdc_lcden);
204 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_SYNCEN);
205 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS))
207 value = lcdc_readl(®s->lcdc_lcden);
208 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_DISPEN);
209 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS))
211 value = lcdc_readl(®s->lcdc_lcden);
212 lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_PWMEN);
213 while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS))