2 * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus.
4 * Interrupt support is added. Now, it has been tested
5 * on ULI1575 chip and works well with USB keyboard.
8 * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com>
11 * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
13 * Note: Much of this code has been derived from Linux 2.4
14 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
15 * (C) Copyright 2000-2002 David Brownell
17 * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
18 * ebenard@eukrea.com - based on s3c24x0's driver
20 * See file CREDITS for list of people who contributed to this
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License as
25 * published by the Free Software Foundation; either version 2 of
26 * the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
41 * 1 - Read doc/README.generic_usb_ohci
42 * 2 - this driver is intended for use with USB Mass Storage Devices
43 * (BBB) and USB keyboard. There is NO support for Isochronous pipes!
44 * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG
45 * to activate workaround for bug #41 or this driver will NOT work!
50 #ifdef CONFIG_USB_OHCI_NEW
52 #include <asm/byteorder.h>
54 #if defined(CONFIG_PCI_OHCI)
62 #ifdef CONFIG_AT91RM9200
63 #include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */
66 #if defined(CONFIG_ARM920T) || \
67 defined(CONFIG_S3C2400) || \
68 defined(CONFIG_S3C2410) || \
69 defined(CONFIG_440EP) || \
70 defined(CONFIG_PCI_OHCI) || \
71 defined(CONFIG_MPC5200)
72 # define OHCI_USE_NPS /* force NoPowerSwitching mode */
75 #undef OHCI_VERBOSE_DEBUG /* not always helpful */
78 #undef OHCI_FILL_TRACE
80 /* For initializing controller (mask in an HCFS mode too) */
81 #define OHCI_CONTROL_INIT \
82 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
85 * e.g. PCI controllers need this
87 #ifdef CFG_OHCI_SWAP_REG_ACCESS
88 # define readl(a) __swap_32(*((vu_long *)(a)))
89 # define writel(a, b) (*((vu_long *)(b)) = __swap_32((vu_long)a))
91 # define readl(a) (*((vu_long *)(a)))
92 # define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
93 #endif /* CFG_OHCI_SWAP_REG_ACCESS */
95 #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
97 #ifdef CONFIG_PCI_OHCI
98 static struct pci_device_id ohci_pci_ids[] = {
99 {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */
100 {0x1033, 0x0035}, /* NEC PCI OHCI module ids */
101 /* Please add supported PCI OHCI controller ids here */
107 #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
109 #define dbg(format, arg...) do {} while(0)
111 #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
114 #define info(format, arg...) printf("INFO: " format "\n", ## arg)
116 #define info(format, arg...) do {} while(0)
119 #ifdef CFG_OHCI_BE_CONTROLLER
120 # define m16_swap(x) cpu_to_be16(x)
121 # define m32_swap(x) cpu_to_be32(x)
123 # define m16_swap(x) cpu_to_le16(x)
124 # define m32_swap(x) cpu_to_le32(x)
125 #endif /* CFG_OHCI_BE_CONTROLLER */
129 /* this must be aligned to a 256 byte boundary */
130 struct ohci_hcca ghcca[1];
131 /* a pointer to the aligned storage */
132 struct ohci_hcca *phcca;
133 /* this allocates EDs for all possible endpoints */
134 struct ohci_device ohci_dev;
137 /* device which was disconnected */
138 struct usb_device *devgone;
140 /*-------------------------------------------------------------------------*/
142 /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
143 * The erratum (#4) description is incorrect. AMD's workaround waits
144 * till some bits (mostly reserved) are clear; ok for all revs.
146 #define OHCI_QUIRK_AMD756 0xabcd
147 #define read_roothub(hc, register, mask) ({ \
148 u32 temp = readl (&hc->regs->roothub.register); \
149 if (hc->flags & OHCI_QUIRK_AMD756) \
150 while (temp & mask) \
151 temp = readl (&hc->regs->roothub.register); \
154 static u32 roothub_a (struct ohci *hc)
155 { return read_roothub (hc, a, 0xfc0fe000); }
156 static inline u32 roothub_b (struct ohci *hc)
157 { return readl (&hc->regs->roothub.b); }
158 static inline u32 roothub_status (struct ohci *hc)
159 { return readl (&hc->regs->roothub.status); }
160 static u32 roothub_portstatus (struct ohci *hc, int i)
161 { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
163 /* forward declaration */
164 static int hc_interrupt (void);
166 td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
167 int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
169 /*-------------------------------------------------------------------------*
170 * URB support functions
171 *-------------------------------------------------------------------------*/
173 /* free HCD-private data associated with this URB */
175 static void urb_free_priv (urb_priv_t * urb)
181 last = urb->length - 1;
183 for (i = 0; i <= last; i++) {
194 /*-------------------------------------------------------------------------*/
197 static int sohci_get_current_frame_number (struct usb_device * dev);
199 /* debug| print the main components of an URB
200 * small: 0) header + data packets 1) just header */
202 static void pkt_print (urb_priv_t *purb, struct usb_device * dev,
203 unsigned long pipe, void * buffer,
204 int transfer_len, struct devrequest * setup, char * str, int small)
206 dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
208 sohci_get_current_frame_number (dev),
209 usb_pipedevice (pipe),
210 usb_pipeendpoint (pipe),
211 usb_pipeout (pipe)? 'O': 'I',
212 usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
213 (usb_pipecontrol (pipe)? "CTRL": "BULK"),
214 (purb ? purb->actual_length : 0),
215 transfer_len, dev->status);
216 #ifdef OHCI_VERBOSE_DEBUG
220 if (usb_pipecontrol (pipe)) {
221 printf (__FILE__ ": cmd(8):");
222 for (i = 0; i < 8 ; i++)
223 printf (" %02x", ((__u8 *) setup) [i]);
226 if (transfer_len > 0 && buffer) {
227 printf (__FILE__ ": data(%d/%d):",
228 (purb ? purb->actual_length : 0),
230 len = usb_pipeout (pipe)?
232 (purb ? purb->actual_length : 0);
233 for (i = 0; i < 16 && i < len; i++)
234 printf (" %02x", ((__u8 *) buffer) [i]);
235 printf ("%s\n", i < len? "...": "");
241 /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
242 void ep_print_int_eds (ohci_t *ohci, char * str) {
245 for (i= 0; i < 32; i++) {
247 ed_p = &(ohci->hcca->int_table [i]);
250 printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
251 while (*ed_p != 0 && j--) {
252 ed_t *ed = (ed_t *)m32_swap(ed_p);
253 printf (" ed: %4x;", ed->hwINFO);
254 ed_p = &ed->hwNextED;
260 static void ohci_dump_intr_mask (char *label, __u32 mask)
262 dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
265 (mask & OHCI_INTR_MIE) ? " MIE" : "",
266 (mask & OHCI_INTR_OC) ? " OC" : "",
267 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
268 (mask & OHCI_INTR_FNO) ? " FNO" : "",
269 (mask & OHCI_INTR_UE) ? " UE" : "",
270 (mask & OHCI_INTR_RD) ? " RD" : "",
271 (mask & OHCI_INTR_SF) ? " SF" : "",
272 (mask & OHCI_INTR_WDH) ? " WDH" : "",
273 (mask & OHCI_INTR_SO) ? " SO" : ""
277 static void maybe_print_eds (char *label, __u32 value)
279 ed_t *edp = (ed_t *)value;
282 dbg ("%s %08x", label, value);
283 dbg ("%08x", edp->hwINFO);
284 dbg ("%08x", edp->hwTailP);
285 dbg ("%08x", edp->hwHeadP);
286 dbg ("%08x", edp->hwNextED);
290 static char * hcfs2string (int state)
293 case OHCI_USB_RESET: return "reset";
294 case OHCI_USB_RESUME: return "resume";
295 case OHCI_USB_OPER: return "operational";
296 case OHCI_USB_SUSPEND: return "suspend";
301 /* dump control and status registers */
302 static void ohci_dump_status (ohci_t *controller)
304 struct ohci_regs *regs = controller->regs;
307 temp = readl (®s->revision) & 0xff;
309 dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
311 temp = readl (®s->control);
312 dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
313 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
314 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
315 (temp & OHCI_CTRL_IR) ? " IR" : "",
316 hcfs2string (temp & OHCI_CTRL_HCFS),
317 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
318 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
319 (temp & OHCI_CTRL_IE) ? " IE" : "",
320 (temp & OHCI_CTRL_PLE) ? " PLE" : "",
321 temp & OHCI_CTRL_CBSR
324 temp = readl (®s->cmdstatus);
325 dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
326 (temp & OHCI_SOC) >> 16,
327 (temp & OHCI_OCR) ? " OCR" : "",
328 (temp & OHCI_BLF) ? " BLF" : "",
329 (temp & OHCI_CLF) ? " CLF" : "",
330 (temp & OHCI_HCR) ? " HCR" : ""
333 ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus));
334 ohci_dump_intr_mask ("intrenable", readl (®s->intrenable));
336 maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent));
338 maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead));
339 maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent));
341 maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead));
342 maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent));
344 maybe_print_eds ("donehead", readl (®s->donehead));
347 static void ohci_dump_roothub (ohci_t *controller, int verbose)
351 temp = roothub_a (controller);
352 ndp = (temp & RH_A_NDP);
353 #ifdef CONFIG_AT91C_PQFP_UHPBUG
354 ndp = (ndp == 2) ? 1:0;
357 dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
358 ((temp & RH_A_POTPGT) >> 24) & 0xff,
359 (temp & RH_A_NOCP) ? " NOCP" : "",
360 (temp & RH_A_OCPM) ? " OCPM" : "",
361 (temp & RH_A_DT) ? " DT" : "",
362 (temp & RH_A_NPS) ? " NPS" : "",
363 (temp & RH_A_PSM) ? " PSM" : "",
366 temp = roothub_b (controller);
367 dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
369 (temp & RH_B_PPCM) >> 16,
372 temp = roothub_status (controller);
373 dbg ("roothub.status: %08x%s%s%s%s%s%s",
375 (temp & RH_HS_CRWE) ? " CRWE" : "",
376 (temp & RH_HS_OCIC) ? " OCIC" : "",
377 (temp & RH_HS_LPSC) ? " LPSC" : "",
378 (temp & RH_HS_DRWE) ? " DRWE" : "",
379 (temp & RH_HS_OCI) ? " OCI" : "",
380 (temp & RH_HS_LPS) ? " LPS" : ""
384 for (i = 0; i < ndp; i++) {
385 temp = roothub_portstatus (controller, i);
386 dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
389 (temp & RH_PS_PRSC) ? " PRSC" : "",
390 (temp & RH_PS_OCIC) ? " OCIC" : "",
391 (temp & RH_PS_PSSC) ? " PSSC" : "",
392 (temp & RH_PS_PESC) ? " PESC" : "",
393 (temp & RH_PS_CSC) ? " CSC" : "",
395 (temp & RH_PS_LSDA) ? " LSDA" : "",
396 (temp & RH_PS_PPS) ? " PPS" : "",
397 (temp & RH_PS_PRS) ? " PRS" : "",
398 (temp & RH_PS_POCI) ? " POCI" : "",
399 (temp & RH_PS_PSS) ? " PSS" : "",
401 (temp & RH_PS_PES) ? " PES" : "",
402 (temp & RH_PS_CCS) ? " CCS" : ""
407 static void ohci_dump (ohci_t *controller, int verbose)
409 dbg ("OHCI controller usb-%s state", controller->slot_name);
411 /* dumps some of the state we know about */
412 ohci_dump_status (controller);
414 ep_print_int_eds (controller, "hcca");
415 dbg ("hcca frame #%04x", controller->hcca->frame_no);
416 ohci_dump_roothub (controller, 1);
420 /*-------------------------------------------------------------------------*
421 * Interface functions (URB)
422 *-------------------------------------------------------------------------*/
424 /* get a transfer request */
426 int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup)
430 urb_priv_t *purb_priv = urb;
432 struct usb_device *dev = urb->dev;
433 unsigned long pipe = urb->pipe;
434 void *buffer = urb->transfer_buffer;
435 int transfer_len = urb->transfer_buffer_length;
436 int interval = urb->interval;
440 /* when controller's hung, permit only roothub cleanup attempts
441 * such as powering down ports */
442 if (ohci->disabled) {
443 err("sohci_submit_job: EPIPE");
447 /* we're about to begin a new transaction here so mark the URB unfinished */
450 /* every endpoint has a ed, locate and fill it */
451 if (!(ed = ep_add_ed (dev, pipe, interval, 1))) {
452 err("sohci_submit_job: ENOMEM");
456 /* for the private part of the URB we need the number of TDs (size) */
457 switch (usb_pipetype (pipe)) {
458 case PIPE_BULK: /* one TD for every 4096 Byte */
459 size = (transfer_len - 1) / 4096 + 1;
461 case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
462 size = (transfer_len == 0)? 2:
463 (transfer_len - 1) / 4096 + 3;
465 case PIPE_INTERRUPT: /* 1 TD */
472 if (size >= (N_URB_TD - 1)) {
473 err("need %d TDs, only have %d", size, N_URB_TD);
476 purb_priv->pipe = pipe;
478 /* fill the private part of the URB */
479 purb_priv->length = size;
481 purb_priv->actual_length = 0;
483 /* allocate the TDs */
484 /* note that td[0] was allocated in ep_add_ed */
485 for (i = 0; i < size; i++) {
486 purb_priv->td[i] = td_alloc (dev);
487 if (!purb_priv->td[i]) {
488 purb_priv->length = i;
489 urb_free_priv (purb_priv);
490 err("sohci_submit_job: ENOMEM");
495 if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
496 urb_free_priv (purb_priv);
497 err("sohci_submit_job: EINVAL");
501 /* link the ed into a chain if is not already */
502 if (ed->state != ED_OPER)
505 /* fill the TDs and link it to the ed */
506 td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
511 static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb)
513 struct ohci_regs *regs = hc->regs;
515 switch (usb_pipetype (urb->pipe)) {
517 /* implicitly requeued */
518 if (urb->dev->irq_handle &&
519 (urb->dev->irq_act_len = urb->actual_length)) {
520 writel (OHCI_INTR_WDH, ®s->intrenable);
521 readl (®s->intrenable); /* PCI posting flush */
522 urb->dev->irq_handle(urb->dev);
523 writel (OHCI_INTR_WDH, ®s->intrdisable);
524 readl (®s->intrdisable); /* PCI posting flush */
526 urb->actual_length = 0;
530 urb->transfer_buffer,
531 urb->transfer_buffer_length,
545 /*-------------------------------------------------------------------------*/
548 /* tell us the current USB frame number */
550 static int sohci_get_current_frame_number (struct usb_device *usb_dev)
552 ohci_t *ohci = &gohci;
554 return m16_swap (ohci->hcca->frame_no);
558 /*-------------------------------------------------------------------------*
559 * ED handling functions
560 *-------------------------------------------------------------------------*/
562 /* search for the right branch to insert an interrupt ed into the int tree
563 * do some load ballancing;
564 * returns the branch and
565 * sets the interval to interval = 2^integer (ld (interval)) */
567 static int ep_int_ballance (ohci_t * ohci, int interval, int load)
571 /* search for the least loaded interrupt endpoint
572 * branch of all 32 branches
574 for (i = 0; i < 32; i++)
575 if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i])
578 branch = branch % interval;
579 for (i = branch; i < 32; i += interval)
580 ohci->ohci_int_load [i] += load;
585 /*-------------------------------------------------------------------------*/
587 /* 2^int( ld (inter)) */
589 static int ep_2_n_interval (int inter)
592 for (i = 0; ((inter >> i) > 1 ) && (i < 5); i++);
596 /*-------------------------------------------------------------------------*/
598 /* the int tree is a binary tree
599 * in order to process it sequentially the indexes of the branches have to be mapped
600 * the mapping reverses the bits of a word of num_bits length */
602 static int ep_rev (int num_bits, int word)
606 for (i = 0; i < num_bits; i++)
607 wout |= (((word >> i) & 1) << (num_bits - i - 1));
611 /*-------------------------------------------------------------------------*
612 * ED handling functions
613 *-------------------------------------------------------------------------*/
615 /* link an ed into one of the HC chains */
617 static int ep_link (ohci_t *ohci, ed_t *edi)
619 volatile ed_t *ed = edi;
628 ed->int_interval = 0;
633 if (ohci->ed_controltail == NULL) {
634 writel (ed, &ohci->regs->ed_controlhead);
636 ohci->ed_controltail->hwNextED = m32_swap ((unsigned long)ed);
638 ed->ed_prev = ohci->ed_controltail;
639 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
640 !ohci->ed_rm_list[1] && !ohci->sleeping) {
641 ohci->hc_control |= OHCI_CTRL_CLE;
642 writel (ohci->hc_control, &ohci->regs->control);
644 ohci->ed_controltail = edi;
649 if (ohci->ed_bulktail == NULL) {
650 writel (ed, &ohci->regs->ed_bulkhead);
652 ohci->ed_bulktail->hwNextED = m32_swap ((unsigned long)ed);
654 ed->ed_prev = ohci->ed_bulktail;
655 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
656 !ohci->ed_rm_list[1] && !ohci->sleeping) {
657 ohci->hc_control |= OHCI_CTRL_BLE;
658 writel (ohci->hc_control, &ohci->regs->control);
660 ohci->ed_bulktail = edi;
665 interval = ep_2_n_interval (ed->int_period);
666 ed->int_interval = interval;
667 int_branch = ep_int_ballance (ohci, interval, load);
668 ed->int_branch = int_branch;
670 for (i = 0; i < ep_rev (6, interval); i += inter) {
672 for (ed_p = &(ohci->hcca->int_table[ep_rev (5, i) + int_branch]);
673 (*ed_p != 0) && (((ed_t *)ed_p)->int_interval >= interval);
674 ed_p = &(((ed_t *)ed_p)->hwNextED))
675 inter = ep_rev (6, ((ed_t *)ed_p)->int_interval);
676 ed->hwNextED = *ed_p;
677 *ed_p = m32_swap((unsigned long)ed);
684 /*-------------------------------------------------------------------------*/
686 /* scan the periodic table to find and unlink this ED */
687 static void periodic_unlink ( struct ohci *ohci, volatile struct ed *ed,
688 unsigned index, unsigned period)
690 for (; index < NUM_INTS; index += period) {
691 __u32 *ed_p = &ohci->hcca->int_table [index];
693 /* ED might have been unlinked through another path */
695 if (((struct ed *)m32_swap ((unsigned long)ed_p)) == ed) {
696 *ed_p = ed->hwNextED;
699 ed_p = & (((struct ed *)m32_swap ((unsigned long)ed_p))->hwNextED);
704 /* unlink an ed from one of the HC chains.
705 * just the link to the ed is unlinked.
706 * the link from the ed still points to another operational ed or 0
707 * so the HC can eventually finish the processing of the unlinked ed */
709 static int ep_unlink (ohci_t *ohci, ed_t *edi)
711 volatile ed_t *ed = edi;
714 ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
718 if (ed->ed_prev == NULL) {
720 ohci->hc_control &= ~OHCI_CTRL_CLE;
721 writel (ohci->hc_control, &ohci->regs->control);
723 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
725 ed->ed_prev->hwNextED = ed->hwNextED;
727 if (ohci->ed_controltail == ed) {
728 ohci->ed_controltail = ed->ed_prev;
730 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
735 if (ed->ed_prev == NULL) {
737 ohci->hc_control &= ~OHCI_CTRL_BLE;
738 writel (ohci->hc_control, &ohci->regs->control);
740 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
742 ed->ed_prev->hwNextED = ed->hwNextED;
744 if (ohci->ed_bulktail == ed) {
745 ohci->ed_bulktail = ed->ed_prev;
747 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
752 periodic_unlink (ohci, ed, 0, 1);
753 for (i = ed->int_branch; i < 32; i += ed->int_interval)
754 ohci->ohci_int_load[i] -= ed->int_load;
757 ed->state = ED_UNLINK;
761 /*-------------------------------------------------------------------------*/
763 /* add/reinit an endpoint; this should be done once at the
764 * usb_set_configuration command, but the USB stack is a little bit
765 * stateless so we do it at every transaction if the state of the ed
766 * is ED_NEW then a dummy td is added and the state is changed to
767 * ED_UNLINK in all other cases the state is left unchanged the ed
768 * info fields are setted anyway even though most of them should not
771 static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe,
772 int interval, int load)
778 ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
779 (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
781 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
782 err("ep_add_ed: pending delete");
783 /* pending delete request */
787 if (ed->state == ED_NEW) {
788 ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
789 /* dummy td; end of td list for ed */
790 td = td_alloc (usb_dev);
791 ed->hwTailP = m32_swap ((unsigned long)td);
792 ed->hwHeadP = ed->hwTailP;
793 ed->state = ED_UNLINK;
794 ed->type = usb_pipetype (pipe);
798 ed->hwINFO = m32_swap (usb_pipedevice (pipe)
799 | usb_pipeendpoint (pipe) << 7
800 | (usb_pipeisoc (pipe)? 0x8000: 0)
801 | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
802 | usb_pipeslow (pipe) << 13
803 | usb_maxpacket (usb_dev, pipe) << 16);
805 if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) {
806 ed->int_period = interval;
813 /*-------------------------------------------------------------------------*
814 * TD handling functions
815 *-------------------------------------------------------------------------*/
817 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
819 static void td_fill (ohci_t *ohci, unsigned int info,
821 struct usb_device *dev, int index, urb_priv_t *urb_priv)
823 volatile td_t *td, *td_pt;
824 #ifdef OHCI_FILL_TRACE
828 if (index > urb_priv->length) {
829 err("index > length");
832 /* use this td as the next dummy */
833 td_pt = urb_priv->td [index];
836 /* fill the old dummy TD */
837 td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
839 td->ed = urb_priv->ed;
840 td->next_dl_td = NULL;
842 td->data = (__u32)data;
843 #ifdef OHCI_FILL_TRACE
844 if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
845 for (i = 0; i < len; i++)
846 printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
853 td->hwINFO = m32_swap (info);
854 td->hwCBP = m32_swap ((unsigned long)data);
856 td->hwBE = m32_swap ((unsigned long)(data + len - 1));
859 td->hwNextTD = m32_swap ((unsigned long)td_pt);
861 /* append to queue */
862 td->ed->hwTailP = td->hwNextTD;
865 /*-------------------------------------------------------------------------*/
867 /* prepare all TDs of a transfer */
869 static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
870 int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
872 ohci_t *ohci = &gohci;
873 int data_len = transfer_len;
877 unsigned int toggle = 0;
879 /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
880 if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
881 toggle = TD_T_TOGGLE;
884 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
892 switch (usb_pipetype (pipe)) {
894 info = usb_pipeout (pipe)?
895 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
896 while(data_len > 4096) {
897 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
898 data += 4096; data_len -= 4096; cnt++;
900 info = usb_pipeout (pipe)?
901 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
902 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
906 writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
910 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
911 td_fill (ohci, info, setup, 8, dev, cnt++, urb);
913 info = usb_pipeout (pipe)?
914 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
915 /* NOTE: mishandles transfers >8K, some >4K */
916 td_fill (ohci, info, data, data_len, dev, cnt++, urb);
918 info = usb_pipeout (pipe)?
919 TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
920 td_fill (ohci, info, data, 0, dev, cnt++, urb);
922 writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
926 info = usb_pipeout (urb->pipe)?
927 TD_CC | TD_DP_OUT | toggle:
928 TD_CC | TD_R | TD_DP_IN | toggle;
929 td_fill (ohci, info, data, data_len, dev, cnt++, urb);
932 if (urb->length != cnt)
933 dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
936 /*-------------------------------------------------------------------------*
937 * Done List handling functions
938 *-------------------------------------------------------------------------*/
940 /* calculate the transfer length and update the urb */
942 static void dl_transfer_length(td_t * td)
944 __u32 tdINFO, tdBE, tdCBP;
945 urb_priv_t *lurb_priv = td->ed->purb;
947 tdINFO = m32_swap (td->hwINFO);
948 tdBE = m32_swap (td->hwBE);
949 tdCBP = m32_swap (td->hwCBP);
951 if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
952 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
955 lurb_priv->actual_length += tdBE - td->data + 1;
957 lurb_priv->actual_length += tdCBP - td->data;
962 /*-------------------------------------------------------------------------*/
964 /* replies to the request have to be on a FIFO basis so
965 * we reverse the reversed done-list */
967 static td_t * dl_reverse_done_list (ohci_t *ohci)
971 td_t *td_list = NULL;
972 urb_priv_t *lurb_priv = NULL;
974 td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
975 ohci->hcca->done_head = 0;
978 td_list = (td_t *)td_list_hc;
980 if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
981 lurb_priv = td_list->ed->purb;
982 dbg(" USB-error/status: %x : %p",
983 TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
984 if (td_list->ed->hwHeadP & m32_swap (0x1)) {
985 if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
986 td_list->ed->hwHeadP =
987 (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
988 (td_list->ed->hwHeadP & m32_swap (0x2));
989 lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
991 td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
993 #ifdef CONFIG_MPC5200
994 td_list->hwNextTD = 0;
998 td_list->next_dl_td = td_rev;
1000 td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
1005 /*-------------------------------------------------------------------------*/
1008 static int dl_done_list (ohci_t *ohci, td_t *td_list)
1010 td_t *td_list_next = NULL;
1015 urb_priv_t *lurb_priv;
1016 __u32 tdINFO, edHeadP, edTailP;
1019 td_list_next = td_list->next_dl_td;
1021 tdINFO = m32_swap (td_list->hwINFO);
1024 lurb_priv = ed->purb;
1026 dl_transfer_length(td_list);
1028 /* error code of transfer */
1029 cc = TD_CC_GET (tdINFO);
1031 dbg("ConditionCode %#x", cc);
1032 stat = cc_to_error[cc];
1035 /* see if this done list makes for all TD's of current URB,
1036 * and mark the URB finished if so */
1037 if (++(lurb_priv->td_cnt) == lurb_priv->length) {
1039 if ((ed->state & (ED_OPER | ED_UNLINK)) &&
1040 (lurb_priv->state != URB_DEL))
1042 if ((ed->state & (ED_OPER | ED_UNLINK)))
1044 lurb_priv->finished = sohci_return_job(ohci,
1047 dbg("dl_done_list: strange.., ED state %x, ed->state\n");
1049 dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt,
1051 if (ed->state != ED_NEW &&
1052 (usb_pipetype (lurb_priv->pipe) != PIPE_INTERRUPT)) {
1053 edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
1054 edTailP = m32_swap (ed->hwTailP);
1056 /* unlink eds if they are not busy */
1057 if ((edHeadP == edTailP) && (ed->state == ED_OPER))
1058 ep_unlink (ohci, ed);
1061 td_list = td_list_next;
1066 /*-------------------------------------------------------------------------*
1068 *-------------------------------------------------------------------------*/
1070 /* Device descriptor */
1071 static __u8 root_hub_dev_des[] =
1073 0x12, /* __u8 bLength; */
1074 0x01, /* __u8 bDescriptorType; Device */
1075 0x10, /* __u16 bcdUSB; v1.1 */
1077 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
1078 0x00, /* __u8 bDeviceSubClass; */
1079 0x00, /* __u8 bDeviceProtocol; */
1080 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
1081 0x00, /* __u16 idVendor; */
1083 0x00, /* __u16 idProduct; */
1085 0x00, /* __u16 bcdDevice; */
1087 0x00, /* __u8 iManufacturer; */
1088 0x01, /* __u8 iProduct; */
1089 0x00, /* __u8 iSerialNumber; */
1090 0x01 /* __u8 bNumConfigurations; */
1093 /* Configuration descriptor */
1094 static __u8 root_hub_config_des[] =
1096 0x09, /* __u8 bLength; */
1097 0x02, /* __u8 bDescriptorType; Configuration */
1098 0x19, /* __u16 wTotalLength; */
1100 0x01, /* __u8 bNumInterfaces; */
1101 0x01, /* __u8 bConfigurationValue; */
1102 0x00, /* __u8 iConfiguration; */
1103 0x40, /* __u8 bmAttributes;
1104 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
1105 0x00, /* __u8 MaxPower; */
1108 0x09, /* __u8 if_bLength; */
1109 0x04, /* __u8 if_bDescriptorType; Interface */
1110 0x00, /* __u8 if_bInterfaceNumber; */
1111 0x00, /* __u8 if_bAlternateSetting; */
1112 0x01, /* __u8 if_bNumEndpoints; */
1113 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
1114 0x00, /* __u8 if_bInterfaceSubClass; */
1115 0x00, /* __u8 if_bInterfaceProtocol; */
1116 0x00, /* __u8 if_iInterface; */
1119 0x07, /* __u8 ep_bLength; */
1120 0x05, /* __u8 ep_bDescriptorType; Endpoint */
1121 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
1122 0x03, /* __u8 ep_bmAttributes; Interrupt */
1123 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
1125 0xff /* __u8 ep_bInterval; 255 ms */
1128 static unsigned char root_hub_str_index0[] =
1130 0x04, /* __u8 bLength; */
1131 0x03, /* __u8 bDescriptorType; String-descriptor */
1132 0x09, /* __u8 lang ID */
1133 0x04, /* __u8 lang ID */
1136 static unsigned char root_hub_str_index1[] =
1138 28, /* __u8 bLength; */
1139 0x03, /* __u8 bDescriptorType; String-descriptor */
1140 'O', /* __u8 Unicode */
1141 0, /* __u8 Unicode */
1142 'H', /* __u8 Unicode */
1143 0, /* __u8 Unicode */
1144 'C', /* __u8 Unicode */
1145 0, /* __u8 Unicode */
1146 'I', /* __u8 Unicode */
1147 0, /* __u8 Unicode */
1148 ' ', /* __u8 Unicode */
1149 0, /* __u8 Unicode */
1150 'R', /* __u8 Unicode */
1151 0, /* __u8 Unicode */
1152 'o', /* __u8 Unicode */
1153 0, /* __u8 Unicode */
1154 'o', /* __u8 Unicode */
1155 0, /* __u8 Unicode */
1156 't', /* __u8 Unicode */
1157 0, /* __u8 Unicode */
1158 ' ', /* __u8 Unicode */
1159 0, /* __u8 Unicode */
1160 'H', /* __u8 Unicode */
1161 0, /* __u8 Unicode */
1162 'u', /* __u8 Unicode */
1163 0, /* __u8 Unicode */
1164 'b', /* __u8 Unicode */
1165 0, /* __u8 Unicode */
1168 /* Hub class-specific descriptor is constructed dynamically */
1170 /*-------------------------------------------------------------------------*/
1172 #define OK(x) len = (x); break
1174 #define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
1175 #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
1177 #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
1178 #define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
1180 #define RD_RH_STAT roothub_status(&gohci)
1181 #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
1183 /* request to virtual root hub */
1185 int rh_check_port_status(ohci_t *controller)
1191 temp = roothub_a (controller);
1192 ndp = (temp & RH_A_NDP);
1193 #ifdef CONFIG_AT91C_PQFP_UHPBUG
1194 ndp = (ndp == 2) ? 1:0;
1196 for (i = 0; i < ndp; i++) {
1197 temp = roothub_portstatus (controller, i);
1198 /* check for a device disconnect */
1199 if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
1200 (RH_PS_PESC | RH_PS_CSC)) &&
1201 ((temp & RH_PS_CCS) == 0)) {
1209 static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
1210 void *buffer, int transfer_len, struct devrequest *cmd)
1212 void * data = buffer;
1213 int leni = transfer_len;
1217 __u8 *data_buf = (__u8 *)datab;
1224 pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
1228 if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
1229 info("Root-Hub submit IRQ: NOT implemented");
1233 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
1234 wValue = cpu_to_le16 (cmd->value);
1235 wIndex = cpu_to_le16 (cmd->index);
1236 wLength = cpu_to_le16 (cmd->length);
1238 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
1239 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
1241 switch (bmRType_bReq) {
1242 /* Request Destination:
1243 without flags: Device,
1244 RH_INTERFACE: interface,
1245 RH_ENDPOINT: endpoint,
1246 RH_CLASS means HUB here,
1247 RH_OTHER | RH_CLASS almost ever means HUB_PORT here
1251 *(__u16 *) data_buf = cpu_to_le16 (1); OK (2);
1252 case RH_GET_STATUS | RH_INTERFACE:
1253 *(__u16 *) data_buf = cpu_to_le16 (0); OK (2);
1254 case RH_GET_STATUS | RH_ENDPOINT:
1255 *(__u16 *) data_buf = cpu_to_le16 (0); OK (2);
1256 case RH_GET_STATUS | RH_CLASS:
1257 *(__u32 *) data_buf = cpu_to_le32 (
1258 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
1260 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
1261 *(__u32 *) data_buf = cpu_to_le32 (RD_RH_PORTSTAT); OK (4);
1263 case RH_CLEAR_FEATURE | RH_ENDPOINT:
1265 case (RH_ENDPOINT_STALL): OK (0);
1269 case RH_CLEAR_FEATURE | RH_CLASS:
1271 case RH_C_HUB_LOCAL_POWER:
1273 case (RH_C_HUB_OVER_CURRENT):
1274 WR_RH_STAT(RH_HS_OCIC); OK (0);
1278 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
1280 case (RH_PORT_ENABLE):
1281 WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
1282 case (RH_PORT_SUSPEND):
1283 WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
1284 case (RH_PORT_POWER):
1285 WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
1286 case (RH_C_PORT_CONNECTION):
1287 WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
1288 case (RH_C_PORT_ENABLE):
1289 WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
1290 case (RH_C_PORT_SUSPEND):
1291 WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
1292 case (RH_C_PORT_OVER_CURRENT):
1293 WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
1294 case (RH_C_PORT_RESET):
1295 WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
1299 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
1301 case (RH_PORT_SUSPEND):
1302 WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
1303 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
1304 if (RD_RH_PORTSTAT & RH_PS_CCS)
1305 WR_RH_PORTSTAT (RH_PS_PRS);
1307 case (RH_PORT_POWER):
1308 WR_RH_PORTSTAT (RH_PS_PPS );
1311 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
1312 if (RD_RH_PORTSTAT & RH_PS_CCS)
1313 WR_RH_PORTSTAT (RH_PS_PES );
1318 case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
1320 case RH_GET_DESCRIPTOR:
1321 switch ((wValue & 0xff00) >> 8) {
1322 case (0x01): /* device descriptor */
1323 len = min_t(unsigned int,
1326 sizeof (root_hub_dev_des),
1328 data_buf = root_hub_dev_des; OK(len);
1329 case (0x02): /* configuration descriptor */
1330 len = min_t(unsigned int,
1333 sizeof (root_hub_config_des),
1335 data_buf = root_hub_config_des; OK(len);
1336 case (0x03): /* string descriptors */
1337 if(wValue==0x0300) {
1338 len = min_t(unsigned int,
1341 sizeof (root_hub_str_index0),
1343 data_buf = root_hub_str_index0;
1346 if(wValue==0x0301) {
1347 len = min_t(unsigned int,
1350 sizeof (root_hub_str_index1),
1352 data_buf = root_hub_str_index1;
1356 stat = USB_ST_STALLED;
1360 case RH_GET_DESCRIPTOR | RH_CLASS:
1362 __u32 temp = roothub_a (&gohci);
1364 data_buf [0] = 9; /* min length; */
1365 data_buf [1] = 0x29;
1366 data_buf [2] = temp & RH_A_NDP;
1367 #ifdef CONFIG_AT91C_PQFP_UHPBUG
1368 data_buf [2] = (data_buf [2] == 2) ? 1:0;
1371 if (temp & RH_A_PSM) /* per-port power switching? */
1372 data_buf [3] |= 0x1;
1373 if (temp & RH_A_NOCP) /* no overcurrent reporting? */
1374 data_buf [3] |= 0x10;
1375 else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
1376 data_buf [3] |= 0x8;
1378 /* corresponds to data_buf[4-7] */
1380 data_buf [5] = (temp & RH_A_POTPGT) >> 24;
1381 temp = roothub_b (&gohci);
1382 data_buf [7] = temp & RH_B_DR;
1383 if (data_buf [2] < 7) {
1384 data_buf [8] = 0xff;
1387 data_buf [8] = (temp & RH_B_DR) >> 8;
1388 data_buf [10] = data_buf [9] = 0xff;
1391 len = min_t(unsigned int, leni,
1392 min_t(unsigned int, data_buf [0], wLength));
1396 case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
1398 case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
1401 dbg ("unsupported root hub command");
1402 stat = USB_ST_STALLED;
1406 ohci_dump_roothub (&gohci, 1);
1411 len = min_t(int, len, leni);
1412 if (data != data_buf)
1413 memcpy (data, data_buf, len);
1418 pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
1426 /*-------------------------------------------------------------------------*/
1428 /* common code for handling submit messages - used for all but root hub */
1430 int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1431 int transfer_len, struct devrequest *setup, int interval)
1434 int maxsize = usb_maxpacket(dev, pipe);
1438 urb = malloc(sizeof(urb_priv_t));
1439 memset(urb, 0, sizeof(urb_priv_t));
1443 urb->transfer_buffer = buffer;
1444 urb->transfer_buffer_length = transfer_len;
1445 urb->interval = interval;
1447 /* device pulled? Shortcut the action. */
1448 if (devgone == dev) {
1449 dev->status = USB_ST_CRC_ERR;
1454 urb->actual_length = 0;
1455 pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1460 err("submit_common_message: pipesize for pipe %lx is zero",
1465 if (sohci_submit_job(urb, setup) < 0) {
1466 err("sohci_submit_job failed");
1472 /* ohci_dump_status(&gohci); */
1475 /* allow more time for a BULK device to react - some are slow */
1476 #define BULK_TO 5000 /* timeout in milliseconds */
1477 if (usb_pipetype (pipe) == PIPE_BULK)
1482 /* wait for it to complete */
1484 /* check whether the controller is done */
1485 stat = hc_interrupt();
1487 stat = USB_ST_CRC_ERR;
1491 /* NOTE: since we are not interrupt driven in U-Boot and always
1492 * handle only one URB at a time, we cannot assume the
1493 * transaction finished on the first successful return from
1494 * hc_interrupt().. unless the flag for current URB is set,
1495 * meaning that all TD's to/from device got actually
1496 * transferred and processed. If the current URB is not
1497 * finished we need to re-iterate this loop so as
1498 * hc_interrupt() gets called again as there needs to be some
1499 * more TD's to process still */
1500 if ((stat >= 0) && (stat != 0xff) && (urb->finished)) {
1501 /* 0xff is returned for an SF-interrupt */
1511 err("CTL:TIMEOUT ");
1512 dbg("submit_common_msg: TO status %x\n", stat);
1514 stat = USB_ST_CRC_ERR;
1520 dev->act_len = transfer_len;
1523 pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
1528 /* free TDs in urb_priv */
1529 if (usb_pipetype (pipe) != PIPE_INTERRUPT)
1530 urb_free_priv (urb);
1534 /* submit routines called from usb.c */
1535 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1538 info("submit_bulk_msg");
1539 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
1542 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1543 int transfer_len, struct devrequest *setup)
1545 int maxsize = usb_maxpacket(dev, pipe);
1547 info("submit_control_msg");
1549 pkt_print(NULL, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1554 err("submit_control_message: pipesize for pipe %lx is zero",
1558 if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
1560 /* root hub - redirect */
1561 return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
1565 return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
1568 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1569 int transfer_len, int interval)
1571 info("submit_int_msg");
1572 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL,
1576 /*-------------------------------------------------------------------------*
1578 *-------------------------------------------------------------------------*/
1580 /* reset the HC and BUS */
1582 static int hc_reset (ohci_t *ohci)
1585 int smm_timeout = 50; /* 0,5 sec */
1587 dbg("%s\n", __FUNCTION__);
1589 if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
1590 writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
1591 info("USB HC TakeOver from SMM");
1592 while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
1594 if (--smm_timeout == 0) {
1595 err("USB HC TakeOver failed!");
1601 /* Disable HC interrupts */
1602 writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
1604 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
1606 readl(&ohci->regs->control));
1608 /* Reset USB (needed by some controllers) */
1609 ohci->hc_control = 0;
1610 writel (ohci->hc_control, &ohci->regs->control);
1612 /* HC Reset requires max 10 us delay */
1613 writel (OHCI_HCR, &ohci->regs->cmdstatus);
1614 while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1615 if (--timeout == 0) {
1616 err("USB HC reset timed out!");
1624 /*-------------------------------------------------------------------------*/
1626 /* Start an OHCI controller, set the BUS operational
1628 * connect the virtual root hub */
1630 static int hc_start (ohci_t * ohci)
1633 unsigned int fminterval;
1637 /* Tell the controller where the control and bulk lists are
1638 * The lists are empty now. */
1640 writel (0, &ohci->regs->ed_controlhead);
1641 writel (0, &ohci->regs->ed_bulkhead);
1643 writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
1645 fminterval = 0x2edf;
1646 writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
1647 fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
1648 writel (fminterval, &ohci->regs->fminterval);
1649 writel (0x628, &ohci->regs->lsthresh);
1651 /* start controller operations */
1652 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
1654 writel (ohci->hc_control, &ohci->regs->control);
1656 /* disable all interrupts */
1657 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
1658 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
1659 OHCI_INTR_OC | OHCI_INTR_MIE);
1660 writel (mask, &ohci->regs->intrdisable);
1661 /* clear all interrupts */
1662 mask &= ~OHCI_INTR_MIE;
1663 writel (mask, &ohci->regs->intrstatus);
1664 /* Choose the interrupts we care about now - but w/o MIE */
1665 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
1666 writel (mask, &ohci->regs->intrenable);
1669 /* required for AMD-756 and some Mac platforms */
1670 writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
1671 &ohci->regs->roothub.a);
1672 writel (RH_HS_LPSC, &ohci->regs->roothub.status);
1673 #endif /* OHCI_USE_NPS */
1675 #define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
1676 /* POTPGT delay is bits 24-31, in 2 ms units. */
1677 mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
1679 /* connect the virtual root hub */
1680 ohci->rh.devnum = 0;
1685 /*-------------------------------------------------------------------------*/
1687 /* Poll USB interrupt. */
1688 void usb_event_poll(void)
1693 /* an interrupt happens */
1695 static int hc_interrupt (void)
1697 ohci_t *ohci = &gohci;
1698 struct ohci_regs *regs = ohci->regs;
1702 if ((ohci->hcca->done_head != 0) &&
1703 !(m32_swap (ohci->hcca->done_head) & 0x01)) {
1704 ints = OHCI_INTR_WDH;
1705 } else if ((ints = readl (®s->intrstatus)) == ~(u32)0) {
1707 err ("%s device removed!", ohci->slot_name);
1709 } else if ((ints &= readl (®s->intrenable)) == 0) {
1710 dbg("hc_interrupt: returning..\n");
1714 /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
1716 if (ints & OHCI_INTR_RHSC) {
1721 if (ints & OHCI_INTR_UE) {
1723 err ("OHCI Unrecoverable Error, controller usb-%s disabled",
1725 /* e.g. due to PCI Master/Target Abort */
1728 ohci_dump (ohci, 1);
1732 /* FIXME: be optimistic, hope that bug won't repeat often. */
1733 /* Make some non-interrupt context restart the controller. */
1734 /* Count and limit the retries though; either hardware or */
1735 /* software errors can go forever... */
1740 if (ints & OHCI_INTR_WDH) {
1742 writel (OHCI_INTR_WDH, ®s->intrdisable);
1743 (void)readl (®s->intrdisable); /* flush */
1744 stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
1745 writel (OHCI_INTR_WDH, ®s->intrenable);
1746 (void)readl (®s->intrdisable); /* flush */
1749 if (ints & OHCI_INTR_SO) {
1750 dbg("USB Schedule overrun\n");
1751 writel (OHCI_INTR_SO, ®s->intrenable);
1755 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
1756 if (ints & OHCI_INTR_SF) {
1757 unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
1759 writel (OHCI_INTR_SF, ®s->intrdisable);
1760 if (ohci->ed_rm_list[frame] != NULL)
1761 writel (OHCI_INTR_SF, ®s->intrenable);
1765 writel (ints, ®s->intrstatus);
1769 /*-------------------------------------------------------------------------*/
1771 /*-------------------------------------------------------------------------*/
1773 /* De-allocate all resources.. */
1775 static void hc_release_ohci (ohci_t *ohci)
1777 dbg ("USB HC release ohci usb-%s", ohci->slot_name);
1779 if (!ohci->disabled)
1783 /*-------------------------------------------------------------------------*/
1786 * low level initalisation routine, called from usb.c
1788 static char ohci_inited = 0;
1790 int usb_lowlevel_init(void)
1792 #ifdef CONFIG_PCI_OHCI
1796 #ifdef CFG_USB_OHCI_CPU_INIT
1797 /* cpu dependant init */
1802 #ifdef CFG_USB_OHCI_BOARD_INIT
1803 /* board dependant init */
1804 if(usb_board_init())
1807 memset (&gohci, 0, sizeof (ohci_t));
1809 /* align the storage */
1810 if ((__u32)&ghcca[0] & 0xff) {
1811 err("HCCA not aligned!!");
1815 info("aligned ghcca %p", phcca);
1816 memset(&ohci_dev, 0, sizeof(struct ohci_device));
1817 if ((__u32)&ohci_dev.ed[0] & 0x7) {
1818 err("EDs not aligned!!");
1821 memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
1822 if ((__u32)gtd & 0x7) {
1823 err("TDs not aligned!!");
1828 memset (phcca, 0, sizeof (struct ohci_hcca));
1833 #ifdef CONFIG_PCI_OHCI
1834 pdev = pci_find_devices(ohci_pci_ids, 0);
1839 pci_read_config_word(pdev, PCI_VENDOR_ID, &vid);
1840 pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
1841 printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n",
1842 vid, did, (pdev >> 16) & 0xff,
1843 (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);
1844 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
1845 printf("OHCI regs address 0x%08x\n", base);
1846 gohci.regs = (struct ohci_regs *)base;
1850 gohci.regs = (struct ohci_regs *)CFG_USB_OHCI_REGS_BASE;
1854 gohci.slot_name = CFG_USB_OHCI_SLOT_NAME;
1856 if (hc_reset (&gohci) < 0) {
1857 hc_release_ohci (&gohci);
1858 err ("can't reset usb-%s", gohci.slot_name);
1859 #ifdef CFG_USB_OHCI_BOARD_INIT
1860 /* board dependant cleanup */
1861 usb_board_init_fail();
1864 #ifdef CFG_USB_OHCI_CPU_INIT
1865 /* cpu dependant cleanup */
1866 usb_cpu_init_fail();
1871 /* FIXME this is a second HC reset; why?? */
1872 /* writel(gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
1874 if (hc_start (&gohci) < 0) {
1875 err ("can't start usb-%s", gohci.slot_name);
1876 hc_release_ohci (&gohci);
1877 /* Initialization failed */
1878 #ifdef CFG_USB_OHCI_BOARD_INIT
1879 /* board dependant cleanup */
1883 #ifdef CFG_USB_OHCI_CPU_INIT
1884 /* cpu dependant cleanup */
1891 ohci_dump (&gohci, 1);
1899 int usb_lowlevel_stop(void)
1901 /* this gets called really early - before the controller has */
1902 /* even been initialized! */
1905 /* TODO release any interrupts, etc. */
1906 /* call hc_release_ohci() here ? */
1909 #ifdef CFG_USB_OHCI_BOARD_INIT
1910 /* board dependant cleanup */
1911 if(usb_board_stop())
1915 #ifdef CFG_USB_OHCI_CPU_INIT
1916 /* cpu dependant cleanup */
1923 #endif /* CONFIG_USB_OHCI_NEW */