2 * Allwinner SUNXI "glue layer"
4 * Copyright © 2015 Hans de Goede <hdegoede@redhat.com>
5 * Copyright © 2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
7 * Based on the sw_usb "Allwinner OTG Dual Role Controller" code.
8 * Copyright 2007-2012 (C) Allwinner Technology Co., Ltd.
9 * javen <javen@allwinnertech.com>
11 * Based on the DA8xx "glue layer" code.
12 * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
13 * Copyright (C) 2005-2006 by Texas Instruments
15 * This file is part of the Inventra Controller Driver for Linux.
17 * The Inventra Controller Driver for Linux is free software; you
18 * can redistribute it and/or modify it under the terms of the GNU
19 * General Public License version 2 as published by the Free Software
24 #include <asm/arch/cpu.h>
25 #include <asm/arch/clock.h>
26 #include <asm/arch/gpio.h>
27 #include <asm/arch/usb_phy.h>
28 #include <asm-generic/gpio.h>
29 #include <linux/usb/musb.h>
30 #include "linux-compat.h"
31 #include "musb_core.h"
33 /******************************************************************************
34 ******************************************************************************
35 * From the Allwinner driver
36 ******************************************************************************
37 ******************************************************************************/
39 /******************************************************************************
40 * From include/sunxi_usb_bsp.h
41 ******************************************************************************/
44 #define USBC_REG_o_ISCR 0x0400
45 #define USBC_REG_o_PHYCTL 0x0404
46 #define USBC_REG_o_PHYBIST 0x0408
47 #define USBC_REG_o_PHYTUNE 0x040c
49 #define USBC_REG_o_VEND0 0x0043
51 /* Interface Status and Control */
52 #define USBC_BP_ISCR_VBUS_VALID_FROM_DATA 30
53 #define USBC_BP_ISCR_VBUS_VALID_FROM_VBUS 29
54 #define USBC_BP_ISCR_EXT_ID_STATUS 28
55 #define USBC_BP_ISCR_EXT_DM_STATUS 27
56 #define USBC_BP_ISCR_EXT_DP_STATUS 26
57 #define USBC_BP_ISCR_MERGED_VBUS_STATUS 25
58 #define USBC_BP_ISCR_MERGED_ID_STATUS 24
60 #define USBC_BP_ISCR_ID_PULLUP_EN 17
61 #define USBC_BP_ISCR_DPDM_PULLUP_EN 16
62 #define USBC_BP_ISCR_FORCE_ID 14
63 #define USBC_BP_ISCR_FORCE_VBUS_VALID 12
64 #define USBC_BP_ISCR_VBUS_VALID_SRC 10
66 #define USBC_BP_ISCR_HOSC_EN 7
67 #define USBC_BP_ISCR_VBUS_CHANGE_DETECT 6
68 #define USBC_BP_ISCR_ID_CHANGE_DETECT 5
69 #define USBC_BP_ISCR_DPDM_CHANGE_DETECT 4
70 #define USBC_BP_ISCR_IRQ_ENABLE 3
71 #define USBC_BP_ISCR_VBUS_CHANGE_DETECT_EN 2
72 #define USBC_BP_ISCR_ID_CHANGE_DETECT_EN 1
73 #define USBC_BP_ISCR_DPDM_CHANGE_DETECT_EN 0
75 /******************************************************************************
77 ******************************************************************************/
79 static u32 USBC_WakeUp_ClearChangeDetect(u32 reg_val)
83 temp &= ~(1 << USBC_BP_ISCR_VBUS_CHANGE_DETECT);
84 temp &= ~(1 << USBC_BP_ISCR_ID_CHANGE_DETECT);
85 temp &= ~(1 << USBC_BP_ISCR_DPDM_CHANGE_DETECT);
90 static void USBC_EnableIdPullUp(__iomem void *base)
94 reg_val = musb_readl(base, USBC_REG_o_ISCR);
95 reg_val |= (1 << USBC_BP_ISCR_ID_PULLUP_EN);
96 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
97 musb_writel(base, USBC_REG_o_ISCR, reg_val);
100 static void USBC_EnableDpDmPullUp(__iomem void *base)
104 reg_val = musb_readl(base, USBC_REG_o_ISCR);
105 reg_val |= (1 << USBC_BP_ISCR_DPDM_PULLUP_EN);
106 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
107 musb_writel(base, USBC_REG_o_ISCR, reg_val);
110 static void USBC_ForceIdToLow(__iomem void *base)
114 reg_val = musb_readl(base, USBC_REG_o_ISCR);
115 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
116 reg_val |= (0x02 << USBC_BP_ISCR_FORCE_ID);
117 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
118 musb_writel(base, USBC_REG_o_ISCR, reg_val);
121 static void USBC_ForceIdToHigh(__iomem void *base)
125 reg_val = musb_readl(base, USBC_REG_o_ISCR);
126 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
127 reg_val |= (0x03 << USBC_BP_ISCR_FORCE_ID);
128 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
129 musb_writel(base, USBC_REG_o_ISCR, reg_val);
132 static void USBC_ForceVbusValidToLow(__iomem void *base)
136 reg_val = musb_readl(base, USBC_REG_o_ISCR);
137 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
138 reg_val |= (0x02 << USBC_BP_ISCR_FORCE_VBUS_VALID);
139 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
140 musb_writel(base, USBC_REG_o_ISCR, reg_val);
143 static void USBC_ForceVbusValidToHigh(__iomem void *base)
147 reg_val = musb_readl(base, USBC_REG_o_ISCR);
148 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
149 reg_val |= (0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
150 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
151 musb_writel(base, USBC_REG_o_ISCR, reg_val);
154 static void USBC_ConfigFIFO_Base(void)
158 /* config usb fifo, 8kb mode */
159 reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
160 reg_value &= ~(0x03 << 0);
161 reg_value |= (1 << 0);
162 writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
165 /******************************************************************************
167 ******************************************************************************/
169 static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
171 struct musb *musb = __hci;
172 irqreturn_t retval = IRQ_NONE;
174 /* read and flush interrupts */
175 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
177 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
178 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
180 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
181 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
183 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
185 if (musb->int_usb || musb->int_tx || musb->int_rx)
186 retval |= musb_interrupt(musb);
191 /* musb_core does not call enable / disable in a balanced manner <sigh> */
192 static bool enabled = false;
194 static int sunxi_musb_enable(struct musb *musb)
198 pr_debug("%s():\n", __func__);
203 /* select PIO mode */
204 musb_writeb(musb->mregs, USBC_REG_o_VEND0, 0);
206 if (is_host_enabled(musb)) {
207 ret = sunxi_usb_phy_vbus_detect(0);
209 printf("A charger is plugged into the OTG: ");
212 ret = sunxi_usb_phy_id_detect(0);
214 printf("No host cable detected: ");
217 sunxi_usb_phy_power_on(0); /* port power on */
220 USBC_ForceVbusValidToHigh(musb->mregs);
226 static void sunxi_musb_disable(struct musb *musb)
228 pr_debug("%s():\n", __func__);
233 if (is_host_enabled(musb))
234 sunxi_usb_phy_power_off(0); /* port power off */
236 USBC_ForceVbusValidToLow(musb->mregs);
237 mdelay(200); /* Wait for the current session to timeout */
242 static int sunxi_musb_init(struct musb *musb)
244 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
246 pr_debug("%s():\n", __func__);
248 musb->isr = sunxi_musb_interrupt;
250 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0);
251 #ifdef CONFIG_SUNXI_GEN_SUN6I
252 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0);
254 sunxi_usb_phy_init(0);
256 USBC_ConfigFIFO_Base();
257 USBC_EnableDpDmPullUp(musb->mregs);
258 USBC_EnableIdPullUp(musb->mregs);
260 if (is_host_enabled(musb)) {
262 USBC_ForceIdToLow(musb->mregs);
264 /* Peripheral mode */
265 USBC_ForceIdToHigh(musb->mregs);
267 USBC_ForceVbusValidToHigh(musb->mregs);
272 static const struct musb_platform_ops sunxi_musb_ops = {
273 .init = sunxi_musb_init,
274 .enable = sunxi_musb_enable,
275 .disable = sunxi_musb_disable,
278 static struct musb_hdrc_config musb_config = {
285 static struct musb_hdrc_platform_data musb_plat = {
286 #if defined(CONFIG_MUSB_HOST)
289 .mode = MUSB_PERIPHERAL,
291 .config = &musb_config,
293 .platform_ops = &sunxi_musb_ops,
296 void sunxi_musb_board_init(void)
298 musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE);