1 // SPDX-License-Identifier: GPL-2.0
3 * Allwinner SUNXI "glue layer"
5 * Copyright © 2015 Hans de Goede <hdegoede@redhat.com>
6 * Copyright © 2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
8 * Based on the sw_usb "Allwinner OTG Dual Role Controller" code.
9 * Copyright 2007-2012 (C) Allwinner Technology Co., Ltd.
10 * javen <javen@allwinnertech.com>
12 * Based on the DA8xx "glue layer" code.
13 * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
14 * Copyright (C) 2005-2006 by Texas Instruments
16 * This file is part of the Inventra Controller Driver for Linux.
20 #include <generic-phy.h>
21 #include <phy-sun4i-usb.h>
22 #include <asm/arch/cpu.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/gpio.h>
25 #include <asm-generic/gpio.h>
28 #include <linux/usb/musb.h>
29 #include "linux-compat.h"
30 #include "musb_core.h"
31 #include "musb_uboot.h"
33 /******************************************************************************
34 ******************************************************************************
35 * From the Allwinner driver
36 ******************************************************************************
37 ******************************************************************************/
39 /******************************************************************************
40 * From include/sunxi_usb_bsp.h
41 ******************************************************************************/
44 #define USBC_REG_o_ISCR 0x0400
45 #define USBC_REG_o_PHYCTL 0x0404
46 #define USBC_REG_o_PHYBIST 0x0408
47 #define USBC_REG_o_PHYTUNE 0x040c
49 #define USBC_REG_o_VEND0 0x0043
51 /* Interface Status and Control */
52 #define USBC_BP_ISCR_VBUS_VALID_FROM_DATA 30
53 #define USBC_BP_ISCR_VBUS_VALID_FROM_VBUS 29
54 #define USBC_BP_ISCR_EXT_ID_STATUS 28
55 #define USBC_BP_ISCR_EXT_DM_STATUS 27
56 #define USBC_BP_ISCR_EXT_DP_STATUS 26
57 #define USBC_BP_ISCR_MERGED_VBUS_STATUS 25
58 #define USBC_BP_ISCR_MERGED_ID_STATUS 24
60 #define USBC_BP_ISCR_ID_PULLUP_EN 17
61 #define USBC_BP_ISCR_DPDM_PULLUP_EN 16
62 #define USBC_BP_ISCR_FORCE_ID 14
63 #define USBC_BP_ISCR_FORCE_VBUS_VALID 12
64 #define USBC_BP_ISCR_VBUS_VALID_SRC 10
66 #define USBC_BP_ISCR_HOSC_EN 7
67 #define USBC_BP_ISCR_VBUS_CHANGE_DETECT 6
68 #define USBC_BP_ISCR_ID_CHANGE_DETECT 5
69 #define USBC_BP_ISCR_DPDM_CHANGE_DETECT 4
70 #define USBC_BP_ISCR_IRQ_ENABLE 3
71 #define USBC_BP_ISCR_VBUS_CHANGE_DETECT_EN 2
72 #define USBC_BP_ISCR_ID_CHANGE_DETECT_EN 1
73 #define USBC_BP_ISCR_DPDM_CHANGE_DETECT_EN 0
75 /******************************************************************************
77 ******************************************************************************/
79 #define OFF_SUN6I_AHB_RESET0 0x2c0
81 struct sunxi_musb_config {
82 struct musb_hdrc_config *config;
90 struct musb_host_data mdata;
91 struct sunxi_ccm_reg *ccm;
93 struct sunxi_musb_config *cfg;
97 #define to_sunxi_glue(d) container_of(d, struct sunxi_glue, dev)
99 static u32 USBC_WakeUp_ClearChangeDetect(u32 reg_val)
103 temp &= ~BIT(USBC_BP_ISCR_VBUS_CHANGE_DETECT);
104 temp &= ~BIT(USBC_BP_ISCR_ID_CHANGE_DETECT);
105 temp &= ~BIT(USBC_BP_ISCR_DPDM_CHANGE_DETECT);
110 static void USBC_EnableIdPullUp(__iomem void *base)
114 reg_val = musb_readl(base, USBC_REG_o_ISCR);
115 reg_val |= BIT(USBC_BP_ISCR_ID_PULLUP_EN);
116 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
117 musb_writel(base, USBC_REG_o_ISCR, reg_val);
120 static void USBC_EnableDpDmPullUp(__iomem void *base)
124 reg_val = musb_readl(base, USBC_REG_o_ISCR);
125 reg_val |= BIT(USBC_BP_ISCR_DPDM_PULLUP_EN);
126 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
127 musb_writel(base, USBC_REG_o_ISCR, reg_val);
130 static void USBC_ForceIdToLow(__iomem void *base)
134 reg_val = musb_readl(base, USBC_REG_o_ISCR);
135 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
136 reg_val |= (0x02 << USBC_BP_ISCR_FORCE_ID);
137 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
138 musb_writel(base, USBC_REG_o_ISCR, reg_val);
141 static void USBC_ForceIdToHigh(__iomem void *base)
145 reg_val = musb_readl(base, USBC_REG_o_ISCR);
146 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
147 reg_val |= (0x03 << USBC_BP_ISCR_FORCE_ID);
148 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
149 musb_writel(base, USBC_REG_o_ISCR, reg_val);
152 static void USBC_ForceVbusValidToLow(__iomem void *base)
156 reg_val = musb_readl(base, USBC_REG_o_ISCR);
157 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
158 reg_val |= (0x02 << USBC_BP_ISCR_FORCE_VBUS_VALID);
159 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
160 musb_writel(base, USBC_REG_o_ISCR, reg_val);
163 static void USBC_ForceVbusValidToHigh(__iomem void *base)
167 reg_val = musb_readl(base, USBC_REG_o_ISCR);
168 reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
169 reg_val |= (0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
170 reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
171 musb_writel(base, USBC_REG_o_ISCR, reg_val);
174 static void USBC_ConfigFIFO_Base(void)
178 /* config usb fifo, 8kb mode */
179 reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
180 reg_value &= ~(0x03 << 0);
182 writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
185 /******************************************************************************
186 * Needed for the DFU polling magic
187 ******************************************************************************/
189 static u8 last_int_usb;
191 bool dfu_usb_get_reset(void)
193 return !!(last_int_usb & MUSB_INTR_RESET);
196 /******************************************************************************
198 ******************************************************************************/
200 static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
202 struct musb *musb = __hci;
203 irqreturn_t retval = IRQ_NONE;
205 /* read and flush interrupts */
206 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
207 last_int_usb = musb->int_usb;
209 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
210 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
212 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
213 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
215 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
217 if (musb->int_usb || musb->int_tx || musb->int_rx)
218 retval |= musb_interrupt(musb);
223 /* musb_core does not call enable / disable in a balanced manner <sigh> */
224 static bool enabled = false;
226 static int sunxi_musb_enable(struct musb *musb)
228 struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
231 pr_debug("%s():\n", __func__);
233 musb_ep_select(musb->mregs, 0);
234 musb_writeb(musb->mregs, MUSB_FADDR, 0);
239 /* select PIO mode */
240 musb_writeb(musb->mregs, USBC_REG_o_VEND0, 0);
242 if (is_host_enabled(musb)) {
243 ret = sun4i_usb_phy_vbus_detect(&glue->phy);
245 printf("A charger is plugged into the OTG: ");
249 ret = sun4i_usb_phy_id_detect(&glue->phy);
251 printf("No host cable detected: ");
255 ret = generic_phy_power_on(&glue->phy);
257 pr_err("failed to power on USB PHY\n");
262 USBC_ForceVbusValidToHigh(musb->mregs);
268 static void sunxi_musb_disable(struct musb *musb)
270 struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
273 pr_debug("%s():\n", __func__);
278 if (is_host_enabled(musb)) {
279 ret = generic_phy_power_off(&glue->phy);
281 pr_err("failed to power off USB PHY\n");
286 USBC_ForceVbusValidToLow(musb->mregs);
287 mdelay(200); /* Wait for the current session to timeout */
292 static int sunxi_musb_init(struct musb *musb)
294 struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
297 pr_debug("%s():\n", __func__);
299 ret = generic_phy_init(&glue->phy);
301 pr_err("failed to init USB PHY\n");
305 musb->isr = sunxi_musb_interrupt;
307 setbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0));
308 if (glue->cfg->clkgate_bit)
309 setbits_le32(&glue->ccm->ahb_gate0,
310 BIT(glue->cfg->clkgate_bit));
312 if (glue->cfg->has_reset)
313 setbits_le32(glue->reg_reset0, BIT(AHB_GATE_OFFSET_USB0));
315 if (glue->cfg->rst_bit)
316 setbits_le32(glue->reg_reset0, BIT(glue->cfg->rst_bit));
318 USBC_ConfigFIFO_Base();
319 USBC_EnableDpDmPullUp(musb->mregs);
320 USBC_EnableIdPullUp(musb->mregs);
322 if (is_host_enabled(musb)) {
324 USBC_ForceIdToLow(musb->mregs);
326 /* Peripheral mode */
327 USBC_ForceIdToHigh(musb->mregs);
329 USBC_ForceVbusValidToHigh(musb->mregs);
334 static int sunxi_musb_exit(struct musb *musb)
336 struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
339 if (generic_phy_valid(&glue->phy)) {
340 ret = generic_phy_exit(&glue->phy);
342 dev_err(dev, "failed to power off usb phy\n");
347 if (glue->cfg->has_reset)
348 clrbits_le32(glue->reg_reset0, BIT(AHB_GATE_OFFSET_USB0));
350 if (glue->cfg->rst_bit)
351 clrbits_le32(glue->reg_reset0, BIT(glue->cfg->rst_bit));
353 clrbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0));
354 if (glue->cfg->clkgate_bit)
355 clrbits_le32(&glue->ccm->ahb_gate0,
356 BIT(glue->cfg->clkgate_bit));
361 static void sunxi_musb_pre_root_reset_end(struct musb *musb)
363 struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
365 sun4i_usb_phy_set_squelch_detect(&glue->phy, false);
368 static void sunxi_musb_post_root_reset_end(struct musb *musb)
370 struct sunxi_glue *glue = to_sunxi_glue(musb->controller);
372 sun4i_usb_phy_set_squelch_detect(&glue->phy, true);
375 static const struct musb_platform_ops sunxi_musb_ops = {
376 .init = sunxi_musb_init,
377 .exit = sunxi_musb_exit,
378 .enable = sunxi_musb_enable,
379 .disable = sunxi_musb_disable,
380 .pre_root_reset_end = sunxi_musb_pre_root_reset_end,
381 .post_root_reset_end = sunxi_musb_post_root_reset_end,
384 /* Allwinner OTG supports up to 5 endpoints */
385 #define SUNXI_MUSB_MAX_EP_NUM 6
386 #define SUNXI_MUSB_RAM_BITS 11
388 static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = {
389 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
390 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
391 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
392 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
393 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
394 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
395 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
396 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
397 MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512),
398 MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512),
401 /* H3/V3s OTG supports only 4 endpoints */
402 #define SUNXI_MUSB_MAX_EP_NUM_H3 5
404 static struct musb_fifo_cfg sunxi_musb_mode_cfg_h3[] = {
405 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
406 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
407 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
408 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
409 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
410 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
411 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
412 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
415 static struct musb_hdrc_config musb_config = {
416 .fifo_cfg = sunxi_musb_mode_cfg,
417 .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg),
420 .num_eps = SUNXI_MUSB_MAX_EP_NUM,
421 .ram_bits = SUNXI_MUSB_RAM_BITS,
424 static struct musb_hdrc_config musb_config_h3 = {
425 .fifo_cfg = sunxi_musb_mode_cfg_h3,
426 .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg_h3),
430 .num_eps = SUNXI_MUSB_MAX_EP_NUM_H3,
431 .ram_bits = SUNXI_MUSB_RAM_BITS,
434 static int musb_usb_probe(struct udevice *dev)
436 struct sunxi_glue *glue = dev_get_priv(dev);
437 struct musb_host_data *host = &glue->mdata;
438 struct musb_hdrc_platform_data pdata;
439 void *base = dev_read_addr_ptr(dev);
442 #ifdef CONFIG_USB_MUSB_HOST
443 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
449 glue->cfg = (struct sunxi_musb_config *)dev_get_driver_data(dev);
453 glue->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
454 if (IS_ERR(glue->ccm))
455 return PTR_ERR(glue->ccm);
457 glue->reg_reset0 = (void *)glue->ccm + glue->cfg->off_reset0;
459 ret = generic_phy_get_by_name(dev, "usb", &glue->phy);
461 pr_err("failed to get usb PHY\n");
466 memset(&pdata, 0, sizeof(pdata));
468 pdata.platform_ops = &sunxi_musb_ops;
469 pdata.config = glue->cfg->config;
471 #ifdef CONFIG_USB_MUSB_HOST
472 priv->desc_before_addr = true;
474 pdata.mode = MUSB_HOST;
475 host->host = musb_init_controller(&pdata, &glue->dev, base);
479 ret = musb_lowlevel_init(host);
481 printf("Allwinner mUSB OTG (Host)\n");
483 pdata.mode = MUSB_PERIPHERAL;
484 host->host = musb_register(&pdata, &glue->dev, base);
488 printf("Allwinner mUSB OTG (Peripheral)\n");
494 static int musb_usb_remove(struct udevice *dev)
496 struct sunxi_glue *glue = dev_get_priv(dev);
497 struct musb_host_data *host = &glue->mdata;
499 musb_stop(host->host);
506 static const struct sunxi_musb_config sun4i_a10_cfg = {
507 .config = &musb_config,
511 static const struct sunxi_musb_config sun6i_a31_cfg = {
512 .config = &musb_config,
514 .off_reset0 = OFF_SUN6I_AHB_RESET0,
517 static const struct sunxi_musb_config sun8i_h3_cfg = {
518 .config = &musb_config_h3,
522 .off_reset0 = OFF_SUN6I_AHB_RESET0,
525 static const struct udevice_id sunxi_musb_ids[] = {
526 { .compatible = "allwinner,sun4i-a10-musb",
527 .data = (ulong)&sun4i_a10_cfg },
528 { .compatible = "allwinner,sun6i-a31-musb",
529 .data = (ulong)&sun6i_a31_cfg },
530 { .compatible = "allwinner,sun8i-a33-musb",
531 .data = (ulong)&sun6i_a31_cfg },
532 { .compatible = "allwinner,sun8i-h3-musb",
533 .data = (ulong)&sun8i_h3_cfg },
537 U_BOOT_DRIVER(usb_musb) = {
538 .name = "sunxi-musb",
539 #ifdef CONFIG_USB_MUSB_HOST
542 .id = UCLASS_USB_GADGET_GENERIC,
544 .of_match = sunxi_musb_ids,
545 .probe = musb_usb_probe,
546 .remove = musb_usb_remove,
547 #ifdef CONFIG_USB_MUSB_HOST
548 .ops = &musb_usb_ops,
550 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
551 .priv_auto_alloc_size = sizeof(struct sunxi_glue),