2 * Texas Instruments AM35x "glue layer"
4 * Copyright (c) 2010, by Texas Instruments
6 * Based on the DA8xx "glue layer" code.
7 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
9 * This file is part of the Inventra Controller Driver for Linux.
11 * The Inventra Controller Driver for Linux is free software; you
12 * can redistribute it and/or modify it under the terms of the GNU
13 * General Public License version 2 as published by the Free Software
16 * The Inventra Controller Driver for Linux is distributed in
17 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
18 * without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 * License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with The Inventra Controller Driver for Linux ; if not,
24 * write to the Free Software Foundation, Inc., 59 Temple Place,
25 * Suite 330, Boston, MA 02111-1307 USA
30 #include <linux/init.h>
31 #include <linux/module.h>
32 #include <linux/clk.h>
33 #include <linux/err.h>
35 #include <linux/platform_device.h>
36 #include <linux/dma-mapping.h>
41 #include <asm/omap_musb.h>
42 #include "linux-compat.h"
45 #include "musb_core.h"
48 * AM35x specific definitions
50 /* USB 2.0 OTG module registers */
51 #define USB_REVISION_REG 0x00
52 #define USB_CTRL_REG 0x04
53 #define USB_STAT_REG 0x08
54 #define USB_EMULATION_REG 0x0c
56 #define USB_AUTOREQ_REG 0x14
57 #define USB_SRP_FIX_TIME_REG 0x18
58 #define USB_TEARDOWN_REG 0x1c
59 #define EP_INTR_SRC_REG 0x20
60 #define EP_INTR_SRC_SET_REG 0x24
61 #define EP_INTR_SRC_CLEAR_REG 0x28
62 #define EP_INTR_MASK_REG 0x2c
63 #define EP_INTR_MASK_SET_REG 0x30
64 #define EP_INTR_MASK_CLEAR_REG 0x34
65 #define EP_INTR_SRC_MASKED_REG 0x38
66 #define CORE_INTR_SRC_REG 0x40
67 #define CORE_INTR_SRC_SET_REG 0x44
68 #define CORE_INTR_SRC_CLEAR_REG 0x48
69 #define CORE_INTR_MASK_REG 0x4c
70 #define CORE_INTR_MASK_SET_REG 0x50
71 #define CORE_INTR_MASK_CLEAR_REG 0x54
72 #define CORE_INTR_SRC_MASKED_REG 0x58
74 #define USB_END_OF_INTR_REG 0x60
76 /* Control register bits */
77 #define AM35X_SOFT_RESET_MASK 1
79 /* USB interrupt register bits */
80 #define AM35X_INTR_USB_SHIFT 16
81 #define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
82 #define AM35X_INTR_DRVVBUS 0x100
83 #define AM35X_INTR_RX_SHIFT 16
84 #define AM35X_INTR_TX_SHIFT 0
85 #define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
86 #define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
87 #define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
88 #define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
90 #define USB_MENTOR_CORE_OFFSET 0x400
94 struct platform_device *musb;
98 #define glue_to_musb(g) platform_get_drvdata(g->musb)
101 * am35x_musb_enable - enable interrupts
104 static void am35x_musb_enable(struct musb *musb)
106 static int am35x_musb_enable(struct musb *musb)
109 void __iomem *reg_base = musb->ctrl_base;
112 /* Workaround: setup IRQs through both register sets. */
113 epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
114 ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
116 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
117 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
119 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
120 if (is_otg_enabled(musb))
121 musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
122 AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
129 * am35x_musb_disable - disable HDRC and flush interrupts
131 static void am35x_musb_disable(struct musb *musb)
133 void __iomem *reg_base = musb->ctrl_base;
135 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
136 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
137 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
138 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
139 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
143 #define portstate(stmt) stmt
145 static void am35x_musb_set_vbus(struct musb *musb, int is_on)
147 WARN_ON(is_on && is_peripheral_active(musb));
150 #define POLL_SECONDS 2
152 static struct timer_list otg_workaround;
154 static void otg_timer(unsigned long _musb)
156 struct musb *musb = (void *)_musb;
157 void __iomem *mregs = musb->mregs;
162 * We poll because AM35x's won't expose several OTG-critical
163 * status change events (from the transceiver) otherwise.
165 devctl = musb_readb(mregs, MUSB_DEVCTL);
166 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
167 otg_state_string(musb->xceiv->state));
169 spin_lock_irqsave(&musb->lock, flags);
170 switch (musb->xceiv->state) {
171 case OTG_STATE_A_WAIT_BCON:
172 devctl &= ~MUSB_DEVCTL_SESSION;
173 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
175 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
176 if (devctl & MUSB_DEVCTL_BDEVICE) {
177 musb->xceiv->state = OTG_STATE_B_IDLE;
180 musb->xceiv->state = OTG_STATE_A_IDLE;
184 case OTG_STATE_A_WAIT_VFALL:
185 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
186 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
187 MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
189 case OTG_STATE_B_IDLE:
190 if (!is_peripheral_enabled(musb))
193 devctl = musb_readb(mregs, MUSB_DEVCTL);
194 if (devctl & MUSB_DEVCTL_BDEVICE)
195 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
197 musb->xceiv->state = OTG_STATE_A_IDLE;
202 spin_unlock_irqrestore(&musb->lock, flags);
205 static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
207 static unsigned long last_timer;
209 if (!is_otg_enabled(musb))
213 timeout = jiffies + msecs_to_jiffies(3);
215 /* Never idle if active, or when VBUS timeout is not set as host */
216 if (musb->is_active || (musb->a_wait_bcon == 0 &&
217 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
218 dev_dbg(musb->controller, "%s active, deleting timer\n",
219 otg_state_string(musb->xceiv->state));
220 del_timer(&otg_workaround);
221 last_timer = jiffies;
225 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
226 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
229 last_timer = timeout;
231 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
232 otg_state_string(musb->xceiv->state),
233 jiffies_to_msecs(timeout - jiffies));
234 mod_timer(&otg_workaround, timeout);
238 static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
240 struct musb *musb = hci;
241 void __iomem *reg_base = musb->ctrl_base;
243 struct device *dev = musb->controller;
244 struct musb_hdrc_platform_data *plat = dev->platform_data;
245 struct omap_musb_board_data *data = plat->board_data;
246 struct usb_otg *otg = musb->xceiv->otg;
248 struct omap_musb_board_data *data =
249 (struct omap_musb_board_data *)musb->controller;
252 irqreturn_t ret = IRQ_NONE;
257 * It seems that on AM35X interrupt registers can be updated
258 * before core registers. This confuses the code.
259 * As a workaround add a small delay here.
263 spin_lock_irqsave(&musb->lock, flags);
265 /* Get endpoint interrupts */
266 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
269 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
272 (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
274 (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
277 /* Get usb core interrupts */
278 usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
279 if (!usbintr && !epintr)
283 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
286 (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
290 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
291 * AM35x's missing ID change IRQ. We need an ID change IRQ to
292 * switch appropriately between halves of the OTG state machine.
293 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
294 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
295 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
297 if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
298 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
299 void __iomem *mregs = musb->mregs;
300 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
303 err = is_host_enabled(musb) && (musb->int_usb &
304 MUSB_INTR_VBUSERROR);
307 * The Mentor core doesn't debounce VBUS as needed
308 * to cope with device connect current spikes. This
309 * means it's not uncommon for bus-powered devices
310 * to get VBUS errors during enumeration.
312 * This is a workaround, but newer RTL from Mentor
313 * seems to allow a better one: "re"-starting sessions
314 * without waiting for VBUS to stop registering in
317 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
318 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
319 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
320 WARNING("VBUS error workaround (delay coming)\n");
321 } else if (is_host_enabled(musb) && drvvbus) {
324 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
325 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
326 del_timer(&otg_workaround);
331 musb->xceiv->state = OTG_STATE_B_IDLE;
332 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
335 /* NOTE: this must complete power-on within 100 ms. */
336 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
337 drvvbus ? "on" : "off",
338 otg_state_string(musb->xceiv->state),
345 if (musb->int_tx || musb->int_rx || musb->int_usb)
346 ret |= musb_interrupt(musb);
349 /* EOI needs to be written for the IRQ to be re-asserted. */
350 if (ret == IRQ_HANDLED || epintr || usbintr) {
351 /* clear level interrupt */
355 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
359 /* Poll for ID change */
360 if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
361 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
364 spin_unlock_irqrestore(&musb->lock, flags);
370 static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
372 struct device *dev = musb->controller;
373 struct musb_hdrc_platform_data *plat = dev->platform_data;
374 struct omap_musb_board_data *data = plat->board_data;
378 data->set_mode(musb_mode);
386 static int am35x_musb_init(struct musb *musb)
389 struct device *dev = musb->controller;
390 struct musb_hdrc_platform_data *plat = dev->platform_data;
391 struct omap_musb_board_data *data = plat->board_data;
393 struct omap_musb_board_data *data =
394 (struct omap_musb_board_data *)musb->controller;
396 void __iomem *reg_base = musb->ctrl_base;
399 musb->mregs += USB_MENTOR_CORE_OFFSET;
401 /* Returns zero if e.g. not clocked */
402 rev = musb_readl(reg_base, USB_REVISION_REG);
407 usb_nop_xceiv_register();
408 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
409 if (IS_ERR_OR_NULL(musb->xceiv))
412 if (is_host_enabled(musb))
413 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
420 /* Reset the controller */
421 musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
423 /* Start the on-chip PHY and its PLL. */
424 if (data->set_phy_power)
425 data->set_phy_power(1);
429 musb->isr = am35x_musb_interrupt;
431 /* clear level interrupt */
438 static int am35x_musb_exit(struct musb *musb)
441 struct device *dev = musb->controller;
442 struct musb_hdrc_platform_data *plat = dev->platform_data;
443 struct omap_musb_board_data *data = plat->board_data;
445 struct omap_musb_board_data *data =
446 (struct omap_musb_board_data *)musb->controller;
450 if (is_host_enabled(musb))
451 del_timer_sync(&otg_workaround);
454 /* Shutdown the on-chip PHY and its PLL. */
455 if (data->set_phy_power)
456 data->set_phy_power(0);
459 usb_put_phy(musb->xceiv);
460 usb_nop_xceiv_unregister();
466 /* AM35x supports only 32bit read operation */
467 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
469 void __iomem *fifo = hw_ep->fifo;
473 /* Read for 32bit-aligned destination address */
474 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
475 readsl(fifo, dst, len >> 2);
480 * Now read the remaining 1 to 3 byte or complete length if
484 for (i = 0; i < (len >> 2); i++) {
485 *(u32 *) dst = musb_readl(fifo, 0);
491 val = musb_readl(fifo, 0);
492 memcpy(dst, &val, len);
497 static const struct musb_platform_ops am35x_ops = {
499 const struct musb_platform_ops am35x_ops = {
501 .init = am35x_musb_init,
502 .exit = am35x_musb_exit,
504 .enable = am35x_musb_enable,
505 .disable = am35x_musb_disable,
508 .set_mode = am35x_musb_set_mode,
509 .try_idle = am35x_musb_try_idle,
511 .set_vbus = am35x_musb_set_vbus,
516 static u64 am35x_dmamask = DMA_BIT_MASK(32);
518 static int __devinit am35x_probe(struct platform_device *pdev)
520 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
521 struct platform_device *musb;
522 struct am35x_glue *glue;
529 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
531 dev_err(&pdev->dev, "failed to allocate glue context\n");
535 musb = platform_device_alloc("musb-hdrc", -1);
537 dev_err(&pdev->dev, "failed to allocate musb device\n");
541 phy_clk = clk_get(&pdev->dev, "fck");
542 if (IS_ERR(phy_clk)) {
543 dev_err(&pdev->dev, "failed to get PHY clock\n");
544 ret = PTR_ERR(phy_clk);
548 clk = clk_get(&pdev->dev, "ick");
550 dev_err(&pdev->dev, "failed to get clock\n");
555 ret = clk_enable(phy_clk);
557 dev_err(&pdev->dev, "failed to enable PHY clock\n");
561 ret = clk_enable(clk);
563 dev_err(&pdev->dev, "failed to enable clock\n");
567 musb->dev.parent = &pdev->dev;
568 musb->dev.dma_mask = &am35x_dmamask;
569 musb->dev.coherent_dma_mask = am35x_dmamask;
571 glue->dev = &pdev->dev;
573 glue->phy_clk = phy_clk;
576 pdata->platform_ops = &am35x_ops;
578 platform_set_drvdata(pdev, glue);
580 ret = platform_device_add_resources(musb, pdev->resource,
581 pdev->num_resources);
583 dev_err(&pdev->dev, "failed to add resources\n");
587 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
589 dev_err(&pdev->dev, "failed to add platform_data\n");
593 ret = platform_device_add(musb);
595 dev_err(&pdev->dev, "failed to register musb device\n");
605 clk_disable(phy_clk);
614 platform_device_put(musb);
623 static int __devexit am35x_remove(struct platform_device *pdev)
625 struct am35x_glue *glue = platform_get_drvdata(pdev);
627 platform_device_del(glue->musb);
628 platform_device_put(glue->musb);
629 clk_disable(glue->clk);
630 clk_disable(glue->phy_clk);
632 clk_put(glue->phy_clk);
639 static int am35x_suspend(struct device *dev)
641 struct am35x_glue *glue = dev_get_drvdata(dev);
642 struct musb_hdrc_platform_data *plat = dev->platform_data;
643 struct omap_musb_board_data *data = plat->board_data;
645 /* Shutdown the on-chip PHY and its PLL. */
646 if (data->set_phy_power)
647 data->set_phy_power(0);
649 clk_disable(glue->phy_clk);
650 clk_disable(glue->clk);
655 static int am35x_resume(struct device *dev)
657 struct am35x_glue *glue = dev_get_drvdata(dev);
658 struct musb_hdrc_platform_data *plat = dev->platform_data;
659 struct omap_musb_board_data *data = plat->board_data;
662 /* Start the on-chip PHY and its PLL. */
663 if (data->set_phy_power)
664 data->set_phy_power(1);
666 ret = clk_enable(glue->phy_clk);
668 dev_err(dev, "failed to enable PHY clock\n");
672 ret = clk_enable(glue->clk);
674 dev_err(dev, "failed to enable clock\n");
681 static struct dev_pm_ops am35x_pm_ops = {
682 .suspend = am35x_suspend,
683 .resume = am35x_resume,
686 #define DEV_PM_OPS &am35x_pm_ops
688 #define DEV_PM_OPS NULL
691 static struct platform_driver am35x_driver = {
692 .probe = am35x_probe,
693 .remove = __devexit_p(am35x_remove),
695 .name = "musb-am35x",
700 MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
701 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
702 MODULE_LICENSE("GPL v2");
704 static int __init am35x_init(void)
706 return platform_driver_register(&am35x_driver);
708 module_init(am35x_init);
710 static void __exit am35x_exit(void)
712 platform_driver_unregister(&am35x_driver);
714 module_exit(am35x_exit);