1 // SPDX-License-Identifier: GPL-2.0
3 * Texas Instruments AM35x "glue layer"
5 * Copyright (c) 2010, by Texas Instruments
7 * Based on the DA8xx "glue layer" code.
8 * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
10 * This file is part of the Inventra Controller Driver for Linux.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/clk.h>
18 #include <linux/err.h>
20 #include <linux/platform_device.h>
21 #include <linux/dma-mapping.h>
26 #include <asm/omap_musb.h>
27 #include "linux-compat.h"
30 #include "musb_core.h"
33 * AM35x specific definitions
35 /* USB 2.0 OTG module registers */
36 #define USB_REVISION_REG 0x00
37 #define USB_CTRL_REG 0x04
38 #define USB_STAT_REG 0x08
39 #define USB_EMULATION_REG 0x0c
41 #define USB_AUTOREQ_REG 0x14
42 #define USB_SRP_FIX_TIME_REG 0x18
43 #define USB_TEARDOWN_REG 0x1c
44 #define EP_INTR_SRC_REG 0x20
45 #define EP_INTR_SRC_SET_REG 0x24
46 #define EP_INTR_SRC_CLEAR_REG 0x28
47 #define EP_INTR_MASK_REG 0x2c
48 #define EP_INTR_MASK_SET_REG 0x30
49 #define EP_INTR_MASK_CLEAR_REG 0x34
50 #define EP_INTR_SRC_MASKED_REG 0x38
51 #define CORE_INTR_SRC_REG 0x40
52 #define CORE_INTR_SRC_SET_REG 0x44
53 #define CORE_INTR_SRC_CLEAR_REG 0x48
54 #define CORE_INTR_MASK_REG 0x4c
55 #define CORE_INTR_MASK_SET_REG 0x50
56 #define CORE_INTR_MASK_CLEAR_REG 0x54
57 #define CORE_INTR_SRC_MASKED_REG 0x58
59 #define USB_END_OF_INTR_REG 0x60
61 /* Control register bits */
62 #define AM35X_SOFT_RESET_MASK 1
64 /* USB interrupt register bits */
65 #define AM35X_INTR_USB_SHIFT 16
66 #define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
67 #define AM35X_INTR_DRVVBUS 0x100
68 #define AM35X_INTR_RX_SHIFT 16
69 #define AM35X_INTR_TX_SHIFT 0
70 #define AM35X_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
71 #define AM35X_RX_EP_MASK 0xfffe /* 15 Rx EPs */
72 #define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
73 #define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
75 #define USB_MENTOR_CORE_OFFSET 0x400
79 struct platform_device *musb;
83 #define glue_to_musb(g) platform_get_drvdata(g->musb)
86 * am35x_musb_enable - enable interrupts
89 static void am35x_musb_enable(struct musb *musb)
91 static int am35x_musb_enable(struct musb *musb)
94 void __iomem *reg_base = musb->ctrl_base;
97 /* Workaround: setup IRQs through both register sets. */
98 epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
99 ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
101 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
102 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
104 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
105 if (is_otg_enabled(musb))
106 musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
107 AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
114 * am35x_musb_disable - disable HDRC and flush interrupts
116 static void am35x_musb_disable(struct musb *musb)
118 void __iomem *reg_base = musb->ctrl_base;
120 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
121 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
122 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
123 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
124 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
128 #define portstate(stmt) stmt
130 static void am35x_musb_set_vbus(struct musb *musb, int is_on)
132 WARN_ON(is_on && is_peripheral_active(musb));
135 #define POLL_SECONDS 2
137 static struct timer_list otg_workaround;
139 static void otg_timer(unsigned long _musb)
141 struct musb *musb = (void *)_musb;
142 void __iomem *mregs = musb->mregs;
147 * We poll because AM35x's won't expose several OTG-critical
148 * status change events (from the transceiver) otherwise.
150 devctl = musb_readb(mregs, MUSB_DEVCTL);
151 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
152 otg_state_string(musb->xceiv->state));
154 spin_lock_irqsave(&musb->lock, flags);
155 switch (musb->xceiv->state) {
156 case OTG_STATE_A_WAIT_BCON:
157 devctl &= ~MUSB_DEVCTL_SESSION;
158 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
160 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
161 if (devctl & MUSB_DEVCTL_BDEVICE) {
162 musb->xceiv->state = OTG_STATE_B_IDLE;
165 musb->xceiv->state = OTG_STATE_A_IDLE;
169 case OTG_STATE_A_WAIT_VFALL:
170 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
171 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
172 MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
174 case OTG_STATE_B_IDLE:
175 if (!is_peripheral_enabled(musb))
178 devctl = musb_readb(mregs, MUSB_DEVCTL);
179 if (devctl & MUSB_DEVCTL_BDEVICE)
180 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
182 musb->xceiv->state = OTG_STATE_A_IDLE;
187 spin_unlock_irqrestore(&musb->lock, flags);
190 static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
192 static unsigned long last_timer;
194 if (!is_otg_enabled(musb))
198 timeout = jiffies + msecs_to_jiffies(3);
200 /* Never idle if active, or when VBUS timeout is not set as host */
201 if (musb->is_active || (musb->a_wait_bcon == 0 &&
202 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
203 dev_dbg(musb->controller, "%s active, deleting timer\n",
204 otg_state_string(musb->xceiv->state));
205 del_timer(&otg_workaround);
206 last_timer = jiffies;
210 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
211 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
214 last_timer = timeout;
216 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
217 otg_state_string(musb->xceiv->state),
218 jiffies_to_msecs(timeout - jiffies));
219 mod_timer(&otg_workaround, timeout);
223 static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
225 struct musb *musb = hci;
226 void __iomem *reg_base = musb->ctrl_base;
228 struct device *dev = musb->controller;
229 struct musb_hdrc_platform_data *plat = dev->platform_data;
230 struct omap_musb_board_data *data = plat->board_data;
231 struct usb_otg *otg = musb->xceiv->otg;
233 struct omap_musb_board_data *data =
234 (struct omap_musb_board_data *)musb->controller;
237 irqreturn_t ret = IRQ_NONE;
242 * It seems that on AM35X interrupt registers can be updated
243 * before core registers. This confuses the code.
244 * As a workaround add a small delay here.
248 spin_lock_irqsave(&musb->lock, flags);
250 /* Get endpoint interrupts */
251 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
254 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
257 (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
259 (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
262 /* Get usb core interrupts */
263 usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
264 if (!usbintr && !epintr)
268 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
271 (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
275 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
276 * AM35x's missing ID change IRQ. We need an ID change IRQ to
277 * switch appropriately between halves of the OTG state machine.
278 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
279 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
280 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
282 if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
283 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
284 void __iomem *mregs = musb->mregs;
285 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
288 err = is_host_enabled(musb) && (musb->int_usb &
289 MUSB_INTR_VBUSERROR);
292 * The Mentor core doesn't debounce VBUS as needed
293 * to cope with device connect current spikes. This
294 * means it's not uncommon for bus-powered devices
295 * to get VBUS errors during enumeration.
297 * This is a workaround, but newer RTL from Mentor
298 * seems to allow a better one: "re"-starting sessions
299 * without waiting for VBUS to stop registering in
302 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
303 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
304 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
305 WARNING("VBUS error workaround (delay coming)\n");
306 } else if (is_host_enabled(musb) && drvvbus) {
309 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
310 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
311 del_timer(&otg_workaround);
316 musb->xceiv->state = OTG_STATE_B_IDLE;
317 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
320 /* NOTE: this must complete power-on within 100 ms. */
321 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
322 drvvbus ? "on" : "off",
323 otg_state_string(musb->xceiv->state),
330 if (musb->int_tx || musb->int_rx || musb->int_usb)
331 ret |= musb_interrupt(musb);
334 /* EOI needs to be written for the IRQ to be re-asserted. */
335 if (ret == IRQ_HANDLED || epintr || usbintr) {
336 /* clear level interrupt */
338 data->clear_irq(data->dev);
340 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
344 /* Poll for ID change */
345 if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
346 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
349 spin_unlock_irqrestore(&musb->lock, flags);
355 static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
357 struct device *dev = musb->controller;
358 struct musb_hdrc_platform_data *plat = dev->platform_data;
359 struct omap_musb_board_data *data = plat->board_data;
363 data->set_mode(musb_mode);
371 static int am35x_musb_init(struct musb *musb)
374 struct device *dev = musb->controller;
375 struct musb_hdrc_platform_data *plat = dev->platform_data;
376 struct omap_musb_board_data *data = plat->board_data;
378 struct omap_musb_board_data *data =
379 (struct omap_musb_board_data *)musb->controller;
381 void __iomem *reg_base = musb->ctrl_base;
384 musb->mregs += USB_MENTOR_CORE_OFFSET;
386 /* Returns zero if e.g. not clocked */
387 rev = musb_readl(reg_base, USB_REVISION_REG);
392 usb_nop_xceiv_register();
393 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
394 if (IS_ERR_OR_NULL(musb->xceiv))
397 if (is_host_enabled(musb))
398 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
403 data->reset(data->dev);
405 /* Reset the controller */
406 musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
408 /* Start the on-chip PHY and its PLL. */
409 if (data && data->set_phy_power)
410 data->set_phy_power(data->dev, 1);
414 musb->isr = am35x_musb_interrupt;
416 /* clear level interrupt */
418 data->clear_irq(data->dev);
423 static int am35x_musb_exit(struct musb *musb)
426 struct device *dev = musb->controller;
427 struct musb_hdrc_platform_data *plat = dev->platform_data;
428 struct omap_musb_board_data *data = plat->board_data;
430 struct omap_musb_board_data *data =
431 (struct omap_musb_board_data *)musb->controller;
435 if (is_host_enabled(musb))
436 del_timer_sync(&otg_workaround);
439 /* Shutdown the on-chip PHY and its PLL. */
440 if (data && data->set_phy_power)
441 data->set_phy_power(data->dev, 0);
444 usb_put_phy(musb->xceiv);
445 usb_nop_xceiv_unregister();
451 /* AM35x supports only 32bit read operation */
452 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
454 void __iomem *fifo = hw_ep->fifo;
458 /* Read for 32bit-aligned destination address */
459 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
460 readsl(fifo, dst, len >> 2);
465 * Now read the remaining 1 to 3 byte or complete length if
469 for (i = 0; i < (len >> 2); i++) {
470 *(u32 *) dst = musb_readl(fifo, 0);
476 val = musb_readl(fifo, 0);
477 memcpy(dst, &val, len);
482 static const struct musb_platform_ops am35x_ops = {
484 const struct musb_platform_ops am35x_ops = {
486 .init = am35x_musb_init,
487 .exit = am35x_musb_exit,
489 .enable = am35x_musb_enable,
490 .disable = am35x_musb_disable,
493 .set_mode = am35x_musb_set_mode,
494 .try_idle = am35x_musb_try_idle,
496 .set_vbus = am35x_musb_set_vbus,
501 static u64 am35x_dmamask = DMA_BIT_MASK(32);
503 static int __devinit am35x_probe(struct platform_device *pdev)
505 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
506 struct platform_device *musb;
507 struct am35x_glue *glue;
514 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
516 dev_err(&pdev->dev, "failed to allocate glue context\n");
520 musb = platform_device_alloc("musb-hdrc", -1);
522 dev_err(&pdev->dev, "failed to allocate musb device\n");
526 phy_clk = clk_get(&pdev->dev, "fck");
527 if (IS_ERR(phy_clk)) {
528 dev_err(&pdev->dev, "failed to get PHY clock\n");
529 ret = PTR_ERR(phy_clk);
533 clk = clk_get(&pdev->dev, "ick");
535 dev_err(&pdev->dev, "failed to get clock\n");
540 ret = clk_enable(phy_clk);
542 dev_err(&pdev->dev, "failed to enable PHY clock\n");
546 ret = clk_enable(clk);
548 dev_err(&pdev->dev, "failed to enable clock\n");
552 musb->dev.parent = &pdev->dev;
553 musb->dev.dma_mask = &am35x_dmamask;
554 musb->dev.coherent_dma_mask = am35x_dmamask;
556 glue->dev = &pdev->dev;
558 glue->phy_clk = phy_clk;
561 pdata->platform_ops = &am35x_ops;
563 platform_set_drvdata(pdev, glue);
565 ret = platform_device_add_resources(musb, pdev->resource,
566 pdev->num_resources);
568 dev_err(&pdev->dev, "failed to add resources\n");
572 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
574 dev_err(&pdev->dev, "failed to add platform_data\n");
578 ret = platform_device_add(musb);
580 dev_err(&pdev->dev, "failed to register musb device\n");
590 clk_disable(phy_clk);
599 platform_device_put(musb);
608 static int __devexit am35x_remove(struct platform_device *pdev)
610 struct am35x_glue *glue = platform_get_drvdata(pdev);
612 platform_device_del(glue->musb);
613 platform_device_put(glue->musb);
614 clk_disable(glue->clk);
615 clk_disable(glue->phy_clk);
617 clk_put(glue->phy_clk);
624 static int am35x_suspend(struct device *dev)
626 struct am35x_glue *glue = dev_get_drvdata(dev);
627 struct musb_hdrc_platform_data *plat = dev->platform_data;
628 struct omap_musb_board_data *data = plat->board_data;
630 /* Shutdown the on-chip PHY and its PLL. */
631 if (data && data->set_phy_power)
632 data->set_phy_power(data->dev, 0);
634 clk_disable(glue->phy_clk);
635 clk_disable(glue->clk);
640 static int am35x_resume(struct device *dev)
642 struct am35x_glue *glue = dev_get_drvdata(dev);
643 struct musb_hdrc_platform_data *plat = dev->platform_data;
644 struct omap_musb_board_data *data = plat->board_data;
647 /* Start the on-chip PHY and its PLL. */
648 if (data && data->set_phy_power)
649 data->set_phy_power(data->dev, 1);
651 ret = clk_enable(glue->phy_clk);
653 dev_err(dev, "failed to enable PHY clock\n");
657 ret = clk_enable(glue->clk);
659 dev_err(dev, "failed to enable clock\n");
666 static struct dev_pm_ops am35x_pm_ops = {
667 .suspend = am35x_suspend,
668 .resume = am35x_resume,
671 #define DEV_PM_OPS &am35x_pm_ops
673 #define DEV_PM_OPS NULL
676 static struct platform_driver am35x_driver = {
677 .probe = am35x_probe,
678 .remove = __devexit_p(am35x_remove),
680 .name = "musb-am35x",
685 MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
686 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
687 MODULE_LICENSE("GPL v2");
689 static int __init am35x_init(void)
691 return platform_driver_register(&am35x_driver);
693 module_init(am35x_init);
695 static void __exit am35x_exit(void)
697 platform_driver_unregister(&am35x_driver);
699 module_exit(am35x_exit);