3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software Foundation,
21 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #ifndef __LINUX_XHCI_HCD_H
25 #define __LINUX_XHCI_HCD_H
27 #include <linux/usb.h>
28 #include <linux/timer.h>
29 #include <linux/kernel.h>
30 #include <linux/usb/hcd.h>
32 /* Code sharing between pci-quirks and xhci hcd */
33 #include "xhci-ext-caps.h"
34 #include "pci-quirks.h"
36 /* xHCI PCI Configuration Registers */
37 #define XHCI_SBRN_OFFSET (0x60)
39 /* Max number of USB devices for any host controller - limit in section 6.1 */
40 #define MAX_HC_SLOTS 256
41 /* Section 5.3.3 - MaxPorts */
42 #define MAX_HC_PORTS 127
45 * xHCI register interface.
46 * This corresponds to the eXtensible Host Controller Interface (xHCI)
47 * Revision 0.95 specification
51 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
52 * @hc_capbase: length of the capabilities register and HC version number
53 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
54 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
55 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
56 * @hcc_params: HCCPARAMS - Capability Parameters
57 * @db_off: DBOFF - Doorbell array offset
58 * @run_regs_off: RTSOFF - Runtime register space offset
60 struct xhci_cap_regs {
68 /* Reserved up to (CAPLENGTH - 0x1C) */
71 /* hc_capbase bitmasks */
72 /* bits 7:0 - how long is the Capabilities register */
73 #define HC_LENGTH(p) XHCI_HC_LENGTH(p)
75 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
77 /* HCSPARAMS1 - hcs_params1 - bitmasks */
78 /* bits 0:7, Max Device Slots */
79 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
80 #define HCS_SLOTS_MASK 0xff
81 /* bits 8:18, Max Interrupters */
82 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
83 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
84 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
86 /* HCSPARAMS2 - hcs_params2 - bitmasks */
87 /* bits 0:3, frames or uframes that SW needs to queue transactions
88 * ahead of the HW to meet periodic deadlines */
89 #define HCS_IST(p) (((p) >> 0) & 0xf)
90 /* bits 4:7, max number of Event Ring segments */
91 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
92 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
93 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
94 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
95 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
97 /* HCSPARAMS3 - hcs_params3 - bitmasks */
98 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
99 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
100 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
101 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
103 /* HCCPARAMS - hcc_params - bitmasks */
104 /* true: HC can use 64-bit address pointers */
105 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
106 /* true: HC can do bandwidth negotiation */
107 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
108 /* true: HC uses 64-byte Device Context structures
109 * FIXME 64-byte context structures aren't supported yet.
111 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
112 /* true: HC has port power switches */
113 #define HCC_PPC(p) ((p) & (1 << 3))
114 /* true: HC has port indicators */
115 #define HCS_INDICATOR(p) ((p) & (1 << 4))
116 /* true: HC has Light HC Reset Capability */
117 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
118 /* true: HC supports latency tolerance messaging */
119 #define HCC_LTC(p) ((p) & (1 << 6))
120 /* true: no secondary Stream ID Support */
121 #define HCC_NSS(p) ((p) & (1 << 7))
122 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
123 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
124 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
125 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
127 /* db_off bitmask - bits 0:1 reserved */
128 #define DBOFF_MASK (~0x3)
130 /* run_regs_off bitmask - bits 0:4 reserved */
131 #define RTSOFF_MASK (~0x1f)
134 /* Number of registers per port */
135 #define NUM_PORT_REGS 4
143 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
144 * @command: USBCMD - xHC command register
145 * @status: USBSTS - xHC status register
146 * @page_size: This indicates the page size that the host controller
147 * supports. If bit n is set, the HC supports a page size
148 * of 2^(n+12), up to a 128MB page size.
149 * 4K is the minimum page size.
150 * @cmd_ring: CRP - 64-bit Command Ring Pointer
151 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
152 * @config_reg: CONFIG - Configure Register
153 * @port_status_base: PORTSCn - base address for Port Status and Control
154 * Each port has a Port Status and Control register,
155 * followed by a Port Power Management Status and Control
156 * register, a Port Link Info register, and a reserved
158 * @port_power_base: PORTPMSCn - base address for
159 * Port Power Management Status and Control
160 * @port_link_base: PORTLIn - base address for Port Link Info (current
161 * Link PM state and control) for USB 2.1 and USB 3.0
164 struct xhci_op_regs {
170 __le32 dev_notification;
172 /* rsvd: offset 0x20-2F */
176 /* rsvd: offset 0x3C-3FF */
177 __le32 reserved4[241];
178 /* port 1 registers, which serve as a base address for other ports */
179 __le32 port_status_base;
180 __le32 port_power_base;
181 __le32 port_link_base;
183 /* registers for ports 2-255 */
184 __le32 reserved6[NUM_PORT_REGS*254];
187 /* USBCMD - USB command - command bitmasks */
188 /* start/stop HC execution - do not write unless HC is halted*/
189 #define CMD_RUN XHCI_CMD_RUN
190 /* Reset HC - resets internal HC state machine and all registers (except
191 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
192 * The xHCI driver must reinitialize the xHC after setting this bit.
194 #define CMD_RESET (1 << 1)
195 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
196 #define CMD_EIE XHCI_CMD_EIE
197 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
198 #define CMD_HSEIE XHCI_CMD_HSEIE
199 /* bits 4:6 are reserved (and should be preserved on writes). */
200 /* light reset (port status stays unchanged) - reset completed when this is 0 */
201 #define CMD_LRESET (1 << 7)
202 /* host controller save/restore state. */
203 #define CMD_CSS (1 << 8)
204 #define CMD_CRS (1 << 9)
205 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
206 #define CMD_EWE XHCI_CMD_EWE
207 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
208 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
209 * '0' means the xHC can power it off if all ports are in the disconnect,
210 * disabled, or powered-off state.
212 #define CMD_PM_INDEX (1 << 11)
213 /* bits 12:31 are reserved (and should be preserved on writes). */
215 /* IMAN - Interrupt Management Register */
216 #define IMAN_IE (1 << 1)
217 #define IMAN_IP (1 << 0)
219 /* USBSTS - USB status - status bitmasks */
220 /* HC not running - set to 1 when run/stop bit is cleared. */
221 #define STS_HALT XHCI_STS_HALT
222 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
223 #define STS_FATAL (1 << 2)
224 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
225 #define STS_EINT (1 << 3)
226 /* port change detect */
227 #define STS_PORT (1 << 4)
228 /* bits 5:7 reserved and zeroed */
229 /* save state status - '1' means xHC is saving state */
230 #define STS_SAVE (1 << 8)
231 /* restore state status - '1' means xHC is restoring state */
232 #define STS_RESTORE (1 << 9)
233 /* true: save or restore error */
234 #define STS_SRE (1 << 10)
235 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
236 #define STS_CNR XHCI_STS_CNR
237 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
238 #define STS_HCE (1 << 12)
239 /* bits 13:31 reserved and should be preserved */
242 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
243 * Generate a device notification event when the HC sees a transaction with a
244 * notification type that matches a bit set in this bit field.
246 #define DEV_NOTE_MASK (0xffff)
247 #define ENABLE_DEV_NOTE(x) (1 << (x))
248 /* Most of the device notification types should only be used for debug.
249 * SW does need to pay attention to function wake notifications.
251 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
253 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
254 /* bit 0 is the command ring cycle state */
255 /* stop ring operation after completion of the currently executing command */
256 #define CMD_RING_PAUSE (1 << 1)
257 /* stop ring immediately - abort the currently executing command */
258 #define CMD_RING_ABORT (1 << 2)
259 /* true: command ring is running */
260 #define CMD_RING_RUNNING (1 << 3)
261 /* bits 4:5 reserved and should be preserved */
262 /* Command Ring pointer - bit mask for the lower 32 bits. */
263 #define CMD_RING_RSVD_BITS (0x3f)
265 /* CONFIG - Configure Register - config_reg bitmasks */
266 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
267 #define MAX_DEVS(p) ((p) & 0xff)
268 /* bits 8:31 - reserved and should be preserved */
270 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
271 /* true: device connected */
272 #define PORT_CONNECT (1 << 0)
273 /* true: port enabled */
274 #define PORT_PE (1 << 1)
275 /* bit 2 reserved and zeroed */
276 /* true: port has an over-current condition */
277 #define PORT_OC (1 << 3)
278 /* true: port reset signaling asserted */
279 #define PORT_RESET (1 << 4)
280 /* Port Link State - bits 5:8
281 * A read gives the current link PM state of the port,
282 * a write with Link State Write Strobe set sets the link state.
284 #define PORT_PLS_MASK (0xf << 5)
285 #define XDEV_U0 (0x0 << 5)
286 #define XDEV_U1 (0x1 << 5)
287 #define XDEV_U2 (0x2 << 5)
288 #define XDEV_U3 (0x3 << 5)
289 #define XDEV_INACTIVE (0x6 << 5)
290 #define XDEV_POLLING (0x7 << 5)
291 #define XDEV_RECOVERY (0x8 << 5)
292 #define XDEV_COMP_MODE (0xa << 5)
293 #define XDEV_RESUME (0xf << 5)
294 /* true: port has power (see HCC_PPC) */
295 #define PORT_POWER (1 << 9)
296 /* bits 10:13 indicate device speed:
297 * 0 - undefined speed - port hasn't be initialized by a reset yet
304 #define DEV_SPEED_MASK (0xf << 10)
305 #define XDEV_FS (0x1 << 10)
306 #define XDEV_LS (0x2 << 10)
307 #define XDEV_HS (0x3 << 10)
308 #define XDEV_SS (0x4 << 10)
309 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
310 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
311 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
312 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
313 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
314 /* Bits 20:23 in the Slot Context are the speed for the device */
315 #define SLOT_SPEED_FS (XDEV_FS << 10)
316 #define SLOT_SPEED_LS (XDEV_LS << 10)
317 #define SLOT_SPEED_HS (XDEV_HS << 10)
318 #define SLOT_SPEED_SS (XDEV_SS << 10)
319 /* Port Indicator Control */
320 #define PORT_LED_OFF (0 << 14)
321 #define PORT_LED_AMBER (1 << 14)
322 #define PORT_LED_GREEN (2 << 14)
323 #define PORT_LED_MASK (3 << 14)
324 /* Port Link State Write Strobe - set this when changing link state */
325 #define PORT_LINK_STROBE (1 << 16)
326 /* true: connect status change */
327 #define PORT_CSC (1 << 17)
328 /* true: port enable change */
329 #define PORT_PEC (1 << 18)
330 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
331 * into an enabled state, and the device into the default state. A "warm" reset
332 * also resets the link, forcing the device through the link training sequence.
333 * SW can also look at the Port Reset register to see when warm reset is done.
335 #define PORT_WRC (1 << 19)
336 /* true: over-current change */
337 #define PORT_OCC (1 << 20)
338 /* true: reset change - 1 to 0 transition of PORT_RESET */
339 #define PORT_RC (1 << 21)
340 /* port link status change - set on some port link state transitions:
342 * ------------------------------------------------------------------------------
343 * - U3 to Resume Wakeup signaling from a device
344 * - Resume to Recovery to U0 USB 3.0 device resume
345 * - Resume to U0 USB 2.0 device resume
346 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
347 * - U3 to U0 Software resume of USB 2.0 device complete
348 * - U2 to U0 L1 resume of USB 2.1 device complete
349 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
350 * - U0 to disabled L1 entry error with USB 2.1 device
351 * - Any state to inactive Error on USB 3.0 port
353 #define PORT_PLC (1 << 22)
354 /* port configure error change - port failed to configure its link partner */
355 #define PORT_CEC (1 << 23)
356 /* Cold Attach Status - xHC can set this bit to report device attached during
357 * Sx state. Warm port reset should be perfomed to clear this bit and move port
358 * to connected state.
360 #define PORT_CAS (1 << 24)
361 /* wake on connect (enable) */
362 #define PORT_WKCONN_E (1 << 25)
363 /* wake on disconnect (enable) */
364 #define PORT_WKDISC_E (1 << 26)
365 /* wake on over-current (enable) */
366 #define PORT_WKOC_E (1 << 27)
367 /* bits 28:29 reserved */
368 /* true: device is removable - for USB 3.0 roothub emulation */
369 #define PORT_DEV_REMOVE (1 << 30)
370 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
371 #define PORT_WR (1 << 31)
373 /* We mark duplicate entries with -1 */
374 #define DUPLICATE_ENTRY ((u8)(-1))
376 /* Port Power Management Status and Control - port_power_base bitmasks */
377 /* Inactivity timer value for transitions into U1, in microseconds.
378 * Timeout can be up to 127us. 0xFF means an infinite timeout.
380 #define PORT_U1_TIMEOUT(p) ((p) & 0xff)
381 #define PORT_U1_TIMEOUT_MASK 0xff
382 /* Inactivity timer value for transitions into U2 */
383 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
384 #define PORT_U2_TIMEOUT_MASK (0xff << 8)
385 /* Bits 24:31 for port testing */
387 /* USB2 Protocol PORTSPMSC */
388 #define PORT_L1S_MASK 7
389 #define PORT_L1S_SUCCESS 1
390 #define PORT_RWE (1 << 3)
391 #define PORT_HIRD(p) (((p) & 0xf) << 4)
392 #define PORT_HIRD_MASK (0xf << 4)
393 #define PORT_L1DS_MASK (0xff << 8)
394 #define PORT_L1DS(p) (((p) & 0xff) << 8)
395 #define PORT_HLE (1 << 16)
398 /* USB2 Protocol PORTHLPMC */
399 #define PORT_HIRDM(p)((p) & 3)
400 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
401 #define PORT_BESLD(p)(((p) & 0xf) << 10)
403 /* use 512 microseconds as USB2 LPM L1 default timeout. */
404 #define XHCI_L1_TIMEOUT 512
406 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
407 * Safe to use with mixed HIRD and BESL systems (host and device) and is used
408 * by other operating systems.
410 * XHCI 1.0 errata 8/14/12 Table 13 notes:
411 * "Software should choose xHC BESL/BESLD field values that do not violate a
412 * device's resume latency requirements,
413 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
414 * or not program values < '4' if BLC = '0' and a BESL device is attached.
416 #define XHCI_DEFAULT_BESL 4
419 * USB3 specification define a 360ms tPollingLFPSTiemout for USB3 ports
420 * to complete link training. usually link trainig completes much faster
421 * so check status 10 times with 36ms sleep in places we need to wait for
422 * polling to complete.
424 #define XHCI_PORT_POLLING_LFPS_TIME 36
427 * struct xhci_intr_reg - Interrupt Register Set
428 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
429 * interrupts and check for pending interrupts.
430 * @irq_control: IMOD - Interrupt Moderation Register.
431 * Used to throttle interrupts.
432 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
433 * @erst_base: ERST base address.
434 * @erst_dequeue: Event ring dequeue pointer.
436 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
437 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
438 * multiple segments of the same size. The HC places events on the ring and
439 * "updates the Cycle bit in the TRBs to indicate to software the current
440 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
441 * updates the dequeue pointer.
443 struct xhci_intr_reg {
452 /* irq_pending bitmasks */
453 #define ER_IRQ_PENDING(p) ((p) & 0x1)
454 /* bits 2:31 need to be preserved */
455 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
456 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
457 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
458 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
460 /* irq_control bitmasks */
461 /* Minimum interval between interrupts (in 250ns intervals). The interval
462 * between interrupts will be longer if there are no events on the event ring.
463 * Default is 4000 (1 ms).
465 #define ER_IRQ_INTERVAL_MASK (0xffff)
466 /* Counter used to count down the time to the next interrupt - HW use only */
467 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
469 /* erst_size bitmasks */
470 /* Preserve bits 16:31 of erst_size */
471 #define ERST_SIZE_MASK (0xffff << 16)
473 /* erst_dequeue bitmasks */
474 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
475 * where the current dequeue pointer lies. This is an optional HW hint.
477 #define ERST_DESI_MASK (0x7)
478 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
479 * a work queue (or delayed service routine)?
481 #define ERST_EHB (1 << 3)
482 #define ERST_PTR_MASK (0xf)
485 * struct xhci_run_regs
487 * MFINDEX - current microframe number
489 * Section 5.5 Host Controller Runtime Registers:
490 * "Software should read and write these registers using only Dword (32 bit)
491 * or larger accesses"
493 struct xhci_run_regs {
494 __le32 microframe_index;
496 struct xhci_intr_reg ir_set[128];
500 * struct doorbell_array
502 * Bits 0 - 7: Endpoint target
504 * Bits 16 - 31: Stream ID
508 struct xhci_doorbell_array {
509 __le32 doorbell[256];
512 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
513 #define DB_VALUE_HOST 0x00000000
516 * struct xhci_protocol_caps
517 * @revision: major revision, minor revision, capability ID,
518 * and next capability pointer.
519 * @name_string: Four ASCII characters to say which spec this xHC
520 * follows, typically "USB ".
521 * @port_info: Port offset, count, and protocol-defined information.
523 struct xhci_protocol_caps {
529 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
530 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
531 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
534 * struct xhci_container_ctx
535 * @type: Type of context. Used to calculated offsets to contained contexts.
536 * @size: Size of the context data
537 * @bytes: The raw context data given to HW
538 * @dma: dma address of the bytes
540 * Represents either a Device or Input context. Holds a pointer to the raw
541 * memory used for the context (bytes) and dma address of it (dma).
543 struct xhci_container_ctx {
545 #define XHCI_CTX_TYPE_DEVICE 0x1
546 #define XHCI_CTX_TYPE_INPUT 0x2
555 * struct xhci_slot_ctx
556 * @dev_info: Route string, device speed, hub info, and last valid endpoint
557 * @dev_info2: Max exit latency for device number, root hub port number
558 * @tt_info: tt_info is used to construct split transaction tokens
559 * @dev_state: slot state and device address
561 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
562 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
563 * reserved at the end of the slot context for HC internal use.
565 struct xhci_slot_ctx {
570 /* offset 0x10 to 0x1f reserved for HC internal use */
574 /* dev_info bitmasks */
575 /* Route String - 0:19 */
576 #define ROUTE_STRING_MASK (0xfffff)
577 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
578 #define DEV_SPEED (0xf << 20)
579 /* bit 24 reserved */
580 /* Is this LS/FS device connected through a HS hub? - bit 25 */
581 #define DEV_MTT (0x1 << 25)
582 /* Set if the device is a hub - bit 26 */
583 #define DEV_HUB (0x1 << 26)
584 /* Index of the last valid endpoint context in this device context - 27:31 */
585 #define LAST_CTX_MASK (0x1f << 27)
586 #define LAST_CTX(p) ((p) << 27)
587 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
588 #define SLOT_FLAG (1 << 0)
589 #define EP0_FLAG (1 << 1)
591 /* dev_info2 bitmasks */
592 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
593 #define MAX_EXIT (0xffff)
594 /* Root hub port number that is needed to access the USB device */
595 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
596 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
597 /* Maximum number of ports under a hub device */
598 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
600 /* tt_info bitmasks */
602 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
603 * The Slot ID of the hub that isolates the high speed signaling from
604 * this low or full-speed device. '0' if attached to root hub port.
606 #define TT_SLOT (0xff)
608 * The number of the downstream facing port of the high-speed hub
609 * '0' if the device is not low or full speed.
611 #define TT_PORT (0xff << 8)
612 #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
614 /* dev_state bitmasks */
615 /* USB device address - assigned by the HC */
616 #define DEV_ADDR_MASK (0xff)
617 /* bits 8:26 reserved */
619 #define SLOT_STATE (0x1f << 27)
620 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
622 #define SLOT_STATE_DISABLED 0
623 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
624 #define SLOT_STATE_DEFAULT 1
625 #define SLOT_STATE_ADDRESSED 2
626 #define SLOT_STATE_CONFIGURED 3
630 * @ep_info: endpoint state, streams, mult, and interval information.
631 * @ep_info2: information on endpoint type, max packet size, max burst size,
632 * error count, and whether the HC will force an event for all
634 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
635 * defines one stream, this points to the endpoint transfer ring.
636 * Otherwise, it points to a stream context array, which has a
637 * ring pointer for each flow.
639 * Average TRB lengths for the endpoint ring and
640 * max payload within an Endpoint Service Interval Time (ESIT).
642 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
643 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
644 * reserved at the end of the endpoint context for HC internal use.
651 /* offset 0x14 - 0x1f reserved for HC internal use */
655 /* ep_info bitmasks */
657 * Endpoint State - bits 0:2
660 * 2 - halted due to halt condition - ok to manipulate endpoint ring
665 #define EP_STATE_MASK (0xf)
666 #define EP_STATE_DISABLED 0
667 #define EP_STATE_RUNNING 1
668 #define EP_STATE_HALTED 2
669 #define EP_STATE_STOPPED 3
670 #define EP_STATE_ERROR 4
671 /* Mult - Max number of burtst within an interval, in EP companion desc. */
672 #define EP_MULT(p) (((p) & 0x3) << 8)
673 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
674 /* bits 10:14 are Max Primary Streams */
675 /* bit 15 is Linear Stream Array */
676 /* Interval - period between requests to an endpoint - 125u increments. */
677 #define EP_INTERVAL(p) (((p) & 0xff) << 16)
678 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
679 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
680 #define EP_MAXPSTREAMS_MASK (0x1f << 10)
681 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
682 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
683 #define EP_HAS_LSA (1 << 15)
685 /* ep_info2 bitmasks */
687 * Force Event - generate transfer events for all TRBs for this endpoint
688 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
690 #define FORCE_EVENT (0x1)
691 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
692 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
693 #define EP_TYPE(p) ((p) << 3)
694 #define ISOC_OUT_EP 1
695 #define BULK_OUT_EP 2
702 /* bit 7 is Host Initiate Disable - for disabling stream selection */
703 #define MAX_BURST(p) (((p)&0xff) << 8)
704 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
705 #define MAX_PACKET(p) (((p)&0xffff) << 16)
706 #define MAX_PACKET_MASK (0xffff << 16)
707 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
709 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
712 #define GET_MAX_PACKET(p) ((p) & 0x7ff)
714 /* tx_info bitmasks */
715 #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff)
716 #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16)
717 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
720 #define EP_CTX_CYCLE_MASK (1 << 0)
721 #define SCTX_DEQ_MASK (~0xfL)
725 * struct xhci_input_control_context
726 * Input control context; see section 6.2.5.
728 * @drop_context: set the bit of the endpoint context you want to disable
729 * @add_context: set the bit of the endpoint context you want to enable
731 struct xhci_input_control_ctx {
737 #define EP_IS_ADDED(ctrl_ctx, i) \
738 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
739 #define EP_IS_DROPPED(ctrl_ctx, i) \
740 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
742 /* Represents everything that is needed to issue a command on the command ring.
743 * It's useful to pre-allocate these for commands that cannot fail due to
744 * out-of-memory errors, like freeing streams.
746 struct xhci_command {
747 /* Input context for changing device state */
748 struct xhci_container_ctx *in_ctx;
750 /* If completion is null, no one is waiting on this command
751 * and the structure can be freed after the command completes.
753 struct completion *completion;
754 union xhci_trb *command_trb;
755 struct list_head cmd_list;
758 /* drop context bitmasks */
759 #define DROP_EP(x) (0x1 << x)
760 /* add context bitmasks */
761 #define ADD_EP(x) (0x1 << x)
763 struct xhci_stream_ctx {
764 /* 64-bit stream ring address, cycle state, and stream type */
766 /* offset 0x14 - 0x1f reserved for HC internal use */
770 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
771 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
772 /* Secondary stream array type, dequeue pointer is to a transfer ring */
774 /* Primary stream array type, dequeue pointer is to a transfer ring */
776 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
781 #define SCT_SSA_128 6
782 #define SCT_SSA_256 7
784 /* Assume no secondary streams for now */
785 struct xhci_stream_info {
786 struct xhci_ring **stream_rings;
787 /* Number of streams, including stream 0 (which drivers can't use) */
788 unsigned int num_streams;
789 /* The stream context array may be bigger than
790 * the number of streams the driver asked for
792 struct xhci_stream_ctx *stream_ctx_array;
793 unsigned int num_stream_ctxs;
794 dma_addr_t ctx_array_dma;
795 /* For mapping physical TRB addresses to segments in stream rings */
796 struct radix_tree_root trb_address_map;
797 struct xhci_command *free_streams_command;
800 #define SMALL_STREAM_ARRAY_SIZE 256
801 #define MEDIUM_STREAM_ARRAY_SIZE 1024
803 /* Some Intel xHCI host controllers need software to keep track of the bus
804 * bandwidth. Keep track of endpoint info here. Each root port is allocated
805 * the full bus bandwidth. We must also treat TTs (including each port under a
806 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
807 * (DMI) also limits the total bandwidth (across all domains) that can be used.
809 struct xhci_bw_info {
810 /* ep_interval is zero-based */
811 unsigned int ep_interval;
812 /* mult and num_packets are one-based */
814 unsigned int num_packets;
815 unsigned int max_packet_size;
816 unsigned int max_esit_payload;
820 /* "Block" sizes in bytes the hardware uses for different device speeds.
821 * The logic in this part of the hardware limits the number of bits the hardware
822 * can use, so must represent bandwidth in a less precise manner to mimic what
823 * the scheduler hardware computes.
830 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
831 * with each byte transferred. SuperSpeed devices have an initial overhead to
832 * set up bursts. These are in blocks, see above. LS overhead has already been
833 * translated into FS blocks.
835 #define DMI_OVERHEAD 8
836 #define DMI_OVERHEAD_BURST 4
837 #define SS_OVERHEAD 8
838 #define SS_OVERHEAD_BURST 32
839 #define HS_OVERHEAD 26
840 #define FS_OVERHEAD 20
841 #define LS_OVERHEAD 128
842 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
843 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
844 * of overhead associated with split transfers crossing microframe boundaries.
845 * 31 blocks is pure protocol overhead.
847 #define TT_HS_OVERHEAD (31 + 94)
848 #define TT_DMI_OVERHEAD (25 + 12)
850 /* Bandwidth limits in blocks */
851 #define FS_BW_LIMIT 1285
852 #define TT_BW_LIMIT 1320
853 #define HS_BW_LIMIT 1607
854 #define SS_BW_LIMIT_IN 3906
855 #define DMI_BW_LIMIT_IN 3906
856 #define SS_BW_LIMIT_OUT 3906
857 #define DMI_BW_LIMIT_OUT 3906
859 /* Percentage of bus bandwidth reserved for non-periodic transfers */
860 #define FS_BW_RESERVED 10
861 #define HS_BW_RESERVED 20
862 #define SS_BW_RESERVED 10
864 struct xhci_virt_ep {
865 struct xhci_ring *ring;
866 /* Related to endpoints that are configured to use stream IDs only */
867 struct xhci_stream_info *stream_info;
868 /* Temporary storage in case the configure endpoint command fails and we
869 * have to restore the device state to the previous state
871 struct xhci_ring *new_ring;
872 unsigned int ep_state;
873 #define SET_DEQ_PENDING (1 << 0)
874 #define EP_HALTED (1 << 1) /* For stall handling */
875 #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */
876 /* Transitioning the endpoint to using streams, don't enqueue URBs */
877 #define EP_GETTING_STREAMS (1 << 3)
878 #define EP_HAS_STREAMS (1 << 4)
879 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
880 #define EP_GETTING_NO_STREAMS (1 << 5)
881 /* ---- Related to URB cancellation ---- */
882 struct list_head cancelled_td_list;
883 struct xhci_td *stopped_td;
884 unsigned int stopped_stream;
885 /* Watchdog timer for stop endpoint command to cancel URBs */
886 struct timer_list stop_cmd_timer;
887 int stop_cmds_pending;
888 struct xhci_hcd *xhci;
889 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
890 * command. We'll need to update the ring's dequeue segment and dequeue
891 * pointer after the command completes.
893 struct xhci_segment *queued_deq_seg;
894 union xhci_trb *queued_deq_ptr;
896 * Sometimes the xHC can not process isochronous endpoint ring quickly
897 * enough, and it will miss some isoc tds on the ring and generate
898 * a Missed Service Error Event.
899 * Set skip flag when receive a Missed Service Error Event and
900 * process the missed tds on the endpoint ring.
903 /* Bandwidth checking storage */
904 struct xhci_bw_info bw_info;
905 struct list_head bw_endpoint_list;
908 enum xhci_overhead_type {
909 LS_OVERHEAD_TYPE = 0,
914 struct xhci_interval_bw {
915 unsigned int num_packets;
916 /* Sorted by max packet size.
917 * Head of the list is the greatest max packet size.
919 struct list_head endpoints;
920 /* How many endpoints of each speed are present. */
921 unsigned int overhead[3];
924 #define XHCI_MAX_INTERVAL 16
926 struct xhci_interval_bw_table {
927 unsigned int interval0_esit_payload;
928 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
929 /* Includes reserved bandwidth for async endpoints */
930 unsigned int bw_used;
931 unsigned int ss_bw_in;
932 unsigned int ss_bw_out;
936 struct xhci_virt_device {
937 struct usb_device *udev;
939 * Commands to the hardware are passed an "input context" that
940 * tells the hardware what to change in its data structures.
941 * The hardware will return changes in an "output context" that
942 * software must allocate for the hardware. We need to keep
943 * track of input and output contexts separately because
944 * these commands might fail and we don't trust the hardware.
946 struct xhci_container_ctx *out_ctx;
947 /* Used for addressing devices and configuration changes */
948 struct xhci_container_ctx *in_ctx;
949 /* Rings saved to ensure old alt settings can be re-instated */
950 struct xhci_ring **ring_cache;
951 int num_rings_cached;
952 #define XHCI_MAX_RINGS_CACHED 31
953 struct xhci_virt_ep eps[31];
954 struct completion cmd_completion;
957 struct xhci_interval_bw_table *bw_table;
958 struct xhci_tt_bw_info *tt_info;
959 /* The current max exit latency for the enabled USB3 link states. */
964 * For each roothub, keep track of the bandwidth information for each periodic
967 * If a high speed hub is attached to the roothub, each TT associated with that
968 * hub is a separate bandwidth domain. The interval information for the
969 * endpoints on the devices under that TT will appear in the TT structure.
971 struct xhci_root_port_bw_info {
972 struct list_head tts;
973 unsigned int num_active_tts;
974 struct xhci_interval_bw_table bw_table;
977 struct xhci_tt_bw_info {
978 struct list_head tt_list;
981 struct xhci_interval_bw_table bw_table;
987 * struct xhci_device_context_array
988 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
990 struct xhci_device_context_array {
991 /* 64-bit device addresses; we only write 32-bit addresses */
992 __le64 dev_context_ptrs[MAX_HC_SLOTS];
993 /* private xHCD pointers */
996 /* TODO: write function to set the 64-bit device DMA address */
998 * TODO: change this to be dynamically sized at HC mem init time since the HC
999 * might not be able to handle the maximum number of devices possible.
1003 struct xhci_transfer_event {
1004 /* 64-bit buffer address, or immediate data */
1006 __le32 transfer_len;
1007 /* This field is interpreted differently based on the type of TRB */
1011 /* Transfer event TRB length bit mask */
1013 #define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1015 /** Transfer Event bit fields **/
1016 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1018 /* Completion Code - only applicable for some types of TRBs */
1019 #define COMP_CODE_MASK (0xff << 24)
1020 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1021 #define COMP_SUCCESS 1
1022 /* Data Buffer Error */
1023 #define COMP_DB_ERR 2
1024 /* Babble Detected Error */
1025 #define COMP_BABBLE 3
1026 /* USB Transaction Error */
1027 #define COMP_TX_ERR 4
1028 /* TRB Error - some TRB field is invalid */
1029 #define COMP_TRB_ERR 5
1030 /* Stall Error - USB device is stalled */
1031 #define COMP_STALL 6
1032 /* Resource Error - HC doesn't have memory for that device configuration */
1033 #define COMP_ENOMEM 7
1034 /* Bandwidth Error - not enough room in schedule for this dev config */
1035 #define COMP_BW_ERR 8
1036 /* No Slots Available Error - HC ran out of device slots */
1037 #define COMP_ENOSLOTS 9
1038 /* Invalid Stream Type Error */
1039 #define COMP_STREAM_ERR 10
1040 /* Slot Not Enabled Error - doorbell rung for disabled device slot */
1041 #define COMP_EBADSLT 11
1042 /* Endpoint Not Enabled Error */
1043 #define COMP_EBADEP 12
1045 #define COMP_SHORT_TX 13
1046 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
1047 #define COMP_UNDERRUN 14
1048 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
1049 #define COMP_OVERRUN 15
1050 /* Virtual Function Event Ring Full Error */
1051 #define COMP_VF_FULL 16
1052 /* Parameter Error - Context parameter is invalid */
1053 #define COMP_EINVAL 17
1054 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
1055 #define COMP_BW_OVER 18
1056 /* Context State Error - illegal context state transition requested */
1057 #define COMP_CTX_STATE 19
1058 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
1059 #define COMP_PING_ERR 20
1060 /* Event Ring is full */
1061 #define COMP_ER_FULL 21
1062 /* Incompatible Device Error */
1063 #define COMP_DEV_ERR 22
1064 /* Missed Service Error - HC couldn't service an isoc ep within interval */
1065 #define COMP_MISSED_INT 23
1066 /* Successfully stopped command ring */
1067 #define COMP_CMD_STOP 24
1068 /* Successfully aborted current command and stopped command ring */
1069 #define COMP_CMD_ABORT 25
1070 /* Stopped - transfer was terminated by a stop endpoint command */
1071 #define COMP_STOP 26
1072 /* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */
1073 #define COMP_STOP_INVAL 27
1074 /* Control Abort Error - Debug Capability - control pipe aborted */
1075 #define COMP_DBG_ABORT 28
1076 /* Max Exit Latency Too Large Error */
1077 #define COMP_MEL_ERR 29
1078 /* TRB type 30 reserved */
1079 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
1080 #define COMP_BUFF_OVER 31
1081 /* Event Lost Error - xHC has an "internal event overrun condition" */
1082 #define COMP_ISSUES 32
1083 /* Undefined Error - reported when other error codes don't apply */
1084 #define COMP_UNKNOWN 33
1085 /* Invalid Stream ID Error */
1086 #define COMP_STRID_ERR 34
1087 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
1088 #define COMP_2ND_BW_ERR 35
1089 /* Split Transaction Error */
1090 #define COMP_SPLIT_ERR 36
1092 struct xhci_link_trb {
1093 /* 64-bit segment pointer*/
1099 /* control bitfields */
1100 #define LINK_TOGGLE (0x1<<1)
1102 /* Command completion event TRB */
1103 struct xhci_event_cmd {
1104 /* Pointer to command TRB, or the value passed by the event data trb */
1110 /* flags bitmasks */
1112 /* Address device - disable SetAddress */
1113 #define TRB_BSR (1<<9)
1114 enum xhci_setup_dev {
1116 SETUP_CONTEXT_ADDRESS,
1119 /* bits 16:23 are the virtual function ID */
1120 /* bits 24:31 are the slot ID */
1121 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1122 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1124 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1125 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1126 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1128 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1129 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1130 #define LAST_EP_INDEX 30
1132 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1133 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1134 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1135 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1138 /* Port Status Change Event TRB fields */
1139 /* Port ID - bits 31:24 */
1140 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1142 /* Normal TRB fields */
1143 /* transfer_len bitmasks - bits 0:16 */
1144 #define TRB_LEN(p) ((p) & 0x1ffff)
1145 /* Interrupter Target - which MSI-X vector to target the completion event at */
1146 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1147 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1148 #define TRB_TBC(p) (((p) & 0x3) << 7)
1149 #define TRB_TLBPC(p) (((p) & 0xf) << 16)
1151 /* Cycle bit - indicates TRB ownership by HC or HCD */
1152 #define TRB_CYCLE (1<<0)
1154 * Force next event data TRB to be evaluated before task switch.
1155 * Used to pass OS data back after a TD completes.
1157 #define TRB_ENT (1<<1)
1158 /* Interrupt on short packet */
1159 #define TRB_ISP (1<<2)
1160 /* Set PCIe no snoop attribute */
1161 #define TRB_NO_SNOOP (1<<3)
1162 /* Chain multiple TRBs into a TD */
1163 #define TRB_CHAIN (1<<4)
1164 /* Interrupt on completion */
1165 #define TRB_IOC (1<<5)
1166 /* The buffer pointer contains immediate data */
1167 #define TRB_IDT (1<<6)
1169 /* Block Event Interrupt */
1170 #define TRB_BEI (1<<9)
1172 /* Control transfer TRB specific fields */
1173 #define TRB_DIR_IN (1<<16)
1174 #define TRB_TX_TYPE(p) ((p) << 16)
1175 #define TRB_DATA_OUT 2
1176 #define TRB_DATA_IN 3
1178 /* Isochronous TRB specific fields */
1179 #define TRB_SIA (1<<31)
1181 struct xhci_generic_trb {
1186 struct xhci_link_trb link;
1187 struct xhci_transfer_event trans_event;
1188 struct xhci_event_cmd event_cmd;
1189 struct xhci_generic_trb generic;
1193 #define TRB_TYPE_BITMASK (0xfc00)
1194 #define TRB_TYPE(p) ((p) << 10)
1195 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1197 /* bulk, interrupt, isoc scatter/gather, and control data stage */
1198 #define TRB_NORMAL 1
1199 /* setup stage for control transfers */
1201 /* data stage for control transfers */
1203 /* status stage for control transfers */
1204 #define TRB_STATUS 4
1205 /* isoc transfers */
1207 /* TRB for linking ring segments */
1209 #define TRB_EVENT_DATA 7
1210 /* Transfer Ring No-op (not for the command ring) */
1211 #define TRB_TR_NOOP 8
1213 /* Enable Slot Command */
1214 #define TRB_ENABLE_SLOT 9
1215 /* Disable Slot Command */
1216 #define TRB_DISABLE_SLOT 10
1217 /* Address Device Command */
1218 #define TRB_ADDR_DEV 11
1219 /* Configure Endpoint Command */
1220 #define TRB_CONFIG_EP 12
1221 /* Evaluate Context Command */
1222 #define TRB_EVAL_CONTEXT 13
1223 /* Reset Endpoint Command */
1224 #define TRB_RESET_EP 14
1225 /* Stop Transfer Ring Command */
1226 #define TRB_STOP_RING 15
1227 /* Set Transfer Ring Dequeue Pointer Command */
1228 #define TRB_SET_DEQ 16
1229 /* Reset Device Command */
1230 #define TRB_RESET_DEV 17
1231 /* Force Event Command (opt) */
1232 #define TRB_FORCE_EVENT 18
1233 /* Negotiate Bandwidth Command (opt) */
1234 #define TRB_NEG_BANDWIDTH 19
1235 /* Set Latency Tolerance Value Command (opt) */
1236 #define TRB_SET_LT 20
1237 /* Get port bandwidth Command */
1238 #define TRB_GET_BW 21
1239 /* Force Header Command - generate a transaction or link management packet */
1240 #define TRB_FORCE_HEADER 22
1241 /* No-op Command - not for transfer rings */
1242 #define TRB_CMD_NOOP 23
1243 /* TRB IDs 24-31 reserved */
1245 /* Transfer Event */
1246 #define TRB_TRANSFER 32
1247 /* Command Completion Event */
1248 #define TRB_COMPLETION 33
1249 /* Port Status Change Event */
1250 #define TRB_PORT_STATUS 34
1251 /* Bandwidth Request Event (opt) */
1252 #define TRB_BANDWIDTH_EVENT 35
1253 /* Doorbell Event (opt) */
1254 #define TRB_DOORBELL 36
1255 /* Host Controller Event */
1256 #define TRB_HC_EVENT 37
1257 /* Device Notification Event - device sent function wake notification */
1258 #define TRB_DEV_NOTE 38
1259 /* MFINDEX Wrap Event - microframe counter wrapped */
1260 #define TRB_MFINDEX_WRAP 39
1261 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1263 /* Nec vendor-specific command completion event. */
1264 #define TRB_NEC_CMD_COMP 48
1265 /* Get NEC firmware revision. */
1266 #define TRB_NEC_GET_FW 49
1268 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1269 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1270 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1271 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1272 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1273 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1275 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1276 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1279 * TRBS_PER_SEGMENT must be a multiple of 4,
1280 * since the command ring is 64-byte aligned.
1281 * It must also be greater than 16.
1283 #define TRBS_PER_SEGMENT 256
1284 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1285 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1286 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1287 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1288 /* TRB buffer pointers can't cross 64KB boundaries */
1289 #define TRB_MAX_BUFF_SHIFT 16
1290 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1292 struct xhci_segment {
1293 union xhci_trb *trbs;
1294 /* private to HCD */
1295 struct xhci_segment *next;
1300 struct list_head td_list;
1301 struct list_head cancelled_td_list;
1303 struct xhci_segment *start_seg;
1304 union xhci_trb *first_trb;
1305 union xhci_trb *last_trb;
1306 /* actual_length of the URB has already been set */
1307 bool urb_length_set;
1310 /* xHCI command default timeout value */
1311 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1313 /* command descriptor */
1315 struct xhci_command *command;
1316 union xhci_trb *cmd_trb;
1319 struct xhci_dequeue_state {
1320 struct xhci_segment *new_deq_seg;
1321 union xhci_trb *new_deq_ptr;
1322 int new_cycle_state;
1325 enum xhci_ring_type {
1336 struct xhci_segment *first_seg;
1337 struct xhci_segment *last_seg;
1338 union xhci_trb *enqueue;
1339 struct xhci_segment *enq_seg;
1340 unsigned int enq_updates;
1341 union xhci_trb *dequeue;
1342 struct xhci_segment *deq_seg;
1343 unsigned int deq_updates;
1344 struct list_head td_list;
1346 * Write the cycle state into the TRB cycle field to give ownership of
1347 * the TRB to the host controller (if we are the producer), or to check
1348 * if we own the TRB (if we are the consumer). See section 4.9.1.
1351 unsigned int stream_id;
1352 unsigned int num_segs;
1353 unsigned int num_trbs_free;
1354 unsigned int num_trbs_free_temp;
1355 enum xhci_ring_type type;
1356 bool last_td_was_short;
1357 struct radix_tree_root *trb_address_map;
1360 struct xhci_erst_entry {
1361 /* 64-bit event ring segment address */
1369 struct xhci_erst_entry *entries;
1370 unsigned int num_entries;
1371 /* xhci->event_ring keeps track of segment dma addresses */
1372 dma_addr_t erst_dma_addr;
1373 /* Num entries the ERST can contain */
1374 unsigned int erst_size;
1377 struct xhci_scratchpad {
1381 dma_addr_t *sp_dma_buffers;
1387 struct xhci_td *td[0];
1391 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1392 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1393 * meaning 64 ring segments.
1394 * Initial allocated size of the ERST, in number of entries */
1395 #define ERST_NUM_SEGS 1
1396 /* Initial allocated size of the ERST, in number of entries */
1397 #define ERST_SIZE 64
1398 /* Initial number of event segment rings allocated */
1399 #define ERST_ENTRIES 1
1400 /* Poll every 60 seconds */
1401 #define POLL_TIMEOUT 60
1402 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1403 #define XHCI_STOP_EP_CMD_TIMEOUT 5
1404 /* XXX: Make these module parameters */
1421 struct list_head list;
1424 struct xhci_bus_state {
1425 unsigned long bus_suspended;
1426 unsigned long next_statechange;
1428 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1429 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1431 u32 suspended_ports;
1432 u32 port_remote_wakeup;
1433 unsigned long resume_done[USB_MAXCHILDREN];
1434 /* which ports have started to resume */
1435 unsigned long resuming_ports;
1436 /* Which ports are waiting on RExit to U0 transition. */
1437 unsigned long rexit_ports;
1438 struct completion rexit_done[USB_MAXCHILDREN];
1443 * It can take up to 20 ms to transition from RExit to U0 on the
1444 * Intel Lynx Point LP xHCI host.
1446 #define XHCI_MAX_REXIT_TIMEOUT_MS 20
1448 static inline unsigned int hcd_index(struct usb_hcd *hcd)
1450 if (hcd->speed >= HCD_USB3)
1456 /* There is one xhci_hcd structure per controller */
1458 struct usb_hcd *main_hcd;
1459 struct usb_hcd *shared_hcd;
1460 /* glue to PCI and HCD framework */
1461 struct xhci_cap_regs __iomem *cap_regs;
1462 struct xhci_op_regs __iomem *op_regs;
1463 struct xhci_run_regs __iomem *run_regs;
1464 struct xhci_doorbell_array __iomem *dba;
1465 /* Our HCD's current interrupter register set */
1466 struct xhci_intr_reg __iomem *ir_set;
1468 /* Cached register copies of read-only HC data */
1476 /* packed release number */
1480 u8 max_interrupters;
1485 /* 4KB min, 128MB max */
1487 /* Valid values are 12 to 20, inclusive */
1491 struct msix_entry *msix_entries;
1492 /* optional clock */
1494 /* data structures */
1495 struct xhci_device_context_array *dcbaa;
1496 struct xhci_ring *cmd_ring;
1497 unsigned int cmd_ring_state;
1498 #define CMD_RING_STATE_RUNNING (1 << 0)
1499 #define CMD_RING_STATE_ABORTED (1 << 1)
1500 #define CMD_RING_STATE_STOPPED (1 << 2)
1501 struct list_head cmd_list;
1502 unsigned int cmd_ring_reserved_trbs;
1503 struct timer_list cmd_timer;
1504 struct xhci_command *current_cmd;
1505 struct xhci_ring *event_ring;
1506 struct xhci_erst erst;
1508 struct xhci_scratchpad *scratchpad;
1509 /* Store LPM test failed devices' information */
1510 struct list_head lpm_failed_devs;
1512 /* slot enabling and address device helpers */
1513 struct completion addr_dev;
1515 /* For USB 3.0 LPM enable/disable. */
1516 struct xhci_command *lpm_command;
1517 /* Internal mirror of the HW's dcbaa */
1518 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1519 /* For keeping track of bandwidth domains per roothub. */
1520 struct xhci_root_port_bw_info *rh_bw;
1523 struct dma_pool *device_pool;
1524 struct dma_pool *segment_pool;
1525 struct dma_pool *small_streams_pool;
1526 struct dma_pool *medium_streams_pool;
1528 /* Host controller watchdog timer structures */
1529 unsigned int xhc_state;
1533 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1535 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1536 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1537 * that sees this status (other than the timer that set it) should stop touching
1538 * hardware immediately. Interrupt handlers should return immediately when
1539 * they see this status (any time they drop and re-acquire xhci->lock).
1540 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1541 * putting the TD on the canceled list, etc.
1543 * There are no reports of xHCI host controllers that display this issue.
1545 #define XHCI_STATE_DYING (1 << 0)
1546 #define XHCI_STATE_HALTED (1 << 1)
1549 unsigned int quirks;
1550 #define XHCI_LINK_TRB_QUIRK (1 << 0)
1551 #define XHCI_RESET_EP_QUIRK (1 << 1)
1552 #define XHCI_NEC_HOST (1 << 2)
1553 #define XHCI_AMD_PLL_FIX (1 << 3)
1554 #define XHCI_SPURIOUS_SUCCESS (1 << 4)
1556 * Certain Intel host controllers have a limit to the number of endpoint
1557 * contexts they can handle. Ideally, they would signal that they can't handle
1558 * anymore endpoint contexts by returning a Resource Error for the Configure
1559 * Endpoint command, but they don't. Instead they expect software to keep track
1560 * of the number of active endpoints for them, across configure endpoint
1561 * commands, reset device commands, disable slot commands, and address device
1564 #define XHCI_EP_LIMIT_QUIRK (1 << 5)
1565 #define XHCI_BROKEN_MSI (1 << 6)
1566 #define XHCI_RESET_ON_RESUME (1 << 7)
1567 #define XHCI_SW_BW_CHECKING (1 << 8)
1568 #define XHCI_AMD_0x96_HOST (1 << 9)
1569 #define XHCI_TRUST_TX_LENGTH (1 << 10)
1570 #define XHCI_LPM_SUPPORT (1 << 11)
1571 #define XHCI_INTEL_HOST (1 << 12)
1572 #define XHCI_SPURIOUS_REBOOT (1 << 13)
1573 #define XHCI_COMP_MODE_QUIRK (1 << 14)
1574 #define XHCI_AVOID_BEI (1 << 15)
1575 #define XHCI_PLAT (1 << 16)
1576 #define XHCI_SLOW_SUSPEND (1 << 17)
1577 #define XHCI_SPURIOUS_WAKEUP (1 << 18)
1578 /* For controllers with a broken beyond repair streams implementation */
1579 #define XHCI_BROKEN_STREAMS (1 << 19)
1580 #define XHCI_PME_STUCK_QUIRK (1 << 20)
1581 #define XHCI_MISSING_CAS (1 << 24)
1582 #define XHCI_U2_DISABLE_WAKE (1 << 27)
1583 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL (1 << 28)
1584 #define XHCI_SUSPEND_DELAY (1 << 30)
1585 #define XHCI_SNPS_BROKEN_SUSPEND BIT(31)
1586 unsigned int num_active_eps;
1587 unsigned int limit_active_eps;
1588 /* There are two roothubs to keep track of bus suspend info for */
1589 struct xhci_bus_state bus_state[2];
1590 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
1592 /* Array of pointers to USB 3.0 PORTSC registers */
1593 __le32 __iomem **usb3_ports;
1594 unsigned int num_usb3_ports;
1595 /* Array of pointers to USB 2.0 PORTSC registers */
1596 __le32 __iomem **usb2_ports;
1597 unsigned int num_usb2_ports;
1598 /* support xHCI 0.96 spec USB2 software LPM */
1599 unsigned sw_lpm_support:1;
1600 /* support xHCI 1.0 spec USB2 hardware LPM */
1601 unsigned hw_lpm_support:1;
1602 /* Broken Suspend flag for SNPS Suspend resume issue */
1603 unsigned broken_suspend:1;
1604 /* cached usb2 extened protocol capabilites */
1606 unsigned int num_ext_caps;
1607 /* Compliance Mode Recovery Data */
1608 struct timer_list comp_mode_recovery_timer;
1610 /* Compliance Mode Timer Triggered every 2 seconds */
1611 #define COMP_MODE_RCVRY_MSECS 2000
1614 /* convert between an HCD pointer and the corresponding EHCI_HCD */
1615 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1617 return *((struct xhci_hcd **) (hcd->hcd_priv));
1620 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1622 return xhci->main_hcd;
1625 #define xhci_dbg(xhci, fmt, args...) \
1626 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1627 #define xhci_err(xhci, fmt, args...) \
1628 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1629 #define xhci_warn(xhci, fmt, args...) \
1630 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1631 #define xhci_warn_ratelimited(xhci, fmt, args...) \
1632 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1635 * Registers should always be accessed with double word or quad word accesses.
1637 * Some xHCI implementations may support 64-bit address pointers. Registers
1638 * with 64-bit address pointers should be written to with dword accesses by
1639 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1640 * xHCI implementations that do not support 64-bit address pointers will ignore
1641 * the high dword, and write order is irrelevant.
1643 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1644 __le64 __iomem *regs)
1646 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1647 u64 val_lo = readl(ptr);
1648 u64 val_hi = readl(ptr + 1);
1649 return val_lo + (val_hi << 32);
1651 static inline void xhci_write_64(struct xhci_hcd *xhci,
1652 const u64 val, __le64 __iomem *regs)
1654 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1655 u32 val_lo = lower_32_bits(val);
1656 u32 val_hi = upper_32_bits(val);
1658 writel(val_lo, ptr);
1659 writel(val_hi, ptr + 1);
1662 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1664 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1667 /* xHCI debugging */
1668 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
1669 void xhci_print_registers(struct xhci_hcd *xhci);
1670 void xhci_dbg_regs(struct xhci_hcd *xhci);
1671 void xhci_print_run_regs(struct xhci_hcd *xhci);
1672 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1673 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
1674 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
1675 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1676 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1677 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1678 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
1679 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
1680 char *xhci_get_slot_state(struct xhci_hcd *xhci,
1681 struct xhci_container_ctx *ctx);
1682 void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
1683 unsigned int slot_id, unsigned int ep_index,
1684 struct xhci_virt_ep *ep);
1685 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1686 const char *fmt, ...);
1688 /* xHCI memory management */
1689 void xhci_mem_cleanup(struct xhci_hcd *xhci);
1690 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1691 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1692 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1693 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1694 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1695 struct usb_device *udev);
1696 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1697 unsigned int xhci_get_endpoint_address(unsigned int ep_index);
1698 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
1699 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1700 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1701 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1702 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
1703 struct xhci_bw_info *ep_bw,
1704 struct xhci_interval_bw_table *bw_table,
1705 struct usb_device *udev,
1706 struct xhci_virt_ep *virt_ep,
1707 struct xhci_tt_bw_info *tt_info);
1708 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1709 struct xhci_virt_device *virt_dev,
1710 int old_active_eps);
1711 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1712 void xhci_update_bw_info(struct xhci_hcd *xhci,
1713 struct xhci_container_ctx *in_ctx,
1714 struct xhci_input_control_ctx *ctrl_ctx,
1715 struct xhci_virt_device *virt_dev);
1716 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1717 struct xhci_container_ctx *in_ctx,
1718 struct xhci_container_ctx *out_ctx,
1719 unsigned int ep_index);
1720 void xhci_slot_copy(struct xhci_hcd *xhci,
1721 struct xhci_container_ctx *in_ctx,
1722 struct xhci_container_ctx *out_ctx);
1723 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1724 struct usb_device *udev, struct usb_host_endpoint *ep,
1726 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1727 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1728 unsigned int num_trbs, gfp_t flags);
1729 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
1730 struct xhci_virt_device *virt_dev,
1731 unsigned int ep_index);
1732 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1733 unsigned int num_stream_ctxs,
1734 unsigned int num_streams, gfp_t flags);
1735 void xhci_free_stream_info(struct xhci_hcd *xhci,
1736 struct xhci_stream_info *stream_info);
1737 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1738 struct xhci_ep_ctx *ep_ctx,
1739 struct xhci_stream_info *stream_info);
1740 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
1741 struct xhci_ep_ctx *ep_ctx,
1742 struct xhci_virt_ep *ep);
1743 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1744 struct xhci_virt_device *virt_dev, bool drop_control_ep);
1745 struct xhci_ring *xhci_dma_to_transfer_ring(
1746 struct xhci_virt_ep *ep,
1748 struct xhci_ring *xhci_stream_id_to_ring(
1749 struct xhci_virt_device *dev,
1750 unsigned int ep_index,
1751 unsigned int stream_id);
1752 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1753 bool allocate_in_ctx, bool allocate_completion,
1755 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv);
1756 void xhci_free_command(struct xhci_hcd *xhci,
1757 struct xhci_command *command);
1761 int xhci_register_pci(void);
1762 void xhci_unregister_pci(void);
1764 static inline int xhci_register_pci(void) { return 0; }
1765 static inline void xhci_unregister_pci(void) {}
1768 #if IS_ENABLED(CONFIG_USB_XHCI_PLATFORM)
1769 int xhci_register_plat(void);
1770 void xhci_unregister_plat(void);
1772 static inline int xhci_register_plat(void)
1774 static inline void xhci_unregister_plat(void)
1778 /* xHCI host controller glue */
1779 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
1780 int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr,
1781 u32 mask, u32 done, int usec);
1782 void xhci_quiesce(struct xhci_hcd *xhci);
1783 int xhci_halt(struct xhci_hcd *xhci);
1784 int xhci_reset(struct xhci_hcd *xhci);
1785 int xhci_init(struct usb_hcd *hcd);
1786 int xhci_run(struct usb_hcd *hcd);
1787 void xhci_stop(struct usb_hcd *hcd);
1788 void xhci_shutdown(struct usb_hcd *hcd);
1789 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
1792 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
1793 int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
1795 #define xhci_suspend NULL
1796 #define xhci_resume NULL
1799 int xhci_get_frame(struct usb_hcd *hcd);
1800 irqreturn_t xhci_irq(struct usb_hcd *hcd);
1801 irqreturn_t xhci_msi_irq(int irq, void *hcd);
1802 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1803 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1804 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1805 struct xhci_virt_device *virt_dev,
1806 struct usb_device *hdev,
1807 struct usb_tt *tt, gfp_t mem_flags);
1808 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
1809 struct usb_host_endpoint **eps, unsigned int num_eps,
1810 unsigned int num_streams, gfp_t mem_flags);
1811 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1812 struct usb_host_endpoint **eps, unsigned int num_eps,
1814 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
1815 int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev);
1816 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev);
1817 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
1818 struct usb_device *udev, int enable);
1819 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1820 struct usb_tt *tt, gfp_t mem_flags);
1821 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1822 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
1823 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1824 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1825 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
1826 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
1827 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1828 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1830 /* xHCI ring, segment, TRB, and TD functions */
1831 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1832 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1833 union xhci_trb *start_trb, union xhci_trb *end_trb,
1834 dma_addr_t suspect_dma);
1835 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1836 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1837 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
1838 u32 trb_type, u32 slot_id);
1839 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1840 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
1841 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
1842 u32 field1, u32 field2, u32 field3, u32 field4);
1843 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
1844 int slot_id, unsigned int ep_index, int suspend);
1845 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1846 int slot_id, unsigned int ep_index);
1847 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1848 int slot_id, unsigned int ep_index);
1849 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1850 int slot_id, unsigned int ep_index);
1851 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1852 struct urb *urb, int slot_id, unsigned int ep_index);
1853 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
1854 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
1855 bool command_must_succeed);
1856 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
1857 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
1858 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
1859 int slot_id, unsigned int ep_index);
1860 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1862 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1863 unsigned int slot_id, unsigned int ep_index,
1864 unsigned int stream_id, struct xhci_td *cur_td,
1865 struct xhci_dequeue_state *state);
1866 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
1867 struct xhci_command *cmd,
1868 unsigned int slot_id, unsigned int ep_index,
1869 unsigned int stream_id,
1870 struct xhci_dequeue_state *deq_state);
1871 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
1872 struct usb_device *udev, unsigned int ep_index);
1873 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1874 unsigned int slot_id, unsigned int ep_index,
1875 struct xhci_dequeue_state *deq_state);
1876 void xhci_stop_endpoint_command_watchdog(unsigned long arg);
1877 void xhci_handle_command_timeout(unsigned long data);
1879 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1880 unsigned int ep_index, unsigned int stream_id);
1881 void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
1883 /* xHCI roothub code */
1884 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1885 int port_id, u32 link_state);
1886 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
1887 struct usb_device *udev, enum usb3_link_state state);
1888 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
1889 struct usb_device *udev, enum usb3_link_state state);
1890 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1891 int port_id, u32 port_bit);
1892 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1893 char *buf, u16 wLength);
1894 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1895 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
1898 int xhci_bus_suspend(struct usb_hcd *hcd);
1899 int xhci_bus_resume(struct usb_hcd *hcd);
1901 #define xhci_bus_suspend NULL
1902 #define xhci_bus_resume NULL
1903 #endif /* CONFIG_PM */
1905 u32 xhci_port_state_to_neutral(u32 state);
1906 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
1908 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1911 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1912 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1913 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1916 bool xhci_compliance_mode_recovery_timer_quirk_check(void);
1918 #endif /* __LINUX_XHCI_HCD_H */