2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/irq.h>
25 #include <linux/log2.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/slab.h>
29 #include <linux/dmi.h>
30 #include <linux/dma-mapping.h>
33 #include "xhci-trace.h"
36 #define DRIVER_AUTHOR "Sarah Sharp"
37 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
39 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
41 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
42 static int link_quirk;
43 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
44 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
46 static unsigned int quirks;
47 module_param(quirks, uint, S_IRUGO);
48 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
50 /* TODO: copied from ehci-hcd.c - can this be refactored? */
52 * xhci_handshake - spin reading hc until handshake completes or fails
53 * @ptr: address of hc register to be read
54 * @mask: bits to look at in result of read
55 * @done: value of those bits when handshake succeeds
56 * @usec: timeout in microseconds
58 * Returns negative errno, or zero on success
60 * Success happens when the "mask" bits have the specified value (hardware
61 * handshake done). There are two failure modes: "usec" have passed (major
62 * hardware flakeout), or the register reads as all-ones (hardware removed).
64 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
70 if (result == ~(u32)0) /* card removed */
82 * Disable interrupts and begin the xHCI halting process.
84 void xhci_quiesce(struct xhci_hcd *xhci)
91 halted = readl(&xhci->op_regs->status) & STS_HALT;
95 cmd = readl(&xhci->op_regs->command);
97 writel(cmd, &xhci->op_regs->command);
101 * Force HC into halt state.
103 * Disable any IRQs and clear the run/stop bit.
104 * HC will complete any current and actively pipelined transactions, and
105 * should halt within 16 ms of the run/stop bit being cleared.
106 * Read HC Halted bit in the status register to see when the HC is finished.
108 int xhci_halt(struct xhci_hcd *xhci)
111 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
114 ret = xhci_handshake(&xhci->op_regs->status,
115 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
117 xhci->xhc_state |= XHCI_STATE_HALTED;
118 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
120 xhci_warn(xhci, "Host not halted after %u microseconds.\n",
126 * Set the run bit and wait for the host to be running.
128 static int xhci_start(struct xhci_hcd *xhci)
133 temp = readl(&xhci->op_regs->command);
135 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
137 writel(temp, &xhci->op_regs->command);
140 * Wait for the HCHalted Status bit to be 0 to indicate the host is
143 ret = xhci_handshake(&xhci->op_regs->status,
144 STS_HALT, 0, XHCI_MAX_HALT_USEC);
145 if (ret == -ETIMEDOUT)
146 xhci_err(xhci, "Host took too long to start, "
147 "waited %u microseconds.\n",
150 /* clear state flags. Including dying, halted or removing */
159 * This resets pipelines, timers, counters, state machines, etc.
160 * Transactions will be terminated immediately, and operational registers
161 * will be set to their defaults.
163 int xhci_reset(struct xhci_hcd *xhci)
169 state = readl(&xhci->op_regs->status);
170 if ((state & STS_HALT) == 0) {
171 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
175 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
176 command = readl(&xhci->op_regs->command);
177 command |= CMD_RESET;
178 writel(command, &xhci->op_regs->command);
180 /* Existing Intel xHCI controllers require a delay of 1 mS,
181 * after setting the CMD_RESET bit, and before accessing any
182 * HC registers. This allows the HC to complete the
183 * reset operation and be ready for HC register access.
184 * Without this delay, the subsequent HC register access,
185 * may result in a system hang very rarely.
187 if (xhci->quirks & XHCI_INTEL_HOST)
190 ret = xhci_handshake(&xhci->op_regs->command,
191 CMD_RESET, 0, 10 * 1000 * 1000);
195 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
196 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
198 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
199 "Wait for controller to be ready for doorbell rings");
201 * xHCI cannot write to any doorbells or operational registers other
202 * than status until the "Controller Not Ready" flag is cleared.
204 ret = xhci_handshake(&xhci->op_regs->status,
205 STS_CNR, 0, 10 * 1000 * 1000);
207 for (i = 0; i < 2; ++i) {
208 xhci->bus_state[i].port_c_suspend = 0;
209 xhci->bus_state[i].suspended_ports = 0;
210 xhci->bus_state[i].resuming_ports = 0;
217 static int xhci_free_msi(struct xhci_hcd *xhci)
221 if (!xhci->msix_entries)
224 for (i = 0; i < xhci->msix_count; i++)
225 if (xhci->msix_entries[i].vector)
226 free_irq(xhci->msix_entries[i].vector,
234 static int xhci_setup_msi(struct xhci_hcd *xhci)
237 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
239 ret = pci_enable_msi(pdev);
241 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
242 "failed to allocate MSI entry");
246 ret = request_irq(pdev->irq, xhci_msi_irq,
247 0, "xhci_hcd", xhci_to_hcd(xhci));
249 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
250 "disable MSI interrupt");
251 pci_disable_msi(pdev);
259 * free all IRQs request
261 static void xhci_free_irq(struct xhci_hcd *xhci)
263 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
266 /* return if using legacy interrupt */
267 if (xhci_to_hcd(xhci)->irq > 0)
270 ret = xhci_free_msi(xhci);
274 free_irq(pdev->irq, xhci_to_hcd(xhci));
282 static int xhci_setup_msix(struct xhci_hcd *xhci)
285 struct usb_hcd *hcd = xhci_to_hcd(xhci);
286 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
289 * calculate number of msi-x vectors supported.
290 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
291 * with max number of interrupters based on the xhci HCSPARAMS1.
292 * - num_online_cpus: maximum msi-x vectors per CPUs core.
293 * Add additional 1 vector to ensure always available interrupt.
295 xhci->msix_count = min(num_online_cpus() + 1,
296 HCS_MAX_INTRS(xhci->hcs_params1));
299 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
301 if (!xhci->msix_entries)
304 for (i = 0; i < xhci->msix_count; i++) {
305 xhci->msix_entries[i].entry = i;
306 xhci->msix_entries[i].vector = 0;
309 ret = pci_enable_msix_exact(pdev, xhci->msix_entries, xhci->msix_count);
311 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
312 "Failed to enable MSI-X");
316 for (i = 0; i < xhci->msix_count; i++) {
317 ret = request_irq(xhci->msix_entries[i].vector,
319 0, "xhci_hcd", xhci_to_hcd(xhci));
324 hcd->msix_enabled = 1;
328 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
330 pci_disable_msix(pdev);
332 kfree(xhci->msix_entries);
333 xhci->msix_entries = NULL;
337 /* Free any IRQs and disable MSI-X */
338 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
340 struct usb_hcd *hcd = xhci_to_hcd(xhci);
341 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
343 if (xhci->quirks & XHCI_PLAT)
348 if (xhci->msix_entries) {
349 pci_disable_msix(pdev);
350 kfree(xhci->msix_entries);
351 xhci->msix_entries = NULL;
353 pci_disable_msi(pdev);
356 hcd->msix_enabled = 0;
360 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
364 if (xhci->msix_entries) {
365 for (i = 0; i < xhci->msix_count; i++)
366 synchronize_irq(xhci->msix_entries[i].vector);
370 static int xhci_try_enable_msi(struct usb_hcd *hcd)
372 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
373 struct pci_dev *pdev;
376 /* The xhci platform device has set up IRQs through usb_add_hcd. */
377 if (xhci->quirks & XHCI_PLAT)
380 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
382 * Some Fresco Logic host controllers advertise MSI, but fail to
383 * generate interrupts. Don't even try to enable MSI.
385 if (xhci->quirks & XHCI_BROKEN_MSI)
388 /* unregister the legacy interrupt */
390 free_irq(hcd->irq, hcd);
393 ret = xhci_setup_msix(xhci);
395 /* fall back to msi*/
396 ret = xhci_setup_msi(xhci);
399 /* hcd->irq is 0, we have MSI */
403 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
408 if (!strlen(hcd->irq_descr))
409 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
410 hcd->driver->description, hcd->self.busnum);
412 /* fall back to legacy interrupt*/
413 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
414 hcd->irq_descr, hcd);
416 xhci_err(xhci, "request interrupt %d failed\n",
420 hcd->irq = pdev->irq;
426 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
431 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
435 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
441 static void compliance_mode_recovery(unsigned long arg)
443 struct xhci_hcd *xhci;
448 xhci = (struct xhci_hcd *)arg;
450 for (i = 0; i < xhci->num_usb3_ports; i++) {
451 temp = readl(xhci->usb3_ports[i]);
452 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
454 * Compliance Mode Detected. Letting USB Core
455 * handle the Warm Reset
457 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
458 "Compliance mode detected->port %d",
460 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
461 "Attempting compliance mode recovery");
462 hcd = xhci->shared_hcd;
464 if (hcd->state == HC_STATE_SUSPENDED)
465 usb_hcd_resume_root_hub(hcd);
467 usb_hcd_poll_rh_status(hcd);
471 if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
472 mod_timer(&xhci->comp_mode_recovery_timer,
473 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
477 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
478 * that causes ports behind that hardware to enter compliance mode sometimes.
479 * The quirk creates a timer that polls every 2 seconds the link state of
480 * each host controller's port and recovers it by issuing a Warm reset
481 * if Compliance mode is detected, otherwise the port will become "dead" (no
482 * device connections or disconnections will be detected anymore). Becasue no
483 * status event is generated when entering compliance mode (per xhci spec),
484 * this quirk is needed on systems that have the failing hardware installed.
486 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
488 xhci->port_status_u0 = 0;
489 setup_timer(&xhci->comp_mode_recovery_timer,
490 compliance_mode_recovery, (unsigned long)xhci);
491 xhci->comp_mode_recovery_timer.expires = jiffies +
492 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
494 add_timer(&xhci->comp_mode_recovery_timer);
495 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
496 "Compliance mode recovery timer initialized");
500 * This function identifies the systems that have installed the SN65LVPE502CP
501 * USB3.0 re-driver and that need the Compliance Mode Quirk.
503 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
505 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
507 const char *dmi_product_name, *dmi_sys_vendor;
509 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
510 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
511 if (!dmi_product_name || !dmi_sys_vendor)
514 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
517 if (strstr(dmi_product_name, "Z420") ||
518 strstr(dmi_product_name, "Z620") ||
519 strstr(dmi_product_name, "Z820") ||
520 strstr(dmi_product_name, "Z1 Workstation"))
526 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
528 return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
533 * Initialize memory for HCD and xHC (one-time init).
535 * Program the PAGESIZE register, initialize the device context array, create
536 * device contexts (?), set up a command ring segment (or two?), create event
537 * ring (one for now).
539 int xhci_init(struct usb_hcd *hcd)
541 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
544 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
545 spin_lock_init(&xhci->lock);
546 if (xhci->hci_version == 0x95 && link_quirk) {
547 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
548 "QUIRK: Not clearing Link TRB chain bits.");
549 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
551 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
552 "xHCI doesn't need link TRB QUIRK");
554 retval = xhci_mem_init(xhci, GFP_KERNEL);
555 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
557 /* Initializing Compliance Mode Recovery Data If Needed */
558 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
559 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
560 compliance_mode_recovery_timer_init(xhci);
566 /*-------------------------------------------------------------------------*/
569 static int xhci_run_finished(struct xhci_hcd *xhci)
571 if (xhci_start(xhci)) {
575 xhci->shared_hcd->state = HC_STATE_RUNNING;
576 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
578 if (xhci->quirks & XHCI_NEC_HOST)
579 xhci_ring_cmd_db(xhci);
581 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
582 "Finished xhci_run for USB3 roothub");
587 * Start the HC after it was halted.
589 * This function is called by the USB core when the HC driver is added.
590 * Its opposite is xhci_stop().
592 * xhci_init() must be called once before this function can be called.
593 * Reset the HC, enable device slot contexts, program DCBAAP, and
594 * set command ring pointer and event ring pointer.
596 * Setup MSI-X vectors and enable interrupts.
598 int xhci_run(struct usb_hcd *hcd)
603 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
605 /* Start the xHCI host controller running only after the USB 2.0 roothub
609 hcd->uses_new_polling = 1;
610 if (!usb_hcd_is_primary_hcd(hcd))
611 return xhci_run_finished(xhci);
613 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
615 ret = xhci_try_enable_msi(hcd);
619 xhci_dbg(xhci, "Command ring memory map follows:\n");
620 xhci_debug_ring(xhci, xhci->cmd_ring);
621 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
622 xhci_dbg_cmd_ptrs(xhci);
624 xhci_dbg(xhci, "ERST memory map follows:\n");
625 xhci_dbg_erst(xhci, &xhci->erst);
626 xhci_dbg(xhci, "Event ring:\n");
627 xhci_debug_ring(xhci, xhci->event_ring);
628 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
629 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
630 temp_64 &= ~ERST_PTR_MASK;
631 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
632 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
634 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
635 "// Set the interrupt modulation register");
636 temp = readl(&xhci->ir_set->irq_control);
637 temp &= ~ER_IRQ_INTERVAL_MASK;
639 * the increment interval is 8 times as much as that defined
640 * in xHCI spec on MTK's controller
642 temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160);
643 writel(temp, &xhci->ir_set->irq_control);
645 /* Set the HCD state before we enable the irqs */
646 temp = readl(&xhci->op_regs->command);
648 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
649 "// Enable interrupts, cmd = 0x%x.", temp);
650 writel(temp, &xhci->op_regs->command);
652 temp = readl(&xhci->ir_set->irq_pending);
653 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
654 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
655 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
656 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
657 xhci_print_ir_set(xhci, 0);
659 if (xhci->quirks & XHCI_NEC_HOST) {
660 struct xhci_command *command;
661 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
664 xhci_queue_vendor_command(xhci, command, 0, 0, 0,
665 TRB_TYPE(TRB_NEC_GET_FW));
667 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
668 "Finished xhci_run for USB2 roothub");
671 EXPORT_SYMBOL_GPL(xhci_run);
676 * This function is called by the USB core when the HC driver is removed.
677 * Its opposite is xhci_run().
679 * Disable device contexts, disable IRQs, and quiesce the HC.
680 * Reset the HC, finish any completed transactions, and cleanup memory.
682 void xhci_stop(struct usb_hcd *hcd)
685 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
687 mutex_lock(&xhci->mutex);
689 if (!(xhci->xhc_state & XHCI_STATE_HALTED)) {
690 spin_lock_irq(&xhci->lock);
692 xhci->xhc_state |= XHCI_STATE_HALTED;
693 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
697 spin_unlock_irq(&xhci->lock);
700 if (!usb_hcd_is_primary_hcd(hcd)) {
701 mutex_unlock(&xhci->mutex);
705 xhci_cleanup_msix(xhci);
707 /* Deleting Compliance Mode Recovery Timer */
708 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
709 (!(xhci_all_ports_seen_u0(xhci)))) {
710 del_timer_sync(&xhci->comp_mode_recovery_timer);
711 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
712 "%s: compliance mode recovery timer deleted",
716 if (xhci->quirks & XHCI_AMD_PLL_FIX)
719 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
720 "// Disabling event ring interrupts");
721 temp = readl(&xhci->op_regs->status);
722 writel(temp & ~STS_EINT, &xhci->op_regs->status);
723 temp = readl(&xhci->ir_set->irq_pending);
724 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
725 xhci_print_ir_set(xhci, 0);
727 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
728 xhci_mem_cleanup(xhci);
729 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
730 "xhci_stop completed - status = %x",
731 readl(&xhci->op_regs->status));
732 mutex_unlock(&xhci->mutex);
736 * Shutdown HC (not bus-specific)
738 * This is called when the machine is rebooting or halting. We assume that the
739 * machine will be powered off, and the HC's internal state will be reset.
740 * Don't bother to free memory.
742 * This will only ever be called with the main usb_hcd (the USB3 roothub).
744 void xhci_shutdown(struct usb_hcd *hcd)
746 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
748 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
749 usb_disable_xhci_ports(to_pci_dev(hcd->self.controller));
751 spin_lock_irq(&xhci->lock);
753 /* Workaround for spurious wakeups at shutdown with HSW */
754 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
756 spin_unlock_irq(&xhci->lock);
758 xhci_cleanup_msix(xhci);
760 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
761 "xhci_shutdown completed - status = %x",
762 readl(&xhci->op_regs->status));
764 /* Yet another workaround for spurious wakeups at shutdown with HSW */
765 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
766 pci_set_power_state(to_pci_dev(hcd->self.controller), PCI_D3hot);
770 static void xhci_save_registers(struct xhci_hcd *xhci)
772 xhci->s3.command = readl(&xhci->op_regs->command);
773 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
774 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
775 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
776 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
777 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
778 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
779 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
780 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
783 static void xhci_restore_registers(struct xhci_hcd *xhci)
785 writel(xhci->s3.command, &xhci->op_regs->command);
786 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
787 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
788 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
789 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
790 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
791 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
792 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
793 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
796 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
800 /* step 2: initialize command ring buffer */
801 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
802 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
803 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
804 xhci->cmd_ring->dequeue) &
805 (u64) ~CMD_RING_RSVD_BITS) |
806 xhci->cmd_ring->cycle_state;
807 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
808 "// Setting command ring address to 0x%llx",
809 (long unsigned long) val_64);
810 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
814 * The whole command ring must be cleared to zero when we suspend the host.
816 * The host doesn't save the command ring pointer in the suspend well, so we
817 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
818 * aligned, because of the reserved bits in the command ring dequeue pointer
819 * register. Therefore, we can't just set the dequeue pointer back in the
820 * middle of the ring (TRBs are 16-byte aligned).
822 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
824 struct xhci_ring *ring;
825 struct xhci_segment *seg;
827 ring = xhci->cmd_ring;
831 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
832 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
833 cpu_to_le32(~TRB_CYCLE);
835 } while (seg != ring->deq_seg);
837 /* Reset the software enqueue and dequeue pointers */
838 ring->deq_seg = ring->first_seg;
839 ring->dequeue = ring->first_seg->trbs;
840 ring->enq_seg = ring->deq_seg;
841 ring->enqueue = ring->dequeue;
843 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
845 * Ring is now zeroed, so the HW should look for change of ownership
846 * when the cycle bit is set to 1.
848 ring->cycle_state = 1;
851 * Reset the hardware dequeue pointer.
852 * Yes, this will need to be re-written after resume, but we're paranoid
853 * and want to make sure the hardware doesn't access bogus memory
854 * because, say, the BIOS or an SMI started the host without changing
855 * the command ring pointers.
857 xhci_set_cmd_ring_deq(xhci);
860 static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
863 __le32 __iomem **port_array;
867 spin_lock_irqsave(&xhci->lock, flags);
869 /* disble usb3 ports Wake bits*/
870 port_index = xhci->num_usb3_ports;
871 port_array = xhci->usb3_ports;
872 while (port_index--) {
873 t1 = readl(port_array[port_index]);
874 t1 = xhci_port_state_to_neutral(t1);
875 t2 = t1 & ~PORT_WAKE_BITS;
877 writel(t2, port_array[port_index]);
880 /* disble usb2 ports Wake bits*/
881 port_index = xhci->num_usb2_ports;
882 port_array = xhci->usb2_ports;
883 while (port_index--) {
884 t1 = readl(port_array[port_index]);
885 t1 = xhci_port_state_to_neutral(t1);
886 t2 = t1 & ~PORT_WAKE_BITS;
888 writel(t2, port_array[port_index]);
891 spin_unlock_irqrestore(&xhci->lock, flags);
895 * Stop HC (not bus-specific)
897 * This is called when the machine transition into S3/S4 mode.
900 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
903 unsigned int delay = XHCI_MAX_HALT_USEC;
904 struct usb_hcd *hcd = xhci_to_hcd(xhci);
910 if (hcd->state != HC_STATE_SUSPENDED ||
911 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
914 /* Clear root port wake on bits if wakeup not allowed. */
916 xhci_disable_port_wake_on_bits(xhci);
918 /* Don't poll the roothubs on bus suspend. */
919 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
920 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
921 del_timer_sync(&hcd->rh_timer);
922 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
923 del_timer_sync(&xhci->shared_hcd->rh_timer);
925 spin_lock_irq(&xhci->lock);
926 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
927 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
928 /* step 1: stop endpoint */
929 /* skipped assuming that port suspend has done */
931 /* step 2: clear Run/Stop bit */
932 command = readl(&xhci->op_regs->command);
934 writel(command, &xhci->op_regs->command);
936 /* Some chips from Fresco Logic need an extraordinary delay */
937 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
939 if (xhci_handshake(&xhci->op_regs->status,
940 STS_HALT, STS_HALT, delay)) {
941 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
942 spin_unlock_irq(&xhci->lock);
945 xhci_clear_command_ring(xhci);
947 /* step 3: save registers */
948 xhci_save_registers(xhci);
950 /* step 4: set CSS flag */
951 command = readl(&xhci->op_regs->command);
953 writel(command, &xhci->op_regs->command);
954 if (xhci_handshake(&xhci->op_regs->status,
955 STS_SAVE, 0, 10 * 1000)) {
956 xhci_warn(xhci, "WARN: xHC save state timeout\n");
957 spin_unlock_irq(&xhci->lock);
960 spin_unlock_irq(&xhci->lock);
963 * Deleting Compliance Mode Recovery Timer because the xHCI Host
964 * is about to be suspended.
966 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
967 (!(xhci_all_ports_seen_u0(xhci)))) {
968 del_timer_sync(&xhci->comp_mode_recovery_timer);
969 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
970 "%s: compliance mode recovery timer deleted",
974 /* step 5: remove core well power */
975 /* synchronize irq when using MSI-X */
976 xhci_msix_sync_irqs(xhci);
980 EXPORT_SYMBOL_GPL(xhci_suspend);
983 * start xHC (not bus-specific)
985 * This is called when the machine transition from S3/S4 mode.
988 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
990 u32 command, temp = 0, status;
991 struct usb_hcd *hcd = xhci_to_hcd(xhci);
992 struct usb_hcd *secondary_hcd;
994 bool comp_timer_running = false;
999 /* Wait a bit if either of the roothubs need to settle from the
1000 * transition into bus suspend.
1002 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
1003 time_before(jiffies,
1004 xhci->bus_state[1].next_statechange))
1007 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1008 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1010 spin_lock_irq(&xhci->lock);
1011 if (xhci->quirks & XHCI_RESET_ON_RESUME)
1015 /* step 1: restore register */
1016 xhci_restore_registers(xhci);
1017 /* step 2: initialize command ring buffer */
1018 xhci_set_cmd_ring_deq(xhci);
1019 /* step 3: restore state and start state*/
1020 /* step 3: set CRS flag */
1021 command = readl(&xhci->op_regs->command);
1023 writel(command, &xhci->op_regs->command);
1024 if (xhci_handshake(&xhci->op_regs->status,
1025 STS_RESTORE, 0, 10 * 1000)) {
1026 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1027 spin_unlock_irq(&xhci->lock);
1030 temp = readl(&xhci->op_regs->status);
1033 /* If restore operation fails, re-initialize the HC during resume */
1034 if ((temp & STS_SRE) || hibernated) {
1036 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1037 !(xhci_all_ports_seen_u0(xhci))) {
1038 del_timer_sync(&xhci->comp_mode_recovery_timer);
1039 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1040 "Compliance Mode Recovery Timer deleted!");
1043 /* Let the USB core know _both_ roothubs lost power. */
1044 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1045 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1047 xhci_dbg(xhci, "Stop HCD\n");
1050 spin_unlock_irq(&xhci->lock);
1051 xhci_cleanup_msix(xhci);
1053 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1054 temp = readl(&xhci->op_regs->status);
1055 writel(temp & ~STS_EINT, &xhci->op_regs->status);
1056 temp = readl(&xhci->ir_set->irq_pending);
1057 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1058 xhci_print_ir_set(xhci, 0);
1060 xhci_dbg(xhci, "cleaning up memory\n");
1061 xhci_mem_cleanup(xhci);
1062 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1063 readl(&xhci->op_regs->status));
1065 /* USB core calls the PCI reinit and start functions twice:
1066 * first with the primary HCD, and then with the secondary HCD.
1067 * If we don't do the same, the host will never be started.
1069 if (!usb_hcd_is_primary_hcd(hcd))
1070 secondary_hcd = hcd;
1072 secondary_hcd = xhci->shared_hcd;
1074 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1075 retval = xhci_init(hcd->primary_hcd);
1078 comp_timer_running = true;
1080 xhci_dbg(xhci, "Start the primary HCD\n");
1081 retval = xhci_run(hcd->primary_hcd);
1083 xhci_dbg(xhci, "Start the secondary HCD\n");
1084 retval = xhci_run(secondary_hcd);
1086 hcd->state = HC_STATE_SUSPENDED;
1087 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1091 /* step 4: set Run/Stop bit */
1092 command = readl(&xhci->op_regs->command);
1094 writel(command, &xhci->op_regs->command);
1095 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1098 /* step 5: walk topology and initialize portsc,
1099 * portpmsc and portli
1101 /* this is done in bus_resume */
1103 /* step 6: restart each of the previously
1104 * Running endpoints by ringing their doorbells
1107 spin_unlock_irq(&xhci->lock);
1111 /* Resume root hubs only when have pending events. */
1112 status = readl(&xhci->op_regs->status);
1113 if (status & STS_EINT) {
1114 usb_hcd_resume_root_hub(xhci->shared_hcd);
1115 usb_hcd_resume_root_hub(hcd);
1120 * If system is subject to the Quirk, Compliance Mode Timer needs to
1121 * be re-initialized Always after a system resume. Ports are subject
1122 * to suffer the Compliance Mode issue again. It doesn't matter if
1123 * ports have entered previously to U0 before system's suspension.
1125 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1126 compliance_mode_recovery_timer_init(xhci);
1128 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1129 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1131 /* Re-enable port polling. */
1132 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1133 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1134 usb_hcd_poll_rh_status(xhci->shared_hcd);
1135 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1136 usb_hcd_poll_rh_status(hcd);
1140 EXPORT_SYMBOL_GPL(xhci_resume);
1141 #endif /* CONFIG_PM */
1143 /*-------------------------------------------------------------------------*/
1146 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1147 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1148 * value to right shift 1 for the bitmask.
1150 * Index = (epnum * 2) + direction - 1,
1151 * where direction = 0 for OUT, 1 for IN.
1152 * For control endpoints, the IN index is used (OUT index is unused), so
1153 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1155 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1158 if (usb_endpoint_xfer_control(desc))
1159 index = (unsigned int) (usb_endpoint_num(desc)*2);
1161 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1162 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1166 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1167 * address from the XHCI endpoint index.
1169 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1171 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1172 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1173 return direction | number;
1176 /* Find the flag for this endpoint (for use in the control context). Use the
1177 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1180 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1182 return 1 << (xhci_get_endpoint_index(desc) + 1);
1185 /* Find the flag for this endpoint (for use in the control context). Use the
1186 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1189 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1191 return 1 << (ep_index + 1);
1194 /* Compute the last valid endpoint context index. Basically, this is the
1195 * endpoint index plus one. For slot contexts with more than valid endpoint,
1196 * we find the most significant bit set in the added contexts flags.
1197 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1198 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1200 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1202 return fls(added_ctxs) - 1;
1205 /* Returns 1 if the arguments are OK;
1206 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1208 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1209 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1211 struct xhci_hcd *xhci;
1212 struct xhci_virt_device *virt_dev;
1214 if (!hcd || (check_ep && !ep) || !udev) {
1215 pr_debug("xHCI %s called with invalid args\n", func);
1218 if (!udev->parent) {
1219 pr_debug("xHCI %s called for root hub\n", func);
1223 xhci = hcd_to_xhci(hcd);
1224 if (check_virt_dev) {
1225 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1226 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1231 virt_dev = xhci->devs[udev->slot_id];
1232 if (virt_dev->udev != udev) {
1233 xhci_dbg(xhci, "xHCI %s called with udev and "
1234 "virt_dev does not match\n", func);
1239 if (xhci->xhc_state & XHCI_STATE_HALTED)
1245 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1246 struct usb_device *udev, struct xhci_command *command,
1247 bool ctx_change, bool must_succeed);
1250 * Full speed devices may have a max packet size greater than 8 bytes, but the
1251 * USB core doesn't know that until it reads the first 8 bytes of the
1252 * descriptor. If the usb_device's max packet size changes after that point,
1253 * we need to issue an evaluate context command and wait on it.
1255 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1256 unsigned int ep_index, struct urb *urb)
1258 struct xhci_container_ctx *out_ctx;
1259 struct xhci_input_control_ctx *ctrl_ctx;
1260 struct xhci_ep_ctx *ep_ctx;
1261 struct xhci_command *command;
1262 int max_packet_size;
1263 int hw_max_packet_size;
1266 out_ctx = xhci->devs[slot_id]->out_ctx;
1267 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1268 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1269 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1270 if (hw_max_packet_size != max_packet_size) {
1271 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1272 "Max Packet Size for ep 0 changed.");
1273 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1274 "Max packet size in usb_device = %d",
1276 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1277 "Max packet size in xHCI HW = %d",
1278 hw_max_packet_size);
1279 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1280 "Issuing evaluate context command.");
1282 /* Set up the input context flags for the command */
1283 /* FIXME: This won't work if a non-default control endpoint
1284 * changes max packet sizes.
1287 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
1291 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1292 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1294 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1297 goto command_cleanup;
1299 /* Set up the modified control endpoint 0 */
1300 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1301 xhci->devs[slot_id]->out_ctx, ep_index);
1303 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1304 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1305 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1307 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1308 ctrl_ctx->drop_flags = 0;
1310 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1311 xhci_dbg_ctx(xhci, command->in_ctx, ep_index);
1312 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1313 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1315 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1318 /* Clean up the input context for later use by bandwidth
1321 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1323 kfree(command->completion);
1330 * non-error returns are a promise to giveback() the urb later
1331 * we drop ownership so next owner (or urb unlink) can get it
1333 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1335 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1336 struct xhci_td *buffer;
1337 unsigned long flags;
1339 unsigned int slot_id, ep_index;
1340 struct urb_priv *urb_priv;
1343 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1344 true, true, __func__) <= 0)
1347 slot_id = urb->dev->slot_id;
1348 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1350 if (!HCD_HW_ACCESSIBLE(hcd)) {
1351 if (!in_interrupt())
1352 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1357 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1358 size = urb->number_of_packets;
1359 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1360 urb->transfer_buffer_length > 0 &&
1361 urb->transfer_flags & URB_ZERO_PACKET &&
1362 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1367 urb_priv = kzalloc(sizeof(struct urb_priv) +
1368 size * sizeof(struct xhci_td *), mem_flags);
1372 buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
1378 for (i = 0; i < size; i++) {
1379 urb_priv->td[i] = buffer;
1383 urb_priv->length = size;
1384 urb_priv->td_cnt = 0;
1385 urb->hcpriv = urb_priv;
1387 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1388 /* Check to see if the max packet size for the default control
1389 * endpoint changed during FS device enumeration
1391 if (urb->dev->speed == USB_SPEED_FULL) {
1392 ret = xhci_check_maxpacket(xhci, slot_id,
1395 xhci_urb_free_priv(urb_priv);
1401 /* We have a spinlock and interrupts disabled, so we must pass
1402 * atomic context to this function, which may allocate memory.
1404 spin_lock_irqsave(&xhci->lock, flags);
1405 if (xhci->xhc_state & XHCI_STATE_DYING)
1407 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1411 spin_unlock_irqrestore(&xhci->lock, flags);
1412 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1413 spin_lock_irqsave(&xhci->lock, flags);
1414 if (xhci->xhc_state & XHCI_STATE_DYING)
1416 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1417 EP_GETTING_STREAMS) {
1418 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1419 "is transitioning to using streams.\n");
1421 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1422 EP_GETTING_NO_STREAMS) {
1423 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1424 "is transitioning to "
1425 "not having streams.\n");
1428 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1433 spin_unlock_irqrestore(&xhci->lock, flags);
1434 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1435 spin_lock_irqsave(&xhci->lock, flags);
1436 if (xhci->xhc_state & XHCI_STATE_DYING)
1438 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1442 spin_unlock_irqrestore(&xhci->lock, flags);
1444 spin_lock_irqsave(&xhci->lock, flags);
1445 if (xhci->xhc_state & XHCI_STATE_DYING)
1447 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1451 spin_unlock_irqrestore(&xhci->lock, flags);
1456 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1457 "non-responsive xHCI host.\n",
1458 urb->ep->desc.bEndpointAddress, urb);
1461 xhci_urb_free_priv(urb_priv);
1463 spin_unlock_irqrestore(&xhci->lock, flags);
1468 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1469 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1470 * should pick up where it left off in the TD, unless a Set Transfer Ring
1471 * Dequeue Pointer is issued.
1473 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1474 * the ring. Since the ring is a contiguous structure, they can't be physically
1475 * removed. Instead, there are two options:
1477 * 1) If the HC is in the middle of processing the URB to be canceled, we
1478 * simply move the ring's dequeue pointer past those TRBs using the Set
1479 * Transfer Ring Dequeue Pointer command. This will be the common case,
1480 * when drivers timeout on the last submitted URB and attempt to cancel.
1482 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1483 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1484 * HC will need to invalidate the any TRBs it has cached after the stop
1485 * endpoint command, as noted in the xHCI 0.95 errata.
1487 * 3) The TD may have completed by the time the Stop Endpoint Command
1488 * completes, so software needs to handle that case too.
1490 * This function should protect against the TD enqueueing code ringing the
1491 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1492 * It also needs to account for multiple cancellations on happening at the same
1493 * time for the same endpoint.
1495 * Note that this function can be called in any context, or so says
1496 * usb_hcd_unlink_urb()
1498 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1500 unsigned long flags;
1503 struct xhci_hcd *xhci;
1504 struct urb_priv *urb_priv;
1506 unsigned int ep_index;
1507 struct xhci_ring *ep_ring;
1508 struct xhci_virt_ep *ep;
1509 struct xhci_command *command;
1511 xhci = hcd_to_xhci(hcd);
1512 spin_lock_irqsave(&xhci->lock, flags);
1513 /* Make sure the URB hasn't completed or been unlinked already */
1514 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1515 if (ret || !urb->hcpriv)
1517 temp = readl(&xhci->op_regs->status);
1518 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
1519 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1520 "HW died, freeing TD.");
1521 urb_priv = urb->hcpriv;
1522 for (i = urb_priv->td_cnt;
1523 i < urb_priv->length && xhci->devs[urb->dev->slot_id];
1525 td = urb_priv->td[i];
1526 if (!list_empty(&td->td_list))
1527 list_del_init(&td->td_list);
1528 if (!list_empty(&td->cancelled_td_list))
1529 list_del_init(&td->cancelled_td_list);
1532 usb_hcd_unlink_urb_from_ep(hcd, urb);
1533 spin_unlock_irqrestore(&xhci->lock, flags);
1534 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1535 xhci_urb_free_priv(urb_priv);
1539 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1540 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
1541 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1547 urb_priv = urb->hcpriv;
1548 i = urb_priv->td_cnt;
1549 if (i < urb_priv->length)
1550 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1551 "Cancel URB %p, dev %s, ep 0x%x, "
1552 "starting at offset 0x%llx",
1553 urb, urb->dev->devpath,
1554 urb->ep->desc.bEndpointAddress,
1555 (unsigned long long) xhci_trb_virt_to_dma(
1556 urb_priv->td[i]->start_seg,
1557 urb_priv->td[i]->first_trb));
1559 for (; i < urb_priv->length; i++) {
1560 td = urb_priv->td[i];
1561 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1564 /* Queue a stop endpoint command, but only if this is
1565 * the first cancellation to be handled.
1567 if (!(ep->ep_state & EP_HALT_PENDING)) {
1568 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1573 ep->ep_state |= EP_HALT_PENDING;
1574 ep->stop_cmds_pending++;
1575 ep->stop_cmd_timer.expires = jiffies +
1576 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1577 add_timer(&ep->stop_cmd_timer);
1578 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1580 xhci_ring_cmd_db(xhci);
1583 spin_unlock_irqrestore(&xhci->lock, flags);
1587 /* Drop an endpoint from a new bandwidth configuration for this device.
1588 * Only one call to this function is allowed per endpoint before
1589 * check_bandwidth() or reset_bandwidth() must be called.
1590 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1591 * add the endpoint to the schedule with possibly new parameters denoted by a
1592 * different endpoint descriptor in usb_host_endpoint.
1593 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1596 * The USB core will not allow URBs to be queued to an endpoint that is being
1597 * disabled, so there's no need for mutual exclusion to protect
1598 * the xhci->devs[slot_id] structure.
1600 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1601 struct usb_host_endpoint *ep)
1603 struct xhci_hcd *xhci;
1604 struct xhci_container_ctx *in_ctx, *out_ctx;
1605 struct xhci_input_control_ctx *ctrl_ctx;
1606 unsigned int ep_index;
1607 struct xhci_ep_ctx *ep_ctx;
1609 u32 new_add_flags, new_drop_flags;
1612 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1615 xhci = hcd_to_xhci(hcd);
1616 if (xhci->xhc_state & XHCI_STATE_DYING)
1619 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1620 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1621 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1622 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1623 __func__, drop_flag);
1627 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1628 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1629 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1631 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1636 ep_index = xhci_get_endpoint_index(&ep->desc);
1637 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1638 /* If the HC already knows the endpoint is disabled,
1639 * or the HCD has noted it is disabled, ignore this request
1641 if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1642 cpu_to_le32(EP_STATE_DISABLED)) ||
1643 le32_to_cpu(ctrl_ctx->drop_flags) &
1644 xhci_get_endpoint_flag(&ep->desc)) {
1645 /* Do not warn when called after a usb_device_reset */
1646 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1647 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1652 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1653 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1655 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1656 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1658 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1660 if (xhci->quirks & XHCI_MTK_HOST)
1661 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1663 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1664 (unsigned int) ep->desc.bEndpointAddress,
1666 (unsigned int) new_drop_flags,
1667 (unsigned int) new_add_flags);
1671 /* Add an endpoint to a new possible bandwidth configuration for this device.
1672 * Only one call to this function is allowed per endpoint before
1673 * check_bandwidth() or reset_bandwidth() must be called.
1674 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1675 * add the endpoint to the schedule with possibly new parameters denoted by a
1676 * different endpoint descriptor in usb_host_endpoint.
1677 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1680 * The USB core will not allow URBs to be queued to an endpoint until the
1681 * configuration or alt setting is installed in the device, so there's no need
1682 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1684 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1685 struct usb_host_endpoint *ep)
1687 struct xhci_hcd *xhci;
1688 struct xhci_container_ctx *in_ctx;
1689 unsigned int ep_index;
1690 struct xhci_input_control_ctx *ctrl_ctx;
1692 u32 new_add_flags, new_drop_flags;
1693 struct xhci_virt_device *virt_dev;
1696 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1698 /* So we won't queue a reset ep command for a root hub */
1702 xhci = hcd_to_xhci(hcd);
1703 if (xhci->xhc_state & XHCI_STATE_DYING)
1706 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1707 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1708 /* FIXME when we have to issue an evaluate endpoint command to
1709 * deal with ep0 max packet size changing once we get the
1712 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1713 __func__, added_ctxs);
1717 virt_dev = xhci->devs[udev->slot_id];
1718 in_ctx = virt_dev->in_ctx;
1719 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1721 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1726 ep_index = xhci_get_endpoint_index(&ep->desc);
1727 /* If this endpoint is already in use, and the upper layers are trying
1728 * to add it again without dropping it, reject the addition.
1730 if (virt_dev->eps[ep_index].ring &&
1731 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1732 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1733 "without dropping it.\n",
1734 (unsigned int) ep->desc.bEndpointAddress);
1738 /* If the HCD has already noted the endpoint is enabled,
1739 * ignore this request.
1741 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1742 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1748 * Configuration and alternate setting changes must be done in
1749 * process context, not interrupt context (or so documenation
1750 * for usb_set_interface() and usb_set_configuration() claim).
1752 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1753 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1754 __func__, ep->desc.bEndpointAddress);
1758 if (xhci->quirks & XHCI_MTK_HOST) {
1759 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1761 xhci_free_or_cache_endpoint_ring(xhci,
1762 virt_dev, ep_index);
1767 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1768 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1770 /* If xhci_endpoint_disable() was called for this endpoint, but the
1771 * xHC hasn't been notified yet through the check_bandwidth() call,
1772 * this re-adds a new state for the endpoint from the new endpoint
1773 * descriptors. We must drop and re-add this endpoint, so we leave the
1776 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1778 /* Store the usb_device pointer for later use */
1781 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1782 (unsigned int) ep->desc.bEndpointAddress,
1784 (unsigned int) new_drop_flags,
1785 (unsigned int) new_add_flags);
1789 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1791 struct xhci_input_control_ctx *ctrl_ctx;
1792 struct xhci_ep_ctx *ep_ctx;
1793 struct xhci_slot_ctx *slot_ctx;
1796 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1798 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1803 /* When a device's add flag and drop flag are zero, any subsequent
1804 * configure endpoint command will leave that endpoint's state
1805 * untouched. Make sure we don't leave any old state in the input
1806 * endpoint contexts.
1808 ctrl_ctx->drop_flags = 0;
1809 ctrl_ctx->add_flags = 0;
1810 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1811 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1812 /* Endpoint 0 is always valid */
1813 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1814 for (i = 1; i < 31; ++i) {
1815 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1816 ep_ctx->ep_info = 0;
1817 ep_ctx->ep_info2 = 0;
1819 ep_ctx->tx_info = 0;
1823 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1824 struct usb_device *udev, u32 *cmd_status)
1828 switch (*cmd_status) {
1829 case COMP_CMD_ABORT:
1831 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1835 dev_warn(&udev->dev,
1836 "Not enough host controller resources for new device state.\n");
1838 /* FIXME: can we allocate more resources for the HC? */
1841 case COMP_2ND_BW_ERR:
1842 dev_warn(&udev->dev,
1843 "Not enough bandwidth for new device state.\n");
1845 /* FIXME: can we go back to the old state? */
1848 /* the HCD set up something wrong */
1849 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1851 "and endpoint is not disabled.\n");
1855 dev_warn(&udev->dev,
1856 "ERROR: Incompatible device for endpoint configure command.\n");
1860 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1861 "Successful Endpoint Configure command");
1865 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1873 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1874 struct usb_device *udev, u32 *cmd_status)
1877 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1879 switch (*cmd_status) {
1880 case COMP_CMD_ABORT:
1882 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
1886 dev_warn(&udev->dev,
1887 "WARN: xHCI driver setup invalid evaluate context command.\n");
1891 dev_warn(&udev->dev,
1892 "WARN: slot not enabled for evaluate context command.\n");
1895 case COMP_CTX_STATE:
1896 dev_warn(&udev->dev,
1897 "WARN: invalid context state for evaluate context command.\n");
1898 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1902 dev_warn(&udev->dev,
1903 "ERROR: Incompatible device for evaluate context command.\n");
1907 /* Max Exit Latency too large error */
1908 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1912 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1913 "Successful evaluate context command");
1917 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1925 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1926 struct xhci_input_control_ctx *ctrl_ctx)
1928 u32 valid_add_flags;
1929 u32 valid_drop_flags;
1931 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1932 * (bit 1). The default control endpoint is added during the Address
1933 * Device command and is never removed until the slot is disabled.
1935 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1936 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1938 /* Use hweight32 to count the number of ones in the add flags, or
1939 * number of endpoints added. Don't count endpoints that are changed
1940 * (both added and dropped).
1942 return hweight32(valid_add_flags) -
1943 hweight32(valid_add_flags & valid_drop_flags);
1946 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
1947 struct xhci_input_control_ctx *ctrl_ctx)
1949 u32 valid_add_flags;
1950 u32 valid_drop_flags;
1952 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1953 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1955 return hweight32(valid_drop_flags) -
1956 hweight32(valid_add_flags & valid_drop_flags);
1960 * We need to reserve the new number of endpoints before the configure endpoint
1961 * command completes. We can't subtract the dropped endpoints from the number
1962 * of active endpoints until the command completes because we can oversubscribe
1963 * the host in this case:
1965 * - the first configure endpoint command drops more endpoints than it adds
1966 * - a second configure endpoint command that adds more endpoints is queued
1967 * - the first configure endpoint command fails, so the config is unchanged
1968 * - the second command may succeed, even though there isn't enough resources
1970 * Must be called with xhci->lock held.
1972 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
1973 struct xhci_input_control_ctx *ctrl_ctx)
1977 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
1978 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
1979 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1980 "Not enough ep ctxs: "
1981 "%u active, need to add %u, limit is %u.",
1982 xhci->num_active_eps, added_eps,
1983 xhci->limit_active_eps);
1986 xhci->num_active_eps += added_eps;
1987 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1988 "Adding %u ep ctxs, %u now active.", added_eps,
1989 xhci->num_active_eps);
1994 * The configure endpoint was failed by the xHC for some other reason, so we
1995 * need to revert the resources that failed configuration would have used.
1997 * Must be called with xhci->lock held.
1999 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2000 struct xhci_input_control_ctx *ctrl_ctx)
2004 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2005 xhci->num_active_eps -= num_failed_eps;
2006 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2007 "Removing %u failed ep ctxs, %u now active.",
2009 xhci->num_active_eps);
2013 * Now that the command has completed, clean up the active endpoint count by
2014 * subtracting out the endpoints that were dropped (but not changed).
2016 * Must be called with xhci->lock held.
2018 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2019 struct xhci_input_control_ctx *ctrl_ctx)
2021 u32 num_dropped_eps;
2023 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2024 xhci->num_active_eps -= num_dropped_eps;
2025 if (num_dropped_eps)
2026 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2027 "Removing %u dropped ep ctxs, %u now active.",
2029 xhci->num_active_eps);
2032 static unsigned int xhci_get_block_size(struct usb_device *udev)
2034 switch (udev->speed) {
2036 case USB_SPEED_FULL:
2038 case USB_SPEED_HIGH:
2040 case USB_SPEED_SUPER:
2041 case USB_SPEED_SUPER_PLUS:
2043 case USB_SPEED_UNKNOWN:
2044 case USB_SPEED_WIRELESS:
2046 /* Should never happen */
2052 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2054 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2056 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2061 /* If we are changing a LS/FS device under a HS hub,
2062 * make sure (if we are activating a new TT) that the HS bus has enough
2063 * bandwidth for this new TT.
2065 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2066 struct xhci_virt_device *virt_dev,
2069 struct xhci_interval_bw_table *bw_table;
2070 struct xhci_tt_bw_info *tt_info;
2072 /* Find the bandwidth table for the root port this TT is attached to. */
2073 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2074 tt_info = virt_dev->tt_info;
2075 /* If this TT already had active endpoints, the bandwidth for this TT
2076 * has already been added. Removing all periodic endpoints (and thus
2077 * making the TT enactive) will only decrease the bandwidth used.
2081 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2082 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2086 /* Not sure why we would have no new active endpoints...
2088 * Maybe because of an Evaluate Context change for a hub update or a
2089 * control endpoint 0 max packet size change?
2090 * FIXME: skip the bandwidth calculation in that case.
2095 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2096 struct xhci_virt_device *virt_dev)
2098 unsigned int bw_reserved;
2100 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2101 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2104 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2105 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2112 * This algorithm is a very conservative estimate of the worst-case scheduling
2113 * scenario for any one interval. The hardware dynamically schedules the
2114 * packets, so we can't tell which microframe could be the limiting factor in
2115 * the bandwidth scheduling. This only takes into account periodic endpoints.
2117 * Obviously, we can't solve an NP complete problem to find the minimum worst
2118 * case scenario. Instead, we come up with an estimate that is no less than
2119 * the worst case bandwidth used for any one microframe, but may be an
2122 * We walk the requirements for each endpoint by interval, starting with the
2123 * smallest interval, and place packets in the schedule where there is only one
2124 * possible way to schedule packets for that interval. In order to simplify
2125 * this algorithm, we record the largest max packet size for each interval, and
2126 * assume all packets will be that size.
2128 * For interval 0, we obviously must schedule all packets for each interval.
2129 * The bandwidth for interval 0 is just the amount of data to be transmitted
2130 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2131 * the number of packets).
2133 * For interval 1, we have two possible microframes to schedule those packets
2134 * in. For this algorithm, if we can schedule the same number of packets for
2135 * each possible scheduling opportunity (each microframe), we will do so. The
2136 * remaining number of packets will be saved to be transmitted in the gaps in
2137 * the next interval's scheduling sequence.
2139 * As we move those remaining packets to be scheduled with interval 2 packets,
2140 * we have to double the number of remaining packets to transmit. This is
2141 * because the intervals are actually powers of 2, and we would be transmitting
2142 * the previous interval's packets twice in this interval. We also have to be
2143 * sure that when we look at the largest max packet size for this interval, we
2144 * also look at the largest max packet size for the remaining packets and take
2145 * the greater of the two.
2147 * The algorithm continues to evenly distribute packets in each scheduling
2148 * opportunity, and push the remaining packets out, until we get to the last
2149 * interval. Then those packets and their associated overhead are just added
2150 * to the bandwidth used.
2152 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2153 struct xhci_virt_device *virt_dev,
2156 unsigned int bw_reserved;
2157 unsigned int max_bandwidth;
2158 unsigned int bw_used;
2159 unsigned int block_size;
2160 struct xhci_interval_bw_table *bw_table;
2161 unsigned int packet_size = 0;
2162 unsigned int overhead = 0;
2163 unsigned int packets_transmitted = 0;
2164 unsigned int packets_remaining = 0;
2167 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2168 return xhci_check_ss_bw(xhci, virt_dev);
2170 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2171 max_bandwidth = HS_BW_LIMIT;
2172 /* Convert percent of bus BW reserved to blocks reserved */
2173 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2175 max_bandwidth = FS_BW_LIMIT;
2176 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2179 bw_table = virt_dev->bw_table;
2180 /* We need to translate the max packet size and max ESIT payloads into
2181 * the units the hardware uses.
2183 block_size = xhci_get_block_size(virt_dev->udev);
2185 /* If we are manipulating a LS/FS device under a HS hub, double check
2186 * that the HS bus has enough bandwidth if we are activing a new TT.
2188 if (virt_dev->tt_info) {
2189 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2190 "Recalculating BW for rootport %u",
2191 virt_dev->real_port);
2192 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2193 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2194 "newly activated TT.\n");
2197 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2198 "Recalculating BW for TT slot %u port %u",
2199 virt_dev->tt_info->slot_id,
2200 virt_dev->tt_info->ttport);
2202 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2203 "Recalculating BW for rootport %u",
2204 virt_dev->real_port);
2207 /* Add in how much bandwidth will be used for interval zero, or the
2208 * rounded max ESIT payload + number of packets * largest overhead.
2210 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2211 bw_table->interval_bw[0].num_packets *
2212 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2214 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2215 unsigned int bw_added;
2216 unsigned int largest_mps;
2217 unsigned int interval_overhead;
2220 * How many packets could we transmit in this interval?
2221 * If packets didn't fit in the previous interval, we will need
2222 * to transmit that many packets twice within this interval.
2224 packets_remaining = 2 * packets_remaining +
2225 bw_table->interval_bw[i].num_packets;
2227 /* Find the largest max packet size of this or the previous
2230 if (list_empty(&bw_table->interval_bw[i].endpoints))
2233 struct xhci_virt_ep *virt_ep;
2234 struct list_head *ep_entry;
2236 ep_entry = bw_table->interval_bw[i].endpoints.next;
2237 virt_ep = list_entry(ep_entry,
2238 struct xhci_virt_ep, bw_endpoint_list);
2239 /* Convert to blocks, rounding up */
2240 largest_mps = DIV_ROUND_UP(
2241 virt_ep->bw_info.max_packet_size,
2244 if (largest_mps > packet_size)
2245 packet_size = largest_mps;
2247 /* Use the larger overhead of this or the previous interval. */
2248 interval_overhead = xhci_get_largest_overhead(
2249 &bw_table->interval_bw[i]);
2250 if (interval_overhead > overhead)
2251 overhead = interval_overhead;
2253 /* How many packets can we evenly distribute across
2254 * (1 << (i + 1)) possible scheduling opportunities?
2256 packets_transmitted = packets_remaining >> (i + 1);
2258 /* Add in the bandwidth used for those scheduled packets */
2259 bw_added = packets_transmitted * (overhead + packet_size);
2261 /* How many packets do we have remaining to transmit? */
2262 packets_remaining = packets_remaining % (1 << (i + 1));
2264 /* What largest max packet size should those packets have? */
2265 /* If we've transmitted all packets, don't carry over the
2266 * largest packet size.
2268 if (packets_remaining == 0) {
2271 } else if (packets_transmitted > 0) {
2272 /* Otherwise if we do have remaining packets, and we've
2273 * scheduled some packets in this interval, take the
2274 * largest max packet size from endpoints with this
2277 packet_size = largest_mps;
2278 overhead = interval_overhead;
2280 /* Otherwise carry over packet_size and overhead from the last
2281 * time we had a remainder.
2283 bw_used += bw_added;
2284 if (bw_used > max_bandwidth) {
2285 xhci_warn(xhci, "Not enough bandwidth. "
2286 "Proposed: %u, Max: %u\n",
2287 bw_used, max_bandwidth);
2292 * Ok, we know we have some packets left over after even-handedly
2293 * scheduling interval 15. We don't know which microframes they will
2294 * fit into, so we over-schedule and say they will be scheduled every
2297 if (packets_remaining > 0)
2298 bw_used += overhead + packet_size;
2300 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2301 unsigned int port_index = virt_dev->real_port - 1;
2303 /* OK, we're manipulating a HS device attached to a
2304 * root port bandwidth domain. Include the number of active TTs
2305 * in the bandwidth used.
2307 bw_used += TT_HS_OVERHEAD *
2308 xhci->rh_bw[port_index].num_active_tts;
2311 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2312 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2313 "Available: %u " "percent",
2314 bw_used, max_bandwidth, bw_reserved,
2315 (max_bandwidth - bw_used - bw_reserved) * 100 /
2318 bw_used += bw_reserved;
2319 if (bw_used > max_bandwidth) {
2320 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2321 bw_used, max_bandwidth);
2325 bw_table->bw_used = bw_used;
2329 static bool xhci_is_async_ep(unsigned int ep_type)
2331 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2332 ep_type != ISOC_IN_EP &&
2333 ep_type != INT_IN_EP);
2336 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2338 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2341 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2343 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2345 if (ep_bw->ep_interval == 0)
2346 return SS_OVERHEAD_BURST +
2347 (ep_bw->mult * ep_bw->num_packets *
2348 (SS_OVERHEAD + mps));
2349 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2350 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2351 1 << ep_bw->ep_interval);
2355 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2356 struct xhci_bw_info *ep_bw,
2357 struct xhci_interval_bw_table *bw_table,
2358 struct usb_device *udev,
2359 struct xhci_virt_ep *virt_ep,
2360 struct xhci_tt_bw_info *tt_info)
2362 struct xhci_interval_bw *interval_bw;
2363 int normalized_interval;
2365 if (xhci_is_async_ep(ep_bw->type))
2368 if (udev->speed >= USB_SPEED_SUPER) {
2369 if (xhci_is_sync_in_ep(ep_bw->type))
2370 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2371 xhci_get_ss_bw_consumed(ep_bw);
2373 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2374 xhci_get_ss_bw_consumed(ep_bw);
2378 /* SuperSpeed endpoints never get added to intervals in the table, so
2379 * this check is only valid for HS/FS/LS devices.
2381 if (list_empty(&virt_ep->bw_endpoint_list))
2383 /* For LS/FS devices, we need to translate the interval expressed in
2384 * microframes to frames.
2386 if (udev->speed == USB_SPEED_HIGH)
2387 normalized_interval = ep_bw->ep_interval;
2389 normalized_interval = ep_bw->ep_interval - 3;
2391 if (normalized_interval == 0)
2392 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2393 interval_bw = &bw_table->interval_bw[normalized_interval];
2394 interval_bw->num_packets -= ep_bw->num_packets;
2395 switch (udev->speed) {
2397 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2399 case USB_SPEED_FULL:
2400 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2402 case USB_SPEED_HIGH:
2403 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2405 case USB_SPEED_SUPER:
2406 case USB_SPEED_SUPER_PLUS:
2407 case USB_SPEED_UNKNOWN:
2408 case USB_SPEED_WIRELESS:
2409 /* Should never happen because only LS/FS/HS endpoints will get
2410 * added to the endpoint list.
2415 tt_info->active_eps -= 1;
2416 list_del_init(&virt_ep->bw_endpoint_list);
2419 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2420 struct xhci_bw_info *ep_bw,
2421 struct xhci_interval_bw_table *bw_table,
2422 struct usb_device *udev,
2423 struct xhci_virt_ep *virt_ep,
2424 struct xhci_tt_bw_info *tt_info)
2426 struct xhci_interval_bw *interval_bw;
2427 struct xhci_virt_ep *smaller_ep;
2428 int normalized_interval;
2430 if (xhci_is_async_ep(ep_bw->type))
2433 if (udev->speed == USB_SPEED_SUPER) {
2434 if (xhci_is_sync_in_ep(ep_bw->type))
2435 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2436 xhci_get_ss_bw_consumed(ep_bw);
2438 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2439 xhci_get_ss_bw_consumed(ep_bw);
2443 /* For LS/FS devices, we need to translate the interval expressed in
2444 * microframes to frames.
2446 if (udev->speed == USB_SPEED_HIGH)
2447 normalized_interval = ep_bw->ep_interval;
2449 normalized_interval = ep_bw->ep_interval - 3;
2451 if (normalized_interval == 0)
2452 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2453 interval_bw = &bw_table->interval_bw[normalized_interval];
2454 interval_bw->num_packets += ep_bw->num_packets;
2455 switch (udev->speed) {
2457 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2459 case USB_SPEED_FULL:
2460 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2462 case USB_SPEED_HIGH:
2463 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2465 case USB_SPEED_SUPER:
2466 case USB_SPEED_SUPER_PLUS:
2467 case USB_SPEED_UNKNOWN:
2468 case USB_SPEED_WIRELESS:
2469 /* Should never happen because only LS/FS/HS endpoints will get
2470 * added to the endpoint list.
2476 tt_info->active_eps += 1;
2477 /* Insert the endpoint into the list, largest max packet size first. */
2478 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2480 if (ep_bw->max_packet_size >=
2481 smaller_ep->bw_info.max_packet_size) {
2482 /* Add the new ep before the smaller endpoint */
2483 list_add_tail(&virt_ep->bw_endpoint_list,
2484 &smaller_ep->bw_endpoint_list);
2488 /* Add the new endpoint at the end of the list. */
2489 list_add_tail(&virt_ep->bw_endpoint_list,
2490 &interval_bw->endpoints);
2493 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2494 struct xhci_virt_device *virt_dev,
2497 struct xhci_root_port_bw_info *rh_bw_info;
2498 if (!virt_dev->tt_info)
2501 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2502 if (old_active_eps == 0 &&
2503 virt_dev->tt_info->active_eps != 0) {
2504 rh_bw_info->num_active_tts += 1;
2505 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2506 } else if (old_active_eps != 0 &&
2507 virt_dev->tt_info->active_eps == 0) {
2508 rh_bw_info->num_active_tts -= 1;
2509 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2513 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2514 struct xhci_virt_device *virt_dev,
2515 struct xhci_container_ctx *in_ctx)
2517 struct xhci_bw_info ep_bw_info[31];
2519 struct xhci_input_control_ctx *ctrl_ctx;
2520 int old_active_eps = 0;
2522 if (virt_dev->tt_info)
2523 old_active_eps = virt_dev->tt_info->active_eps;
2525 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2527 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2532 for (i = 0; i < 31; i++) {
2533 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2536 /* Make a copy of the BW info in case we need to revert this */
2537 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2538 sizeof(ep_bw_info[i]));
2539 /* Drop the endpoint from the interval table if the endpoint is
2540 * being dropped or changed.
2542 if (EP_IS_DROPPED(ctrl_ctx, i))
2543 xhci_drop_ep_from_interval_table(xhci,
2544 &virt_dev->eps[i].bw_info,
2550 /* Overwrite the information stored in the endpoints' bw_info */
2551 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2552 for (i = 0; i < 31; i++) {
2553 /* Add any changed or added endpoints to the interval table */
2554 if (EP_IS_ADDED(ctrl_ctx, i))
2555 xhci_add_ep_to_interval_table(xhci,
2556 &virt_dev->eps[i].bw_info,
2563 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2564 /* Ok, this fits in the bandwidth we have.
2565 * Update the number of active TTs.
2567 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2571 /* We don't have enough bandwidth for this, revert the stored info. */
2572 for (i = 0; i < 31; i++) {
2573 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2576 /* Drop the new copies of any added or changed endpoints from
2577 * the interval table.
2579 if (EP_IS_ADDED(ctrl_ctx, i)) {
2580 xhci_drop_ep_from_interval_table(xhci,
2581 &virt_dev->eps[i].bw_info,
2587 /* Revert the endpoint back to its old information */
2588 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2589 sizeof(ep_bw_info[i]));
2590 /* Add any changed or dropped endpoints back into the table */
2591 if (EP_IS_DROPPED(ctrl_ctx, i))
2592 xhci_add_ep_to_interval_table(xhci,
2593 &virt_dev->eps[i].bw_info,
2603 /* Issue a configure endpoint command or evaluate context command
2604 * and wait for it to finish.
2606 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2607 struct usb_device *udev,
2608 struct xhci_command *command,
2609 bool ctx_change, bool must_succeed)
2612 unsigned long flags;
2613 struct xhci_input_control_ctx *ctrl_ctx;
2614 struct xhci_virt_device *virt_dev;
2619 spin_lock_irqsave(&xhci->lock, flags);
2620 virt_dev = xhci->devs[udev->slot_id];
2622 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2624 spin_unlock_irqrestore(&xhci->lock, flags);
2625 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2630 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2631 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2632 spin_unlock_irqrestore(&xhci->lock, flags);
2633 xhci_warn(xhci, "Not enough host resources, "
2634 "active endpoint contexts = %u\n",
2635 xhci->num_active_eps);
2638 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2639 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2640 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2641 xhci_free_host_resources(xhci, ctrl_ctx);
2642 spin_unlock_irqrestore(&xhci->lock, flags);
2643 xhci_warn(xhci, "Not enough bandwidth\n");
2648 ret = xhci_queue_configure_endpoint(xhci, command,
2649 command->in_ctx->dma,
2650 udev->slot_id, must_succeed);
2652 ret = xhci_queue_evaluate_context(xhci, command,
2653 command->in_ctx->dma,
2654 udev->slot_id, must_succeed);
2656 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2657 xhci_free_host_resources(xhci, ctrl_ctx);
2658 spin_unlock_irqrestore(&xhci->lock, flags);
2659 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2660 "FIXME allocate a new ring segment");
2663 xhci_ring_cmd_db(xhci);
2664 spin_unlock_irqrestore(&xhci->lock, flags);
2666 /* Wait for the configure endpoint command to complete */
2667 wait_for_completion(command->completion);
2670 ret = xhci_configure_endpoint_result(xhci, udev,
2673 ret = xhci_evaluate_context_result(xhci, udev,
2676 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2677 spin_lock_irqsave(&xhci->lock, flags);
2678 /* If the command failed, remove the reserved resources.
2679 * Otherwise, clean up the estimate to include dropped eps.
2682 xhci_free_host_resources(xhci, ctrl_ctx);
2684 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2685 spin_unlock_irqrestore(&xhci->lock, flags);
2690 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2691 struct xhci_virt_device *vdev, int i)
2693 struct xhci_virt_ep *ep = &vdev->eps[i];
2695 if (ep->ep_state & EP_HAS_STREAMS) {
2696 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2697 xhci_get_endpoint_address(i));
2698 xhci_free_stream_info(xhci, ep->stream_info);
2699 ep->stream_info = NULL;
2700 ep->ep_state &= ~EP_HAS_STREAMS;
2704 /* Called after one or more calls to xhci_add_endpoint() or
2705 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2706 * to call xhci_reset_bandwidth().
2708 * Since we are in the middle of changing either configuration or
2709 * installing a new alt setting, the USB core won't allow URBs to be
2710 * enqueued for any endpoint on the old config or interface. Nothing
2711 * else should be touching the xhci->devs[slot_id] structure, so we
2712 * don't need to take the xhci->lock for manipulating that.
2714 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2718 struct xhci_hcd *xhci;
2719 struct xhci_virt_device *virt_dev;
2720 struct xhci_input_control_ctx *ctrl_ctx;
2721 struct xhci_slot_ctx *slot_ctx;
2722 struct xhci_command *command;
2724 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2727 xhci = hcd_to_xhci(hcd);
2728 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2729 (xhci->xhc_state & XHCI_STATE_REMOVING))
2732 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2733 virt_dev = xhci->devs[udev->slot_id];
2735 command = xhci_alloc_command(xhci, false, true, GFP_KERNEL);
2739 command->in_ctx = virt_dev->in_ctx;
2741 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2742 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2744 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2747 goto command_cleanup;
2749 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2750 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2751 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2753 /* Don't issue the command if there's no endpoints to update. */
2754 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2755 ctrl_ctx->drop_flags == 0) {
2757 goto command_cleanup;
2759 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2760 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2761 for (i = 31; i >= 1; i--) {
2762 __le32 le32 = cpu_to_le32(BIT(i));
2764 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2765 || (ctrl_ctx->add_flags & le32) || i == 1) {
2766 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2767 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2771 xhci_dbg(xhci, "New Input Control Context:\n");
2772 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
2773 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2775 ret = xhci_configure_endpoint(xhci, udev, command,
2778 /* Callee should call reset_bandwidth() */
2779 goto command_cleanup;
2781 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
2782 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
2783 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2785 /* Free any rings that were dropped, but not changed. */
2786 for (i = 1; i < 31; ++i) {
2787 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2788 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2789 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2790 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2793 xhci_zero_in_ctx(xhci, virt_dev);
2795 * Install any rings for completely new endpoints or changed endpoints,
2796 * and free or cache any old rings from changed endpoints.
2798 for (i = 1; i < 31; ++i) {
2799 if (!virt_dev->eps[i].new_ring)
2801 /* Only cache or free the old ring if it exists.
2802 * It may not if this is the first add of an endpoint.
2804 if (virt_dev->eps[i].ring) {
2805 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2807 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2808 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2809 virt_dev->eps[i].new_ring = NULL;
2812 kfree(command->completion);
2818 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2820 struct xhci_hcd *xhci;
2821 struct xhci_virt_device *virt_dev;
2824 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2827 xhci = hcd_to_xhci(hcd);
2829 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2830 virt_dev = xhci->devs[udev->slot_id];
2831 /* Free any rings allocated for added endpoints */
2832 for (i = 0; i < 31; ++i) {
2833 if (virt_dev->eps[i].new_ring) {
2834 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2835 virt_dev->eps[i].new_ring = NULL;
2838 xhci_zero_in_ctx(xhci, virt_dev);
2841 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2842 struct xhci_container_ctx *in_ctx,
2843 struct xhci_container_ctx *out_ctx,
2844 struct xhci_input_control_ctx *ctrl_ctx,
2845 u32 add_flags, u32 drop_flags)
2847 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2848 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2849 xhci_slot_copy(xhci, in_ctx, out_ctx);
2850 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2852 xhci_dbg(xhci, "Input Context:\n");
2853 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
2856 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2857 unsigned int slot_id, unsigned int ep_index,
2858 struct xhci_dequeue_state *deq_state)
2860 struct xhci_input_control_ctx *ctrl_ctx;
2861 struct xhci_container_ctx *in_ctx;
2862 struct xhci_ep_ctx *ep_ctx;
2866 in_ctx = xhci->devs[slot_id]->in_ctx;
2867 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2869 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2874 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2875 xhci->devs[slot_id]->out_ctx, ep_index);
2876 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2877 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2878 deq_state->new_deq_ptr);
2880 xhci_warn(xhci, "WARN Cannot submit config ep after "
2881 "reset ep command\n");
2882 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2883 deq_state->new_deq_seg,
2884 deq_state->new_deq_ptr);
2887 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2889 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2890 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2891 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
2892 added_ctxs, added_ctxs);
2895 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
2896 unsigned int ep_index, struct xhci_td *td)
2898 struct xhci_dequeue_state deq_state;
2899 struct xhci_virt_ep *ep;
2900 struct usb_device *udev = td->urb->dev;
2902 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2903 "Cleaning up stalled endpoint ring");
2904 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2905 /* We need to move the HW's dequeue pointer past this TD,
2906 * or it will attempt to resend it on the next doorbell ring.
2908 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2909 ep_index, ep->stopped_stream, td, &deq_state);
2911 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
2914 /* HW with the reset endpoint quirk will use the saved dequeue state to
2915 * issue a configure endpoint command later.
2917 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2918 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2919 "Queueing new dequeue state");
2920 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2921 ep_index, ep->stopped_stream, &deq_state);
2923 /* Better hope no one uses the input context between now and the
2924 * reset endpoint completion!
2925 * XXX: No idea how this hardware will react when stream rings
2928 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2929 "Setting up input context for "
2930 "configure endpoint command");
2931 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2932 ep_index, &deq_state);
2936 /* Called when clearing halted device. The core should have sent the control
2937 * message to clear the device halt condition. The host side of the halt should
2938 * already be cleared with a reset endpoint command issued when the STALL tx
2939 * event was received.
2941 * Context: in_interrupt
2944 void xhci_endpoint_reset(struct usb_hcd *hcd,
2945 struct usb_host_endpoint *ep)
2947 struct xhci_hcd *xhci;
2949 xhci = hcd_to_xhci(hcd);
2952 * We might need to implement the config ep cmd in xhci 4.8.1 note:
2953 * The Reset Endpoint Command may only be issued to endpoints in the
2954 * Halted state. If software wishes reset the Data Toggle or Sequence
2955 * Number of an endpoint that isn't in the Halted state, then software
2956 * may issue a Configure Endpoint Command with the Drop and Add bits set
2957 * for the target endpoint. that is in the Stopped state.
2960 /* For now just print debug to follow the situation */
2961 xhci_dbg(xhci, "Endpoint 0x%x ep reset callback called\n",
2962 ep->desc.bEndpointAddress);
2965 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
2966 struct usb_device *udev, struct usb_host_endpoint *ep,
2967 unsigned int slot_id)
2970 unsigned int ep_index;
2971 unsigned int ep_state;
2975 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
2978 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
2979 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
2980 " descriptor for ep 0x%x does not support streams\n",
2981 ep->desc.bEndpointAddress);
2985 ep_index = xhci_get_endpoint_index(&ep->desc);
2986 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
2987 if (ep_state & EP_HAS_STREAMS ||
2988 ep_state & EP_GETTING_STREAMS) {
2989 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
2990 "already has streams set up.\n",
2991 ep->desc.bEndpointAddress);
2992 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
2993 "dynamic stream context array reallocation.\n");
2996 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
2997 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
2998 "endpoint 0x%x; URBs are pending.\n",
2999 ep->desc.bEndpointAddress);
3005 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3006 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3008 unsigned int max_streams;
3010 /* The stream context array size must be a power of two */
3011 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3013 * Find out how many primary stream array entries the host controller
3014 * supports. Later we may use secondary stream arrays (similar to 2nd
3015 * level page entries), but that's an optional feature for xHCI host
3016 * controllers. xHCs must support at least 4 stream IDs.
3018 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3019 if (*num_stream_ctxs > max_streams) {
3020 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3022 *num_stream_ctxs = max_streams;
3023 *num_streams = max_streams;
3027 /* Returns an error code if one of the endpoint already has streams.
3028 * This does not change any data structures, it only checks and gathers
3031 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3032 struct usb_device *udev,
3033 struct usb_host_endpoint **eps, unsigned int num_eps,
3034 unsigned int *num_streams, u32 *changed_ep_bitmask)
3036 unsigned int max_streams;
3037 unsigned int endpoint_flag;
3041 for (i = 0; i < num_eps; i++) {
3042 ret = xhci_check_streams_endpoint(xhci, udev,
3043 eps[i], udev->slot_id);
3047 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3048 if (max_streams < (*num_streams - 1)) {
3049 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3050 eps[i]->desc.bEndpointAddress,
3052 *num_streams = max_streams+1;
3055 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3056 if (*changed_ep_bitmask & endpoint_flag)
3058 *changed_ep_bitmask |= endpoint_flag;
3063 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3064 struct usb_device *udev,
3065 struct usb_host_endpoint **eps, unsigned int num_eps)
3067 u32 changed_ep_bitmask = 0;
3068 unsigned int slot_id;
3069 unsigned int ep_index;
3070 unsigned int ep_state;
3073 slot_id = udev->slot_id;
3074 if (!xhci->devs[slot_id])
3077 for (i = 0; i < num_eps; i++) {
3078 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3079 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3080 /* Are streams already being freed for the endpoint? */
3081 if (ep_state & EP_GETTING_NO_STREAMS) {
3082 xhci_warn(xhci, "WARN Can't disable streams for "
3084 "streams are being disabled already\n",
3085 eps[i]->desc.bEndpointAddress);
3088 /* Are there actually any streams to free? */
3089 if (!(ep_state & EP_HAS_STREAMS) &&
3090 !(ep_state & EP_GETTING_STREAMS)) {
3091 xhci_warn(xhci, "WARN Can't disable streams for "
3093 "streams are already disabled!\n",
3094 eps[i]->desc.bEndpointAddress);
3095 xhci_warn(xhci, "WARN xhci_free_streams() called "
3096 "with non-streams endpoint\n");
3099 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3101 return changed_ep_bitmask;
3105 * The USB device drivers use this function (through the HCD interface in USB
3106 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3107 * coordinate mass storage command queueing across multiple endpoints (basically
3108 * a stream ID == a task ID).
3110 * Setting up streams involves allocating the same size stream context array
3111 * for each endpoint and issuing a configure endpoint command for all endpoints.
3113 * Don't allow the call to succeed if one endpoint only supports one stream
3114 * (which means it doesn't support streams at all).
3116 * Drivers may get less stream IDs than they asked for, if the host controller
3117 * hardware or endpoints claim they can't support the number of requested
3120 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3121 struct usb_host_endpoint **eps, unsigned int num_eps,
3122 unsigned int num_streams, gfp_t mem_flags)
3125 struct xhci_hcd *xhci;
3126 struct xhci_virt_device *vdev;
3127 struct xhci_command *config_cmd;
3128 struct xhci_input_control_ctx *ctrl_ctx;
3129 unsigned int ep_index;
3130 unsigned int num_stream_ctxs;
3131 unsigned int max_packet;
3132 unsigned long flags;
3133 u32 changed_ep_bitmask = 0;
3138 /* Add one to the number of streams requested to account for
3139 * stream 0 that is reserved for xHCI usage.
3142 xhci = hcd_to_xhci(hcd);
3143 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3146 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3147 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3148 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3149 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3153 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
3155 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
3158 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3160 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3162 xhci_free_command(xhci, config_cmd);
3166 /* Check to make sure all endpoints are not already configured for
3167 * streams. While we're at it, find the maximum number of streams that
3168 * all the endpoints will support and check for duplicate endpoints.
3170 spin_lock_irqsave(&xhci->lock, flags);
3171 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3172 num_eps, &num_streams, &changed_ep_bitmask);
3174 xhci_free_command(xhci, config_cmd);
3175 spin_unlock_irqrestore(&xhci->lock, flags);
3178 if (num_streams <= 1) {
3179 xhci_warn(xhci, "WARN: endpoints can't handle "
3180 "more than one stream.\n");
3181 xhci_free_command(xhci, config_cmd);
3182 spin_unlock_irqrestore(&xhci->lock, flags);
3185 vdev = xhci->devs[udev->slot_id];
3186 /* Mark each endpoint as being in transition, so
3187 * xhci_urb_enqueue() will reject all URBs.
3189 for (i = 0; i < num_eps; i++) {
3190 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3191 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3193 spin_unlock_irqrestore(&xhci->lock, flags);
3195 /* Setup internal data structures and allocate HW data structures for
3196 * streams (but don't install the HW structures in the input context
3197 * until we're sure all memory allocation succeeded).
3199 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3200 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3201 num_stream_ctxs, num_streams);
3203 for (i = 0; i < num_eps; i++) {
3204 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3205 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&eps[i]->desc));
3206 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3209 max_packet, mem_flags);
3210 if (!vdev->eps[ep_index].stream_info)
3212 /* Set maxPstreams in endpoint context and update deq ptr to
3213 * point to stream context array. FIXME
3217 /* Set up the input context for a configure endpoint command. */
3218 for (i = 0; i < num_eps; i++) {
3219 struct xhci_ep_ctx *ep_ctx;
3221 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3222 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3224 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3225 vdev->out_ctx, ep_index);
3226 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3227 vdev->eps[ep_index].stream_info);
3229 /* Tell the HW to drop its old copy of the endpoint context info
3230 * and add the updated copy from the input context.
3232 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3233 vdev->out_ctx, ctrl_ctx,
3234 changed_ep_bitmask, changed_ep_bitmask);
3236 /* Issue and wait for the configure endpoint command */
3237 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3240 /* xHC rejected the configure endpoint command for some reason, so we
3241 * leave the old ring intact and free our internal streams data
3247 spin_lock_irqsave(&xhci->lock, flags);
3248 for (i = 0; i < num_eps; i++) {
3249 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3250 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3251 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3252 udev->slot_id, ep_index);
3253 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3255 xhci_free_command(xhci, config_cmd);
3256 spin_unlock_irqrestore(&xhci->lock, flags);
3258 /* Subtract 1 for stream 0, which drivers can't use */
3259 return num_streams - 1;
3262 /* If it didn't work, free the streams! */
3263 for (i = 0; i < num_eps; i++) {
3264 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3265 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3266 vdev->eps[ep_index].stream_info = NULL;
3267 /* FIXME Unset maxPstreams in endpoint context and
3268 * update deq ptr to point to normal string ring.
3270 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3271 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3272 xhci_endpoint_zero(xhci, vdev, eps[i]);
3274 xhci_free_command(xhci, config_cmd);
3278 /* Transition the endpoint from using streams to being a "normal" endpoint
3281 * Modify the endpoint context state, submit a configure endpoint command,
3282 * and free all endpoint rings for streams if that completes successfully.
3284 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3285 struct usb_host_endpoint **eps, unsigned int num_eps,
3289 struct xhci_hcd *xhci;
3290 struct xhci_virt_device *vdev;
3291 struct xhci_command *command;
3292 struct xhci_input_control_ctx *ctrl_ctx;
3293 unsigned int ep_index;
3294 unsigned long flags;
3295 u32 changed_ep_bitmask;
3297 xhci = hcd_to_xhci(hcd);
3298 vdev = xhci->devs[udev->slot_id];
3300 /* Set up a configure endpoint command to remove the streams rings */
3301 spin_lock_irqsave(&xhci->lock, flags);
3302 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3303 udev, eps, num_eps);
3304 if (changed_ep_bitmask == 0) {
3305 spin_unlock_irqrestore(&xhci->lock, flags);
3309 /* Use the xhci_command structure from the first endpoint. We may have
3310 * allocated too many, but the driver may call xhci_free_streams() for
3311 * each endpoint it grouped into one call to xhci_alloc_streams().
3313 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3314 command = vdev->eps[ep_index].stream_info->free_streams_command;
3315 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3317 spin_unlock_irqrestore(&xhci->lock, flags);
3318 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3323 for (i = 0; i < num_eps; i++) {
3324 struct xhci_ep_ctx *ep_ctx;
3326 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3327 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3328 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3329 EP_GETTING_NO_STREAMS;
3331 xhci_endpoint_copy(xhci, command->in_ctx,
3332 vdev->out_ctx, ep_index);
3333 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3334 &vdev->eps[ep_index]);
3336 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3337 vdev->out_ctx, ctrl_ctx,
3338 changed_ep_bitmask, changed_ep_bitmask);
3339 spin_unlock_irqrestore(&xhci->lock, flags);
3341 /* Issue and wait for the configure endpoint command,
3342 * which must succeed.
3344 ret = xhci_configure_endpoint(xhci, udev, command,
3347 /* xHC rejected the configure endpoint command for some reason, so we
3348 * leave the streams rings intact.
3353 spin_lock_irqsave(&xhci->lock, flags);
3354 for (i = 0; i < num_eps; i++) {
3355 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3356 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3357 vdev->eps[ep_index].stream_info = NULL;
3358 /* FIXME Unset maxPstreams in endpoint context and
3359 * update deq ptr to point to normal string ring.
3361 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3362 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3364 spin_unlock_irqrestore(&xhci->lock, flags);
3370 * Deletes endpoint resources for endpoints that were active before a Reset
3371 * Device command, or a Disable Slot command. The Reset Device command leaves
3372 * the control endpoint intact, whereas the Disable Slot command deletes it.
3374 * Must be called with xhci->lock held.
3376 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3377 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3380 unsigned int num_dropped_eps = 0;
3381 unsigned int drop_flags = 0;
3383 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3384 if (virt_dev->eps[i].ring) {
3385 drop_flags |= 1 << i;
3389 xhci->num_active_eps -= num_dropped_eps;
3390 if (num_dropped_eps)
3391 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3392 "Dropped %u ep ctxs, flags = 0x%x, "
3394 num_dropped_eps, drop_flags,
3395 xhci->num_active_eps);
3399 * This submits a Reset Device Command, which will set the device state to 0,
3400 * set the device address to 0, and disable all the endpoints except the default
3401 * control endpoint. The USB core should come back and call
3402 * xhci_address_device(), and then re-set up the configuration. If this is
3403 * called because of a usb_reset_and_verify_device(), then the old alternate
3404 * settings will be re-installed through the normal bandwidth allocation
3407 * Wait for the Reset Device command to finish. Remove all structures
3408 * associated with the endpoints that were disabled. Clear the input device
3409 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
3411 * If the virt_dev to be reset does not exist or does not match the udev,
3412 * it means the device is lost, possibly due to the xHC restore error and
3413 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3414 * re-allocate the device.
3416 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
3419 unsigned long flags;
3420 struct xhci_hcd *xhci;
3421 unsigned int slot_id;
3422 struct xhci_virt_device *virt_dev;
3423 struct xhci_command *reset_device_cmd;
3424 int last_freed_endpoint;
3425 struct xhci_slot_ctx *slot_ctx;
3426 int old_active_eps = 0;
3428 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3431 xhci = hcd_to_xhci(hcd);
3432 slot_id = udev->slot_id;
3433 virt_dev = xhci->devs[slot_id];
3435 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3436 "not exist. Re-allocate the device\n", slot_id);
3437 ret = xhci_alloc_dev(hcd, udev);
3444 if (virt_dev->tt_info)
3445 old_active_eps = virt_dev->tt_info->active_eps;
3447 if (virt_dev->udev != udev) {
3448 /* If the virt_dev and the udev does not match, this virt_dev
3449 * may belong to another udev.
3450 * Re-allocate the device.
3452 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3453 "not match the udev. Re-allocate the device\n",
3455 ret = xhci_alloc_dev(hcd, udev);
3462 /* If device is not setup, there is no point in resetting it */
3463 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3464 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3465 SLOT_STATE_DISABLED)
3468 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3469 /* Allocate the command structure that holds the struct completion.
3470 * Assume we're in process context, since the normal device reset
3471 * process has to wait for the device anyway. Storage devices are
3472 * reset as part of error handling, so use GFP_NOIO instead of
3475 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3476 if (!reset_device_cmd) {
3477 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3481 /* Attempt to submit the Reset Device command to the command ring */
3482 spin_lock_irqsave(&xhci->lock, flags);
3484 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3486 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3487 spin_unlock_irqrestore(&xhci->lock, flags);
3488 goto command_cleanup;
3490 xhci_ring_cmd_db(xhci);
3491 spin_unlock_irqrestore(&xhci->lock, flags);
3493 /* Wait for the Reset Device command to finish */
3494 wait_for_completion(reset_device_cmd->completion);
3496 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3497 * unless we tried to reset a slot ID that wasn't enabled,
3498 * or the device wasn't in the addressed or configured state.
3500 ret = reset_device_cmd->status;
3502 case COMP_CMD_ABORT:
3504 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3506 goto command_cleanup;
3507 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
3508 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
3509 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3511 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3512 xhci_dbg(xhci, "Not freeing device rings.\n");
3513 /* Don't treat this as an error. May change my mind later. */
3515 goto command_cleanup;
3517 xhci_dbg(xhci, "Successful reset device command.\n");
3520 if (xhci_is_vendor_info_code(xhci, ret))
3522 xhci_warn(xhci, "Unknown completion code %u for "
3523 "reset device command.\n", ret);
3525 goto command_cleanup;
3528 /* Free up host controller endpoint resources */
3529 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3530 spin_lock_irqsave(&xhci->lock, flags);
3531 /* Don't delete the default control endpoint resources */
3532 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3533 spin_unlock_irqrestore(&xhci->lock, flags);
3536 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
3537 last_freed_endpoint = 1;
3538 for (i = 1; i < 31; ++i) {
3539 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3541 if (ep->ep_state & EP_HAS_STREAMS) {
3542 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3543 xhci_get_endpoint_address(i));
3544 xhci_free_stream_info(xhci, ep->stream_info);
3545 ep->stream_info = NULL;
3546 ep->ep_state &= ~EP_HAS_STREAMS;
3550 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
3551 last_freed_endpoint = i;
3553 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3554 xhci_drop_ep_from_interval_table(xhci,
3555 &virt_dev->eps[i].bw_info,
3560 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3562 /* If necessary, update the number of active TTs on this root port */
3563 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3565 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
3566 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
3570 xhci_free_command(xhci, reset_device_cmd);
3575 * At this point, the struct usb_device is about to go away, the device has
3576 * disconnected, and all traffic has been stopped and the endpoints have been
3577 * disabled. Free any HC data structures associated with that device.
3579 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3581 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3582 struct xhci_virt_device *virt_dev;
3583 unsigned long flags;
3586 struct xhci_command *command;
3588 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3592 #ifndef CONFIG_USB_DEFAULT_PERSIST
3594 * We called pm_runtime_get_noresume when the device was attached.
3595 * Decrement the counter here to allow controller to runtime suspend
3596 * if no devices remain.
3598 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3599 pm_runtime_put_noidle(hcd->self.controller);
3602 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3603 /* If the host is halted due to driver unload, we still need to free the
3606 if (ret <= 0 && ret != -ENODEV) {
3611 virt_dev = xhci->devs[udev->slot_id];
3613 /* Stop any wayward timer functions (which may grab the lock) */
3614 for (i = 0; i < 31; ++i) {
3615 virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
3616 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3619 spin_lock_irqsave(&xhci->lock, flags);
3620 /* Don't disable the slot if the host controller is dead. */
3621 state = readl(&xhci->op_regs->status);
3622 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3623 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3624 xhci_free_virt_device(xhci, udev->slot_id);
3625 spin_unlock_irqrestore(&xhci->lock, flags);
3630 if (xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3632 spin_unlock_irqrestore(&xhci->lock, flags);
3633 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3636 xhci_ring_cmd_db(xhci);
3637 spin_unlock_irqrestore(&xhci->lock, flags);
3640 * Event command completion handler will free any data structures
3641 * associated with the slot. XXX Can free sleep?
3646 * Checks if we have enough host controller resources for the default control
3649 * Must be called with xhci->lock held.
3651 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3653 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3654 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3655 "Not enough ep ctxs: "
3656 "%u active, need to add 1, limit is %u.",
3657 xhci->num_active_eps, xhci->limit_active_eps);
3660 xhci->num_active_eps += 1;
3661 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3662 "Adding 1 ep ctx, %u now active.",
3663 xhci->num_active_eps);
3669 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3670 * timed out, or allocating memory failed. Returns 1 on success.
3672 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3674 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3675 unsigned long flags;
3677 struct xhci_command *command;
3679 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3683 /* xhci->slot_id and xhci->addr_dev are not thread-safe */
3684 mutex_lock(&xhci->mutex);
3685 spin_lock_irqsave(&xhci->lock, flags);
3686 command->completion = &xhci->addr_dev;
3687 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3689 spin_unlock_irqrestore(&xhci->lock, flags);
3690 mutex_unlock(&xhci->mutex);
3691 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3695 xhci_ring_cmd_db(xhci);
3696 spin_unlock_irqrestore(&xhci->lock, flags);
3698 wait_for_completion(command->completion);
3699 slot_id = xhci->slot_id;
3700 mutex_unlock(&xhci->mutex);
3702 if (!slot_id || command->status != COMP_SUCCESS) {
3703 xhci_err(xhci, "Error while assigning device slot ID\n");
3704 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3706 readl(&xhci->cap_regs->hcs_params1)));
3711 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3712 spin_lock_irqsave(&xhci->lock, flags);
3713 ret = xhci_reserve_host_control_ep_resources(xhci);
3715 spin_unlock_irqrestore(&xhci->lock, flags);
3716 xhci_warn(xhci, "Not enough host resources, "
3717 "active endpoint contexts = %u\n",
3718 xhci->num_active_eps);
3721 spin_unlock_irqrestore(&xhci->lock, flags);
3723 /* Use GFP_NOIO, since this function can be called from
3724 * xhci_discover_or_reset_device(), which may be called as part of
3725 * mass storage driver error handling.
3727 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
3728 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3731 udev->slot_id = slot_id;
3733 #ifndef CONFIG_USB_DEFAULT_PERSIST
3735 * If resetting upon resume, we can't put the controller into runtime
3736 * suspend if there is a device attached.
3738 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3739 pm_runtime_get_noresume(hcd->self.controller);
3744 /* Is this a LS or FS device under a HS hub? */
3745 /* Hub or peripherial? */
3749 /* Disable slot, if we can do it without mem alloc */
3750 spin_lock_irqsave(&xhci->lock, flags);
3751 command->completion = NULL;
3752 command->status = 0;
3753 if (!xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3755 xhci_ring_cmd_db(xhci);
3756 spin_unlock_irqrestore(&xhci->lock, flags);
3761 * Issue an Address Device command and optionally send a corresponding
3762 * SetAddress request to the device.
3764 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3765 enum xhci_setup_dev setup)
3767 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
3768 unsigned long flags;
3769 struct xhci_virt_device *virt_dev;
3771 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3772 struct xhci_slot_ctx *slot_ctx;
3773 struct xhci_input_control_ctx *ctrl_ctx;
3775 struct xhci_command *command = NULL;
3777 mutex_lock(&xhci->mutex);
3779 if (xhci->xhc_state) { /* dying, removing or halted */
3784 if (!udev->slot_id) {
3785 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3786 "Bad Slot ID %d", udev->slot_id);
3791 virt_dev = xhci->devs[udev->slot_id];
3793 if (WARN_ON(!virt_dev)) {
3795 * In plug/unplug torture test with an NEC controller,
3796 * a zero-dereference was observed once due to virt_dev = 0.
3797 * Print useful debug rather than crash if it is observed again!
3799 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3805 if (setup == SETUP_CONTEXT_ONLY) {
3806 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3807 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3808 SLOT_STATE_DEFAULT) {
3809 xhci_dbg(xhci, "Slot already in default state\n");
3814 command = xhci_alloc_command(xhci, false, false, GFP_KERNEL);
3820 command->in_ctx = virt_dev->in_ctx;
3821 command->completion = &xhci->addr_dev;
3823 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3824 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
3826 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3832 * If this is the first Set Address since device plug-in or
3833 * virt_device realloaction after a resume with an xHCI power loss,
3834 * then set up the slot context.
3836 if (!slot_ctx->dev_info)
3837 xhci_setup_addressable_virt_dev(xhci, udev);
3838 /* Otherwise, update the control endpoint ring enqueue pointer. */
3840 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3841 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3842 ctrl_ctx->drop_flags = 0;
3844 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3845 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3846 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3847 le32_to_cpu(slot_ctx->dev_info) >> 27);
3849 spin_lock_irqsave(&xhci->lock, flags);
3850 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
3851 udev->slot_id, setup);
3853 spin_unlock_irqrestore(&xhci->lock, flags);
3854 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3855 "FIXME: allocate a command ring segment");
3858 xhci_ring_cmd_db(xhci);
3859 spin_unlock_irqrestore(&xhci->lock, flags);
3861 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3862 wait_for_completion(command->completion);
3864 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3865 * the SetAddress() "recovery interval" required by USB and aborting the
3866 * command on a timeout.
3868 switch (command->status) {
3869 case COMP_CMD_ABORT:
3871 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
3874 case COMP_CTX_STATE:
3876 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
3877 act, udev->slot_id);
3881 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
3885 dev_warn(&udev->dev,
3886 "ERROR: Incompatible device for setup %s command\n", act);
3890 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3891 "Successful setup %s command", act);
3895 "ERROR: unexpected setup %s command completion code 0x%x.\n",
3896 act, command->status);
3897 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3898 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3899 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
3905 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3906 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3907 "Op regs DCBAA ptr = %#016llx", temp_64);
3908 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3909 "Slot ID %d dcbaa entry @%p = %#016llx",
3911 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3912 (unsigned long long)
3913 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
3914 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3915 "Output Context DMA address = %#08llx",
3916 (unsigned long long)virt_dev->out_ctx->dma);
3917 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3918 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3919 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3920 le32_to_cpu(slot_ctx->dev_info) >> 27);
3921 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3922 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3924 * USB core uses address 1 for the roothubs, so we add one to the
3925 * address given back to us by the HC.
3927 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3928 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
3929 le32_to_cpu(slot_ctx->dev_info) >> 27);
3930 /* Zero the input context control for later use */
3931 ctrl_ctx->add_flags = 0;
3932 ctrl_ctx->drop_flags = 0;
3934 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3935 "Internal device address = %d",
3936 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
3938 mutex_unlock(&xhci->mutex);
3943 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
3945 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
3948 int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
3950 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
3954 * Transfer the port index into real index in the HW port status
3955 * registers. Caculate offset between the port's PORTSC register
3956 * and port status base. Divide the number of per port register
3957 * to get the real index. The raw port number bases 1.
3959 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
3961 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3962 __le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
3963 __le32 __iomem *addr;
3966 if (hcd->speed < HCD_USB3)
3967 addr = xhci->usb2_ports[port1 - 1];
3969 addr = xhci->usb3_ports[port1 - 1];
3971 raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
3976 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
3977 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
3979 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
3980 struct usb_device *udev, u16 max_exit_latency)
3982 struct xhci_virt_device *virt_dev;
3983 struct xhci_command *command;
3984 struct xhci_input_control_ctx *ctrl_ctx;
3985 struct xhci_slot_ctx *slot_ctx;
3986 unsigned long flags;
3989 spin_lock_irqsave(&xhci->lock, flags);
3991 virt_dev = xhci->devs[udev->slot_id];
3994 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
3995 * xHC was re-initialized. Exit latency will be set later after
3996 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
3999 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4000 spin_unlock_irqrestore(&xhci->lock, flags);
4004 /* Attempt to issue an Evaluate Context command to change the MEL. */
4005 command = xhci->lpm_command;
4006 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4008 spin_unlock_irqrestore(&xhci->lock, flags);
4009 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4014 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4015 spin_unlock_irqrestore(&xhci->lock, flags);
4017 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4018 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4019 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4020 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4021 slot_ctx->dev_state = 0;
4023 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4024 "Set up evaluate context for LPM MEL change.");
4025 xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id);
4026 xhci_dbg_ctx(xhci, command->in_ctx, 0);
4028 /* Issue and wait for the evaluate context command. */
4029 ret = xhci_configure_endpoint(xhci, udev, command,
4031 xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id);
4032 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0);
4035 spin_lock_irqsave(&xhci->lock, flags);
4036 virt_dev->current_mel = max_exit_latency;
4037 spin_unlock_irqrestore(&xhci->lock, flags);
4044 /* BESL to HIRD Encoding array for USB2 LPM */
4045 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4046 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4048 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4049 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4050 struct usb_device *udev)
4052 int u2del, besl, besl_host;
4053 int besl_device = 0;
4056 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4057 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4059 if (field & USB_BESL_SUPPORT) {
4060 for (besl_host = 0; besl_host < 16; besl_host++) {
4061 if (xhci_besl_encoding[besl_host] >= u2del)
4064 /* Use baseline BESL value as default */
4065 if (field & USB_BESL_BASELINE_VALID)
4066 besl_device = USB_GET_BESL_BASELINE(field);
4067 else if (field & USB_BESL_DEEP_VALID)
4068 besl_device = USB_GET_BESL_DEEP(field);
4073 besl_host = (u2del - 51) / 75 + 1;
4076 besl = besl_host + besl_device;
4083 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4084 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4091 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4093 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4094 l1 = udev->l1_params.timeout / 256;
4096 /* device has preferred BESLD */
4097 if (field & USB_BESL_DEEP_VALID) {
4098 besld = USB_GET_BESL_DEEP(field);
4102 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4105 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4106 struct usb_device *udev, int enable)
4108 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4109 __le32 __iomem **port_array;
4110 __le32 __iomem *pm_addr, *hlpm_addr;
4111 u32 pm_val, hlpm_val, field;
4112 unsigned int port_num;
4113 unsigned long flags;
4114 int hird, exit_latency;
4117 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4121 if (!udev->parent || udev->parent->parent ||
4122 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4125 if (udev->usb2_hw_lpm_capable != 1)
4128 spin_lock_irqsave(&xhci->lock, flags);
4130 port_array = xhci->usb2_ports;
4131 port_num = udev->portnum - 1;
4132 pm_addr = port_array[port_num] + PORTPMSC;
4133 pm_val = readl(pm_addr);
4134 hlpm_addr = port_array[port_num] + PORTHLPMC;
4135 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4137 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4138 enable ? "enable" : "disable", port_num + 1);
4141 /* Host supports BESL timeout instead of HIRD */
4142 if (udev->usb2_hw_lpm_besl_capable) {
4143 /* if device doesn't have a preferred BESL value use a
4144 * default one which works with mixed HIRD and BESL
4145 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4147 if ((field & USB_BESL_SUPPORT) &&
4148 (field & USB_BESL_BASELINE_VALID))
4149 hird = USB_GET_BESL_BASELINE(field);
4151 hird = udev->l1_params.besl;
4153 exit_latency = xhci_besl_encoding[hird];
4154 spin_unlock_irqrestore(&xhci->lock, flags);
4156 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4157 * input context for link powermanagement evaluate
4158 * context commands. It is protected by hcd->bandwidth
4159 * mutex and is shared by all devices. We need to set
4160 * the max ext latency in USB 2 BESL LPM as well, so
4161 * use the same mutex and xhci_change_max_exit_latency()
4163 mutex_lock(hcd->bandwidth_mutex);
4164 ret = xhci_change_max_exit_latency(xhci, udev,
4166 mutex_unlock(hcd->bandwidth_mutex);
4170 spin_lock_irqsave(&xhci->lock, flags);
4172 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4173 writel(hlpm_val, hlpm_addr);
4177 hird = xhci_calculate_hird_besl(xhci, udev);
4180 pm_val &= ~PORT_HIRD_MASK;
4181 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4182 writel(pm_val, pm_addr);
4183 pm_val = readl(pm_addr);
4185 writel(pm_val, pm_addr);
4189 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4190 writel(pm_val, pm_addr);
4193 if (udev->usb2_hw_lpm_besl_capable) {
4194 spin_unlock_irqrestore(&xhci->lock, flags);
4195 mutex_lock(hcd->bandwidth_mutex);
4196 xhci_change_max_exit_latency(xhci, udev, 0);
4197 mutex_unlock(hcd->bandwidth_mutex);
4202 spin_unlock_irqrestore(&xhci->lock, flags);
4206 /* check if a usb2 port supports a given extened capability protocol
4207 * only USB2 ports extended protocol capability values are cached.
4208 * Return 1 if capability is supported
4210 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4211 unsigned capability)
4213 u32 port_offset, port_count;
4216 for (i = 0; i < xhci->num_ext_caps; i++) {
4217 if (xhci->ext_caps[i] & capability) {
4218 /* port offsets starts at 1 */
4219 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4220 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4221 if (port >= port_offset &&
4222 port < port_offset + port_count)
4229 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4231 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4232 int portnum = udev->portnum - 1;
4234 if (hcd->speed >= HCD_USB3 || !xhci->sw_lpm_support ||
4238 /* we only support lpm for non-hub device connected to root hub yet */
4239 if (!udev->parent || udev->parent->parent ||
4240 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4243 if (xhci->hw_lpm_support == 1 &&
4244 xhci_check_usb2_port_capability(
4245 xhci, portnum, XHCI_HLC)) {
4246 udev->usb2_hw_lpm_capable = 1;
4247 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4248 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4249 if (xhci_check_usb2_port_capability(xhci, portnum,
4251 udev->usb2_hw_lpm_besl_capable = 1;
4257 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4259 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4260 static unsigned long long xhci_service_interval_to_ns(
4261 struct usb_endpoint_descriptor *desc)
4263 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4266 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4267 enum usb3_link_state state)
4269 unsigned long long sel;
4270 unsigned long long pel;
4271 unsigned int max_sel_pel;
4276 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4277 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4278 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4279 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4283 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4284 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4285 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4289 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4291 return USB3_LPM_DISABLED;
4294 if (sel <= max_sel_pel && pel <= max_sel_pel)
4295 return USB3_LPM_DEVICE_INITIATED;
4297 if (sel > max_sel_pel)
4298 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4299 "due to long SEL %llu ms\n",
4302 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4303 "due to long PEL %llu ms\n",
4305 return USB3_LPM_DISABLED;
4308 /* The U1 timeout should be the maximum of the following values:
4309 * - For control endpoints, U1 system exit latency (SEL) * 3
4310 * - For bulk endpoints, U1 SEL * 5
4311 * - For interrupt endpoints:
4312 * - Notification EPs, U1 SEL * 3
4313 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4314 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4316 static unsigned long long xhci_calculate_intel_u1_timeout(
4317 struct usb_device *udev,
4318 struct usb_endpoint_descriptor *desc)
4320 unsigned long long timeout_ns;
4324 ep_type = usb_endpoint_type(desc);
4326 case USB_ENDPOINT_XFER_CONTROL:
4327 timeout_ns = udev->u1_params.sel * 3;
4329 case USB_ENDPOINT_XFER_BULK:
4330 timeout_ns = udev->u1_params.sel * 5;
4332 case USB_ENDPOINT_XFER_INT:
4333 intr_type = usb_endpoint_interrupt_type(desc);
4334 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4335 timeout_ns = udev->u1_params.sel * 3;
4338 /* Otherwise the calculation is the same as isoc eps */
4339 case USB_ENDPOINT_XFER_ISOC:
4340 timeout_ns = xhci_service_interval_to_ns(desc);
4341 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4342 if (timeout_ns < udev->u1_params.sel * 2)
4343 timeout_ns = udev->u1_params.sel * 2;
4352 /* Returns the hub-encoded U1 timeout value. */
4353 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4354 struct usb_device *udev,
4355 struct usb_endpoint_descriptor *desc)
4357 unsigned long long timeout_ns;
4359 if (xhci->quirks & XHCI_INTEL_HOST)
4360 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4362 timeout_ns = udev->u1_params.sel;
4364 /* The U1 timeout is encoded in 1us intervals.
4365 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4367 if (timeout_ns == USB3_LPM_DISABLED)
4370 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4372 /* If the necessary timeout value is bigger than what we can set in the
4373 * USB 3.0 hub, we have to disable hub-initiated U1.
4375 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4377 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4378 "due to long timeout %llu ms\n", timeout_ns);
4379 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4382 /* The U2 timeout should be the maximum of:
4383 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4384 * - largest bInterval of any active periodic endpoint (to avoid going
4385 * into lower power link states between intervals).
4386 * - the U2 Exit Latency of the device
4388 static unsigned long long xhci_calculate_intel_u2_timeout(
4389 struct usb_device *udev,
4390 struct usb_endpoint_descriptor *desc)
4392 unsigned long long timeout_ns;
4393 unsigned long long u2_del_ns;
4395 timeout_ns = 10 * 1000 * 1000;
4397 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4398 (xhci_service_interval_to_ns(desc) > timeout_ns))
4399 timeout_ns = xhci_service_interval_to_ns(desc);
4401 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4402 if (u2_del_ns > timeout_ns)
4403 timeout_ns = u2_del_ns;
4408 /* Returns the hub-encoded U2 timeout value. */
4409 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4410 struct usb_device *udev,
4411 struct usb_endpoint_descriptor *desc)
4413 unsigned long long timeout_ns;
4415 if (xhci->quirks & XHCI_INTEL_HOST)
4416 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4418 timeout_ns = udev->u2_params.sel;
4420 /* The U2 timeout is encoded in 256us intervals */
4421 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4422 /* If the necessary timeout value is bigger than what we can set in the
4423 * USB 3.0 hub, we have to disable hub-initiated U2.
4425 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4427 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4428 "due to long timeout %llu ms\n", timeout_ns);
4429 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4432 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4433 struct usb_device *udev,
4434 struct usb_endpoint_descriptor *desc,
4435 enum usb3_link_state state,
4438 if (state == USB3_LPM_U1)
4439 return xhci_calculate_u1_timeout(xhci, udev, desc);
4440 else if (state == USB3_LPM_U2)
4441 return xhci_calculate_u2_timeout(xhci, udev, desc);
4443 return USB3_LPM_DISABLED;
4446 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4447 struct usb_device *udev,
4448 struct usb_endpoint_descriptor *desc,
4449 enum usb3_link_state state,
4454 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4455 desc, state, timeout);
4457 /* If we found we can't enable hub-initiated LPM, or
4458 * the U1 or U2 exit latency was too high to allow
4459 * device-initiated LPM as well, just stop searching.
4461 if (alt_timeout == USB3_LPM_DISABLED ||
4462 alt_timeout == USB3_LPM_DEVICE_INITIATED) {
4463 *timeout = alt_timeout;
4466 if (alt_timeout > *timeout)
4467 *timeout = alt_timeout;
4471 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4472 struct usb_device *udev,
4473 struct usb_host_interface *alt,
4474 enum usb3_link_state state,
4479 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4480 if (xhci_update_timeout_for_endpoint(xhci, udev,
4481 &alt->endpoint[j].desc, state, timeout))
4488 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4489 enum usb3_link_state state)
4491 struct usb_device *parent;
4492 unsigned int num_hubs;
4494 if (state == USB3_LPM_U2)
4497 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4498 for (parent = udev->parent, num_hubs = 0; parent->parent;
4499 parent = parent->parent)
4505 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4506 " below second-tier hub.\n");
4507 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4508 "to decrease power consumption.\n");
4512 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4513 struct usb_device *udev,
4514 enum usb3_link_state state)
4516 if (xhci->quirks & XHCI_INTEL_HOST)
4517 return xhci_check_intel_tier_policy(udev, state);
4522 /* Returns the U1 or U2 timeout that should be enabled.
4523 * If the tier check or timeout setting functions return with a non-zero exit
4524 * code, that means the timeout value has been finalized and we shouldn't look
4525 * at any more endpoints.
4527 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4528 struct usb_device *udev, enum usb3_link_state state)
4530 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4531 struct usb_host_config *config;
4534 u16 timeout = USB3_LPM_DISABLED;
4536 if (state == USB3_LPM_U1)
4538 else if (state == USB3_LPM_U2)
4541 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4546 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4549 /* Gather some information about the currently installed configuration
4550 * and alternate interface settings.
4552 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4556 config = udev->actconfig;
4560 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4561 struct usb_driver *driver;
4562 struct usb_interface *intf = config->interface[i];
4567 /* Check if any currently bound drivers want hub-initiated LPM
4570 if (intf->dev.driver) {
4571 driver = to_usb_driver(intf->dev.driver);
4572 if (driver && driver->disable_hub_initiated_lpm) {
4573 dev_dbg(&udev->dev, "Hub-initiated %s disabled "
4574 "at request of driver %s\n",
4575 state_name, driver->name);
4576 return xhci_get_timeout_no_hub_lpm(udev, state);
4580 /* Not sure how this could happen... */
4581 if (!intf->cur_altsetting)
4584 if (xhci_update_timeout_for_interface(xhci, udev,
4585 intf->cur_altsetting,
4592 static int calculate_max_exit_latency(struct usb_device *udev,
4593 enum usb3_link_state state_changed,
4594 u16 hub_encoded_timeout)
4596 unsigned long long u1_mel_us = 0;
4597 unsigned long long u2_mel_us = 0;
4598 unsigned long long mel_us = 0;
4604 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4605 hub_encoded_timeout == USB3_LPM_DISABLED);
4606 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4607 hub_encoded_timeout == USB3_LPM_DISABLED);
4609 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4610 hub_encoded_timeout != USB3_LPM_DISABLED);
4611 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4612 hub_encoded_timeout != USB3_LPM_DISABLED);
4614 /* If U1 was already enabled and we're not disabling it,
4615 * or we're going to enable U1, account for the U1 max exit latency.
4617 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4619 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4620 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4622 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4624 if (u1_mel_us > u2_mel_us)
4628 /* xHCI host controller max exit latency field is only 16 bits wide. */
4629 if (mel_us > MAX_EXIT) {
4630 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4631 "is too big.\n", mel_us);
4637 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4638 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4639 struct usb_device *udev, enum usb3_link_state state)
4641 struct xhci_hcd *xhci;
4642 u16 hub_encoded_timeout;
4646 xhci = hcd_to_xhci(hcd);
4647 /* The LPM timeout values are pretty host-controller specific, so don't
4648 * enable hub-initiated timeouts unless the vendor has provided
4649 * information about their timeout algorithm.
4651 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4652 !xhci->devs[udev->slot_id])
4653 return USB3_LPM_DISABLED;
4655 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4656 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4658 /* Max Exit Latency is too big, disable LPM. */
4659 hub_encoded_timeout = USB3_LPM_DISABLED;
4663 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4666 return hub_encoded_timeout;
4669 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4670 struct usb_device *udev, enum usb3_link_state state)
4672 struct xhci_hcd *xhci;
4675 xhci = hcd_to_xhci(hcd);
4676 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4677 !xhci->devs[udev->slot_id])
4680 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4681 return xhci_change_max_exit_latency(xhci, udev, mel);
4683 #else /* CONFIG_PM */
4685 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4686 struct usb_device *udev, int enable)
4691 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4696 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4697 struct usb_device *udev, enum usb3_link_state state)
4699 return USB3_LPM_DISABLED;
4702 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4703 struct usb_device *udev, enum usb3_link_state state)
4707 #endif /* CONFIG_PM */
4709 /*-------------------------------------------------------------------------*/
4711 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4712 * internal data structures for the device.
4714 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4715 struct usb_tt *tt, gfp_t mem_flags)
4717 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4718 struct xhci_virt_device *vdev;
4719 struct xhci_command *config_cmd;
4720 struct xhci_input_control_ctx *ctrl_ctx;
4721 struct xhci_slot_ctx *slot_ctx;
4722 unsigned long flags;
4723 unsigned think_time;
4726 /* Ignore root hubs */
4730 vdev = xhci->devs[hdev->slot_id];
4732 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4735 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
4737 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
4740 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
4742 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4744 xhci_free_command(xhci, config_cmd);
4748 spin_lock_irqsave(&xhci->lock, flags);
4749 if (hdev->speed == USB_SPEED_HIGH &&
4750 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4751 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4752 xhci_free_command(xhci, config_cmd);
4753 spin_unlock_irqrestore(&xhci->lock, flags);
4757 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4758 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4759 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4760 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4762 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4763 * but it may be already set to 1 when setup an xHCI virtual
4764 * device, so clear it anyway.
4767 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4768 else if (hdev->speed == USB_SPEED_FULL)
4769 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
4771 if (xhci->hci_version > 0x95) {
4772 xhci_dbg(xhci, "xHCI version %x needs hub "
4773 "TT think time and number of ports\n",
4774 (unsigned int) xhci->hci_version);
4775 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4776 /* Set TT think time - convert from ns to FS bit times.
4777 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4778 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4780 * xHCI 1.0: this field shall be 0 if the device is not a
4783 think_time = tt->think_time;
4784 if (think_time != 0)
4785 think_time = (think_time / 666) - 1;
4786 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4787 slot_ctx->tt_info |=
4788 cpu_to_le32(TT_THINK_TIME(think_time));
4790 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4791 "TT think time or number of ports\n",
4792 (unsigned int) xhci->hci_version);
4794 slot_ctx->dev_state = 0;
4795 spin_unlock_irqrestore(&xhci->lock, flags);
4797 xhci_dbg(xhci, "Set up %s for hub device.\n",
4798 (xhci->hci_version > 0x95) ?
4799 "configure endpoint" : "evaluate context");
4800 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
4801 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
4803 /* Issue and wait for the configure endpoint or
4804 * evaluate context command.
4806 if (xhci->hci_version > 0x95)
4807 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4810 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4813 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
4814 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
4816 xhci_free_command(xhci, config_cmd);
4820 int xhci_get_frame(struct usb_hcd *hcd)
4822 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4823 /* EHCI mods by the periodic size. Why? */
4824 return readl(&xhci->run_regs->microframe_index) >> 3;
4827 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4829 struct xhci_hcd *xhci;
4830 struct device *dev = hcd->self.controller;
4833 /* Accept arbitrarily long scatter-gather lists */
4834 hcd->self.sg_tablesize = ~0;
4836 /* support to build packet from discontinuous buffers */
4837 hcd->self.no_sg_constraint = 1;
4839 /* XHCI controllers don't stop the ep queue on short packets :| */
4840 hcd->self.no_stop_on_short = 1;
4842 xhci = hcd_to_xhci(hcd);
4844 if (usb_hcd_is_primary_hcd(hcd)) {
4845 xhci->main_hcd = hcd;
4846 /* Mark the first roothub as being USB 2.0.
4847 * The xHCI driver will register the USB 3.0 roothub.
4849 hcd->speed = HCD_USB2;
4850 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4852 * USB 2.0 roothub under xHCI has an integrated TT,
4853 * (rate matching hub) as opposed to having an OHCI/UHCI
4854 * companion controller.
4858 if (xhci->sbrn == 0x31) {
4859 xhci_info(xhci, "Host supports USB 3.1 Enhanced SuperSpeed\n");
4860 hcd->speed = HCD_USB31;
4861 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
4863 /* xHCI private pointer was set in xhci_pci_probe for the second
4864 * registered roothub.
4869 mutex_init(&xhci->mutex);
4870 xhci->cap_regs = hcd->regs;
4871 xhci->op_regs = hcd->regs +
4872 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
4873 xhci->run_regs = hcd->regs +
4874 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4875 /* Cache read-only capability registers */
4876 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
4877 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
4878 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
4879 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
4880 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4881 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
4882 if (xhci->hci_version > 0x100)
4883 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
4884 xhci_print_registers(xhci);
4886 xhci->quirks |= quirks;
4888 get_quirks(dev, xhci);
4890 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4891 * success event after a short transfer. This quirk will ignore such
4894 if (xhci->hci_version > 0x96)
4895 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
4897 /* Make sure the HC is halted. */
4898 retval = xhci_halt(xhci);
4902 xhci_dbg(xhci, "Resetting HCD\n");
4903 /* Reset the internal HC memory state and registers. */
4904 retval = xhci_reset(xhci);
4907 xhci_dbg(xhci, "Reset complete\n");
4910 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
4911 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
4912 * address memory pointers actually. So, this driver clears the AC64
4913 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
4914 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
4916 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
4917 xhci->hcc_params &= ~BIT(0);
4919 /* Set dma_mask and coherent_dma_mask to 64-bits,
4920 * if xHC supports 64-bit addressing */
4921 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
4922 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
4923 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4924 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
4927 * This is to avoid error in cases where a 32-bit USB
4928 * controller is used on a 64-bit capable system.
4930 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
4933 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
4934 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
4937 xhci_dbg(xhci, "Calling HCD init\n");
4938 /* Initialize HCD and host controller data structures. */
4939 retval = xhci_init(hcd);
4942 xhci_dbg(xhci, "Called HCD init\n");
4944 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%08x\n",
4945 xhci->hcc_params, xhci->hci_version, xhci->quirks);
4949 EXPORT_SYMBOL_GPL(xhci_gen_setup);
4951 static const struct hc_driver xhci_hc_driver = {
4952 .description = "xhci-hcd",
4953 .product_desc = "xHCI Host Controller",
4954 .hcd_priv_size = sizeof(struct xhci_hcd),
4957 * generic hardware linkage
4960 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
4963 * basic lifecycle operations
4965 .reset = NULL, /* set in xhci_init_driver() */
4968 .shutdown = xhci_shutdown,
4971 * managing i/o requests and associated device resources
4973 .urb_enqueue = xhci_urb_enqueue,
4974 .urb_dequeue = xhci_urb_dequeue,
4975 .alloc_dev = xhci_alloc_dev,
4976 .free_dev = xhci_free_dev,
4977 .alloc_streams = xhci_alloc_streams,
4978 .free_streams = xhci_free_streams,
4979 .add_endpoint = xhci_add_endpoint,
4980 .drop_endpoint = xhci_drop_endpoint,
4981 .endpoint_reset = xhci_endpoint_reset,
4982 .check_bandwidth = xhci_check_bandwidth,
4983 .reset_bandwidth = xhci_reset_bandwidth,
4984 .address_device = xhci_address_device,
4985 .enable_device = xhci_enable_device,
4986 .update_hub_device = xhci_update_hub_device,
4987 .reset_device = xhci_discover_or_reset_device,
4990 * scheduling support
4992 .get_frame_number = xhci_get_frame,
4997 .hub_control = xhci_hub_control,
4998 .hub_status_data = xhci_hub_status_data,
4999 .bus_suspend = xhci_bus_suspend,
5000 .bus_resume = xhci_bus_resume,
5003 * call back when device connected and addressed
5005 .update_device = xhci_update_device,
5006 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5007 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5008 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5009 .find_raw_port_number = xhci_find_raw_port_number,
5012 void xhci_init_driver(struct hc_driver *drv,
5013 const struct xhci_driver_overrides *over)
5017 /* Copy the generic table to drv then apply the overrides */
5018 *drv = xhci_hc_driver;
5021 drv->hcd_priv_size += over->extra_priv_size;
5023 drv->reset = over->reset;
5025 drv->start = over->start;
5028 EXPORT_SYMBOL_GPL(xhci_init_driver);
5030 MODULE_DESCRIPTION(DRIVER_DESC);
5031 MODULE_AUTHOR(DRIVER_AUTHOR);
5032 MODULE_LICENSE("GPL");
5034 static int __init xhci_hcd_init(void)
5037 * Check the compiler generated sizes of structures that must be laid
5038 * out in specific ways for hardware access.
5040 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5041 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5042 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5043 /* xhci_device_control has eight fields, and also
5044 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5046 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5047 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5048 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5049 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5050 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5051 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5052 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5061 * If an init function is provided, an exit function must also be provided
5062 * to allow module unload.
5064 static void __exit xhci_hcd_fini(void) { }
5066 module_init(xhci_hcd_init);
5067 module_exit(xhci_hcd_fini);