2 * USB HOST XHCI Controller stack
4 * Based on xHCI host controller driver in linux-kernel
7 * Copyright (C) 2008 Intel Corp.
10 * Copyright (C) 2013 Samsung Electronics Co.Ltd
11 * Authors: Vivek Gautam <gautam.vivek@samsung.com>
12 * Vikas Sajjan <vikas.sajjan@samsung.com>
14 * SPDX-License-Identifier: GPL-2.0+
18 * This file gives the xhci stack for usb3.0 looking into
19 * xhci specification Rev1.0 (5/21/10).
20 * The quirk devices support hasn't been given yet.
25 #include <asm/byteorder.h>
29 #include <asm/cache.h>
30 #include <asm/unaligned.h>
31 #include <linux/errno.h>
34 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
35 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
38 static struct descriptor {
39 struct usb_hub_descriptor hub;
40 struct usb_device_descriptor device;
41 struct usb_config_descriptor config;
42 struct usb_interface_descriptor interface;
43 struct usb_endpoint_descriptor endpoint;
44 struct usb_ss_ep_comp_descriptor ep_companion;
45 } __attribute__ ((packed)) descriptor = {
47 0xc, /* bDescLength */
48 0x2a, /* bDescriptorType: hub descriptor */
49 2, /* bNrPorts -- runtime modified */
50 cpu_to_le16(0x8), /* wHubCharacteristics */
51 10, /* bPwrOn2PwrGood */
52 0, /* bHubCntrCurrent */
53 { /* Device removable */
54 } /* at most 7 ports! XXX */
58 1, /* bDescriptorType: UDESC_DEVICE */
59 cpu_to_le16(0x0300), /* bcdUSB: v3.0 */
60 9, /* bDeviceClass: UDCLASS_HUB */
61 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
62 3, /* bDeviceProtocol: UDPROTO_SSHUBSTT */
63 9, /* bMaxPacketSize: 512 bytes 2^9 */
64 0x0000, /* idVendor */
65 0x0000, /* idProduct */
66 cpu_to_le16(0x0100), /* bcdDevice */
67 1, /* iManufacturer */
69 0, /* iSerialNumber */
70 1 /* bNumConfigurations: 1 */
74 2, /* bDescriptorType: UDESC_CONFIG */
75 cpu_to_le16(0x1f), /* includes SS endpoint descriptor */
76 1, /* bNumInterface */
77 1, /* bConfigurationValue */
78 0, /* iConfiguration */
79 0x40, /* bmAttributes: UC_SELF_POWER */
84 4, /* bDescriptorType: UDESC_INTERFACE */
85 0, /* bInterfaceNumber */
86 0, /* bAlternateSetting */
87 1, /* bNumEndpoints */
88 9, /* bInterfaceClass: UICLASS_HUB */
89 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
90 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
95 5, /* bDescriptorType: UDESC_ENDPOINT */
96 0x81, /* bEndpointAddress: IN endpoint 1 */
97 3, /* bmAttributes: UE_INTERRUPT */
98 8, /* wMaxPacketSize */
102 0x06, /* ss_bLength */
103 0x30, /* ss_bDescriptorType: SS EP Companion */
104 0x00, /* ss_bMaxBurst: allows 1 TX between ACKs */
105 /* ss_bmAttributes: 1 packet per service interval */
107 /* ss_wBytesPerInterval: 15 bits for max 15 ports */
112 #ifndef CONFIG_DM_USB
113 static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
116 struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev)
121 /* Find the USB controller */
122 for (dev = udev->dev;
123 device_get_uclass_id(dev) != UCLASS_USB;
126 return dev_get_priv(dev);
128 return udev->controller;
133 * Waits for as per specified amount of time
134 * for the "result" to match with "done"
136 * @param ptr pointer to the register to be read
137 * @param mask mask for the value read
138 * @param done value to be campared with result
139 * @param usec time to wait till
140 * @return 0 if handshake is success else < 0 on failure
142 static int handshake(uint32_t volatile *ptr, uint32_t mask,
143 uint32_t done, int usec)
148 result = xhci_readl(ptr);
149 if (result == ~(uint32_t)0)
162 * Set the run bit and wait for the host to be running.
164 * @param hcor pointer to host controller operation registers
165 * @return status of the Handshake
167 static int xhci_start(struct xhci_hcor *hcor)
172 puts("Starting the controller\n");
173 temp = xhci_readl(&hcor->or_usbcmd);
175 xhci_writel(&hcor->or_usbcmd, temp);
178 * Wait for the HCHalted Status bit to be 0 to indicate the host is
181 ret = handshake(&hcor->or_usbsts, STS_HALT, 0, XHCI_MAX_HALT_USEC);
183 debug("Host took too long to start, "
184 "waited %u microseconds.\n",
190 * Resets the XHCI Controller
192 * @param hcor pointer to host controller operation registers
193 * @return -EBUSY if XHCI Controller is not halted else status of handshake
195 static int xhci_reset(struct xhci_hcor *hcor)
201 /* Halting the Host first */
202 debug("// Halt the HC: %p\n", hcor);
203 state = xhci_readl(&hcor->or_usbsts) & STS_HALT;
205 cmd = xhci_readl(&hcor->or_usbcmd);
207 xhci_writel(&hcor->or_usbcmd, cmd);
210 ret = handshake(&hcor->or_usbsts,
211 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
213 printf("Host not halted after %u microseconds.\n",
218 debug("// Reset the HC\n");
219 cmd = xhci_readl(&hcor->or_usbcmd);
221 xhci_writel(&hcor->or_usbcmd, cmd);
223 ret = handshake(&hcor->or_usbcmd, CMD_RESET, 0, XHCI_MAX_RESET_USEC);
228 * xHCI cannot write to any doorbells or operational registers other
229 * than status until the "Controller Not Ready" flag is cleared.
231 return handshake(&hcor->or_usbsts, STS_CNR, 0, XHCI_MAX_RESET_USEC);
235 * Used for passing endpoint bitmasks between the core and HCDs.
236 * Find the index for an endpoint given its descriptor.
237 * Use the return value to right shift 1 for the bitmask.
239 * Index = (epnum * 2) + direction - 1,
240 * where direction = 0 for OUT, 1 for IN.
241 * For control endpoints, the IN index is used (OUT index is unused), so
242 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
244 * @param desc USB enpdoint Descriptor
245 * @return index of the Endpoint
247 static unsigned int xhci_get_ep_index(struct usb_endpoint_descriptor *desc)
251 if (usb_endpoint_xfer_control(desc))
252 index = (unsigned int)(usb_endpoint_num(desc) * 2);
254 index = (unsigned int)((usb_endpoint_num(desc) * 2) -
255 (usb_endpoint_dir_in(desc) ? 0 : 1));
261 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
262 * microframes, rounded down to nearest power of 2.
264 static unsigned int xhci_microframes_to_exponent(unsigned int desc_interval,
265 unsigned int min_exponent,
266 unsigned int max_exponent)
268 unsigned int interval;
270 interval = fls(desc_interval) - 1;
271 interval = clamp_val(interval, min_exponent, max_exponent);
272 if ((1 << interval) != desc_interval)
273 debug("rounding interval to %d microframes, "\
274 "ep desc says %d microframes\n",
275 1 << interval, desc_interval);
280 static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
281 struct usb_endpoint_descriptor *endpt_desc)
283 if (endpt_desc->bInterval == 0)
286 return xhci_microframes_to_exponent(endpt_desc->bInterval, 0, 15);
289 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
290 struct usb_endpoint_descriptor *endpt_desc)
292 return xhci_microframes_to_exponent(endpt_desc->bInterval * 8, 3, 10);
296 * Convert interval expressed as 2^(bInterval - 1) == interval into
297 * straight exponent value 2^n == interval.
299 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
300 struct usb_endpoint_descriptor *endpt_desc)
302 unsigned int interval;
304 interval = clamp_val(endpt_desc->bInterval, 1, 16) - 1;
305 if (interval != endpt_desc->bInterval - 1)
306 debug("ep %#x - rounding interval to %d %sframes\n",
307 endpt_desc->bEndpointAddress, 1 << interval,
308 udev->speed == USB_SPEED_FULL ? "" : "micro");
310 if (udev->speed == USB_SPEED_FULL) {
312 * Full speed isoc endpoints specify interval in frames,
313 * not microframes. We are using microframes everywhere,
314 * so adjust accordingly.
316 interval += 3; /* 1 frame = 2^3 uframes */
323 * Return the polling or NAK interval.
325 * The polling interval is expressed in "microframes". If xHCI's Interval field
326 * is set to N, it will service the endpoint every 2^(Interval)*125us.
328 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
331 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
332 struct usb_endpoint_descriptor *endpt_desc)
334 unsigned int interval = 0;
336 switch (udev->speed) {
339 if (usb_endpoint_xfer_control(endpt_desc) ||
340 usb_endpoint_xfer_bulk(endpt_desc)) {
341 interval = xhci_parse_microframe_interval(udev,
345 /* Fall through - SS and HS isoc/int have same decoding */
347 case USB_SPEED_SUPER:
348 if (usb_endpoint_xfer_int(endpt_desc) ||
349 usb_endpoint_xfer_isoc(endpt_desc)) {
350 interval = xhci_parse_exponent_interval(udev,
356 if (usb_endpoint_xfer_isoc(endpt_desc)) {
357 interval = xhci_parse_exponent_interval(udev,
362 * Fall through for interrupt endpoint interval decoding
363 * since it uses the same rules as low speed interrupt
368 if (usb_endpoint_xfer_int(endpt_desc) ||
369 usb_endpoint_xfer_isoc(endpt_desc)) {
370 interval = xhci_parse_frame_interval(udev, endpt_desc);
382 * The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
383 * High speed endpoint descriptors can define "the number of additional
384 * transaction opportunities per microframe", but that goes in the Max Burst
385 * endpoint context field.
387 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
388 struct usb_endpoint_descriptor *endpt_desc,
389 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
391 if (udev->speed < USB_SPEED_SUPER ||
392 !usb_endpoint_xfer_isoc(endpt_desc))
395 return ss_ep_comp_desc->bmAttributes;
398 static u32 xhci_get_endpoint_max_burst(struct usb_device *udev,
399 struct usb_endpoint_descriptor *endpt_desc,
400 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
402 /* Super speed and Plus have max burst in ep companion desc */
403 if (udev->speed >= USB_SPEED_SUPER)
404 return ss_ep_comp_desc->bMaxBurst;
406 if (udev->speed == USB_SPEED_HIGH &&
407 (usb_endpoint_xfer_isoc(endpt_desc) ||
408 usb_endpoint_xfer_int(endpt_desc)))
409 return usb_endpoint_maxp_mult(endpt_desc) - 1;
415 * Return the maximum endpoint service interval time (ESIT) payload.
416 * Basically, this is the maxpacket size, multiplied by the burst size
419 static u32 xhci_get_max_esit_payload(struct usb_device *udev,
420 struct usb_endpoint_descriptor *endpt_desc,
421 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
426 /* Only applies for interrupt or isochronous endpoints */
427 if (usb_endpoint_xfer_control(endpt_desc) ||
428 usb_endpoint_xfer_bulk(endpt_desc))
431 /* SuperSpeed Isoc ep with less than 48k per esit */
432 if (udev->speed >= USB_SPEED_SUPER)
433 return le16_to_cpu(ss_ep_comp_desc->wBytesPerInterval);
435 max_packet = usb_endpoint_maxp(endpt_desc);
436 max_burst = usb_endpoint_maxp_mult(endpt_desc);
438 /* A 0 in max burst means 1 transfer per ESIT */
439 return max_packet * max_burst;
443 * Issue a configure endpoint command or evaluate context command
444 * and wait for it to finish.
446 * @param udev pointer to the Device Data Structure
447 * @param ctx_change flag to indicate the Context has changed or NOT
448 * @return 0 on success, -1 on failure
450 static int xhci_configure_endpoints(struct usb_device *udev, bool ctx_change)
452 struct xhci_container_ctx *in_ctx;
453 struct xhci_virt_device *virt_dev;
454 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
455 union xhci_trb *event;
457 virt_dev = ctrl->devs[udev->slot_id];
458 in_ctx = virt_dev->in_ctx;
460 xhci_flush_cache((uintptr_t)in_ctx->bytes, in_ctx->size);
461 xhci_queue_command(ctrl, in_ctx->bytes, udev->slot_id, 0,
462 ctx_change ? TRB_EVAL_CONTEXT : TRB_CONFIG_EP);
463 event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
464 BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
467 switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
469 debug("Successful %s command\n",
470 ctx_change ? "Evaluate Context" : "Configure Endpoint");
473 printf("ERROR: %s command returned completion code %d.\n",
474 ctx_change ? "Evaluate Context" : "Configure Endpoint",
475 GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
479 xhci_acknowledge_event(ctrl);
485 * Configure the endpoint, programming the device contexts.
487 * @param udev pointer to the USB device structure
488 * @return returns the status of the xhci_configure_endpoints
490 static int xhci_set_configuration(struct usb_device *udev)
492 struct xhci_container_ctx *in_ctx;
493 struct xhci_container_ctx *out_ctx;
494 struct xhci_input_control_ctx *ctrl_ctx;
495 struct xhci_slot_ctx *slot_ctx;
496 struct xhci_ep_ctx *ep_ctx[MAX_EP_CTX_NUM];
501 unsigned int ep_type;
502 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
506 int slot_id = udev->slot_id;
507 struct xhci_virt_device *virt_dev = ctrl->devs[slot_id];
508 struct usb_interface *ifdesc;
509 u32 max_esit_payload;
510 unsigned int interval;
512 unsigned int max_burst;
513 unsigned int avg_trb_len;
514 unsigned int err_count = 0;
516 out_ctx = virt_dev->out_ctx;
517 in_ctx = virt_dev->in_ctx;
519 num_of_ep = udev->config.if_desc[0].no_of_ep;
520 ifdesc = &udev->config.if_desc[0];
522 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
523 /* Initialize the input context control */
524 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
525 ctrl_ctx->drop_flags = 0;
527 /* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */
528 for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
529 ep_flag = xhci_get_ep_index(&ifdesc->ep_desc[cur_ep]);
530 ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1));
531 if (max_ep_flag < ep_flag)
532 max_ep_flag = ep_flag;
535 xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
538 xhci_slot_copy(ctrl, in_ctx, out_ctx);
539 slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
540 slot_ctx->dev_info &= ~(LAST_CTX_MASK);
541 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(max_ep_flag + 1) | 0);
543 xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0);
545 /* filling up ep contexts */
546 for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
547 struct usb_endpoint_descriptor *endpt_desc = NULL;
548 struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc = NULL;
550 endpt_desc = &ifdesc->ep_desc[cur_ep];
551 ss_ep_comp_desc = &ifdesc->ss_ep_comp_desc[cur_ep];
555 * Get values to fill the endpoint context, mostly from ep
556 * descriptor. The average TRB buffer lengt for bulk endpoints
557 * is unclear as we have no clue on scatter gather list entry
558 * size. For Isoc and Int, set it to max available.
559 * See xHCI 1.1 spec 4.14.1.1 for details.
561 max_esit_payload = xhci_get_max_esit_payload(udev, endpt_desc,
563 interval = xhci_get_endpoint_interval(udev, endpt_desc);
564 mult = xhci_get_endpoint_mult(udev, endpt_desc,
566 max_burst = xhci_get_endpoint_max_burst(udev, endpt_desc,
568 avg_trb_len = max_esit_payload;
570 ep_index = xhci_get_ep_index(endpt_desc);
571 ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
573 /* Allocate the ep rings */
574 virt_dev->eps[ep_index].ring = xhci_ring_alloc(1, true);
575 if (!virt_dev->eps[ep_index].ring)
578 /*NOTE: ep_desc[0] actually represents EP1 and so on */
579 dir = (((endpt_desc->bEndpointAddress) & (0x80)) >> 7);
580 ep_type = (((endpt_desc->bmAttributes) & (0x3)) | (dir << 2));
582 ep_ctx[ep_index]->ep_info =
583 cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) |
584 EP_INTERVAL(interval) | EP_MULT(mult));
586 ep_ctx[ep_index]->ep_info2 =
587 cpu_to_le32(ep_type << EP_TYPE_SHIFT);
588 ep_ctx[ep_index]->ep_info2 |=
589 cpu_to_le32(MAX_PACKET
590 (get_unaligned(&endpt_desc->wMaxPacketSize)));
592 /* Allow 3 retries for everything but isoc, set CErr = 3 */
593 if (!usb_endpoint_xfer_isoc(endpt_desc))
595 ep_ctx[ep_index]->ep_info2 |=
596 cpu_to_le32(MAX_BURST(max_burst) |
597 ERROR_COUNT(err_count));
600 virt_dev->eps[ep_index].ring->enqueue;
601 ep_ctx[ep_index]->deq = cpu_to_le64(trb_64 |
602 virt_dev->eps[ep_index].ring->cycle_state);
606 * 'Average TRB Length' should be 8 for control endpoints.
608 if (usb_endpoint_xfer_control(endpt_desc))
610 ep_ctx[ep_index]->tx_info =
611 cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) |
612 EP_AVG_TRB_LENGTH(avg_trb_len));
615 return xhci_configure_endpoints(udev, false);
619 * Issue an Address Device command (which will issue a SetAddress request to
622 * @param udev pointer to the Device Data Structure
623 * @return 0 if successful else error code on failure
625 static int xhci_address_device(struct usb_device *udev, int root_portnr)
628 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
629 struct xhci_slot_ctx *slot_ctx;
630 struct xhci_input_control_ctx *ctrl_ctx;
631 struct xhci_virt_device *virt_dev;
632 int slot_id = udev->slot_id;
633 union xhci_trb *event;
635 virt_dev = ctrl->devs[slot_id];
638 * This is the first Set Address since device plug-in
639 * so setting up the slot context.
641 debug("Setting up addressable devices %p\n", ctrl->dcbaa);
642 xhci_setup_addressable_virt_dev(ctrl, udev, root_portnr);
644 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
645 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
646 ctrl_ctx->drop_flags = 0;
648 xhci_queue_command(ctrl, (void *)ctrl_ctx, slot_id, 0, TRB_ADDR_DEV);
649 event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
650 BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id);
652 switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
655 printf("Setup ERROR: address device command for slot %d.\n",
660 puts("Device not responding to set address.\n");
664 puts("ERROR: Incompatible device"
665 "for address device command.\n");
669 debug("Successful Address Device command\n");
673 printf("ERROR: unexpected command completion code 0x%x.\n",
674 GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
679 xhci_acknowledge_event(ctrl);
683 * TODO: Unsuccessful Address Device command shall leave the
684 * slot in default state. So, issue Disable Slot command now.
688 xhci_inval_cache((uintptr_t)virt_dev->out_ctx->bytes,
689 virt_dev->out_ctx->size);
690 slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->out_ctx);
692 debug("xHC internal address is: %d\n",
693 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
699 * Issue Enable slot command to the controller to allocate
700 * device slot and assign the slot id. It fails if the xHC
701 * ran out of device slots, the Enable Slot command timed out,
702 * or allocating memory failed.
704 * @param udev pointer to the Device Data Structure
705 * @return Returns 0 on succes else return error code on failure
707 static int _xhci_alloc_device(struct usb_device *udev)
709 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
710 union xhci_trb *event;
714 * Root hub will be first device to be initailized.
715 * If this device is root-hub, don't do any xHC related
718 if (ctrl->rootdev == 0) {
719 udev->speed = USB_SPEED_SUPER;
723 xhci_queue_command(ctrl, NULL, 0, 0, TRB_ENABLE_SLOT);
724 event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
725 BUG_ON(GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))
728 udev->slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags));
730 xhci_acknowledge_event(ctrl);
732 ret = xhci_alloc_virt_device(ctrl, udev->slot_id);
735 * TODO: Unsuccessful Address Device command shall leave
736 * the slot in default. So, issue Disable Slot command now.
738 puts("Could not allocate xHCI USB device data structures\n");
745 #ifndef CONFIG_DM_USB
746 int usb_alloc_device(struct usb_device *udev)
748 return _xhci_alloc_device(udev);
753 * Full speed devices may have a max packet size greater than 8 bytes, but the
754 * USB core doesn't know that until it reads the first 8 bytes of the
755 * descriptor. If the usb_device's max packet size changes after that point,
756 * we need to issue an evaluate context command and wait on it.
758 * @param udev pointer to the Device Data Structure
759 * @return returns the status of the xhci_configure_endpoints
761 int xhci_check_maxpacket(struct usb_device *udev)
763 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
764 unsigned int slot_id = udev->slot_id;
765 int ep_index = 0; /* control endpoint */
766 struct xhci_container_ctx *in_ctx;
767 struct xhci_container_ctx *out_ctx;
768 struct xhci_input_control_ctx *ctrl_ctx;
769 struct xhci_ep_ctx *ep_ctx;
771 int hw_max_packet_size;
774 out_ctx = ctrl->devs[slot_id]->out_ctx;
775 xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
777 ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index);
778 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
779 max_packet_size = udev->epmaxpacketin[0];
780 if (hw_max_packet_size != max_packet_size) {
781 debug("Max Packet Size for ep 0 changed.\n");
782 debug("Max packet size in usb_device = %d\n", max_packet_size);
783 debug("Max packet size in xHCI HW = %d\n", hw_max_packet_size);
784 debug("Issuing evaluate context command.\n");
786 /* Set up the modified control endpoint 0 */
787 xhci_endpoint_copy(ctrl, ctrl->devs[slot_id]->in_ctx,
788 ctrl->devs[slot_id]->out_ctx, ep_index);
789 in_ctx = ctrl->devs[slot_id]->in_ctx;
790 ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
791 ep_ctx->ep_info2 &= cpu_to_le32(~((0xffff & MAX_PACKET_MASK)
792 << MAX_PACKET_SHIFT));
793 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
796 * Set up the input context flags for the command
797 * FIXME: This won't work if a non-default control endpoint
798 * changes max packet sizes.
800 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
801 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
802 ctrl_ctx->drop_flags = 0;
804 ret = xhci_configure_endpoints(udev, true);
810 * Clears the Change bits of the Port Status Register
812 * @param wValue request value
813 * @param wIndex request index
814 * @param addr address of posrt status register
815 * @param port_status state of port status register
818 static void xhci_clear_port_change_bit(u16 wValue,
819 u16 wIndex, volatile uint32_t *addr, u32 port_status)
821 char *port_change_bit;
825 case USB_PORT_FEAT_C_RESET:
827 port_change_bit = "reset";
829 case USB_PORT_FEAT_C_CONNECTION:
831 port_change_bit = "connect";
833 case USB_PORT_FEAT_C_OVER_CURRENT:
835 port_change_bit = "over-current";
837 case USB_PORT_FEAT_C_ENABLE:
839 port_change_bit = "enable/disable";
841 case USB_PORT_FEAT_C_SUSPEND:
843 port_change_bit = "suspend/resume";
846 /* Should never happen */
850 /* Change bits are all write 1 to clear */
851 xhci_writel(addr, port_status | status);
853 port_status = xhci_readl(addr);
854 debug("clear port %s change, actual port %d status = 0x%x\n",
855 port_change_bit, wIndex, port_status);
859 * Save Read Only (RO) bits and save read/write bits where
860 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
861 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
863 * @param state state of the Port Status and Control Regsiter
864 * @return a value that would result in the port being in the
865 * same state, if the value was written to the port
866 * status control register.
868 static u32 xhci_port_state_to_neutral(u32 state)
870 /* Save read-only status and port state */
871 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
875 * Submits the Requests to the XHCI Host Controller
877 * @param udev pointer to the USB device structure
878 * @param pipe contains the DIR_IN or OUT , devnum
879 * @param buffer buffer to be read/written based on the request
880 * @return returns 0 if successful else -1 on failure
882 static int xhci_submit_root(struct usb_device *udev, unsigned long pipe,
883 void *buffer, struct devrequest *req)
890 volatile uint32_t *status_reg;
891 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
892 struct xhci_hccr *hccr = ctrl->hccr;
893 struct xhci_hcor *hcor = ctrl->hcor;
894 int max_ports = HCS_MAX_PORTS(xhci_readl(&hccr->cr_hcsparams1));
896 if ((req->requesttype & USB_RT_PORT) &&
897 le16_to_cpu(req->index) > max_ports) {
898 printf("The request port(%d) exceeds maximum port number\n",
899 le16_to_cpu(req->index) - 1);
903 status_reg = (volatile uint32_t *)
904 (&hcor->portregs[le16_to_cpu(req->index) - 1].or_portsc);
907 typeReq = req->request | req->requesttype << 8;
910 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
911 switch (le16_to_cpu(req->value) >> 8) {
913 debug("USB_DT_DEVICE request\n");
914 srcptr = &descriptor.device;
918 debug("USB_DT_CONFIG config\n");
919 srcptr = &descriptor.config;
923 debug("USB_DT_STRING config\n");
924 switch (le16_to_cpu(req->value) & 0xff) {
925 case 0: /* Language */
926 srcptr = "\4\3\11\4";
929 case 1: /* Vendor String */
930 srcptr = "\16\3U\0-\0B\0o\0o\0t\0";
933 case 2: /* Product Name */
934 srcptr = "\52\3X\0H\0C\0I\0 "
936 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
940 printf("unknown value DT_STRING %x\n",
941 le16_to_cpu(req->value));
946 printf("unknown value %x\n", le16_to_cpu(req->value));
950 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
951 switch (le16_to_cpu(req->value) >> 8) {
954 debug("USB_DT_HUB config\n");
955 srcptr = &descriptor.hub;
959 printf("unknown value %x\n", le16_to_cpu(req->value));
963 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
964 debug("USB_REQ_SET_ADDRESS\n");
965 ctrl->rootdev = le16_to_cpu(req->value);
967 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
970 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
971 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
976 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
977 memset(tmpbuf, 0, 4);
978 reg = xhci_readl(status_reg);
979 if (reg & PORT_CONNECT) {
980 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
981 switch (reg & DEV_SPEED_MASK) {
983 debug("SPEED = FULLSPEED\n");
986 debug("SPEED = LOWSPEED\n");
987 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
990 debug("SPEED = HIGHSPEED\n");
991 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
994 debug("SPEED = SUPERSPEED\n");
995 tmpbuf[1] |= USB_PORT_STAT_SUPER_SPEED >> 8;
1000 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
1001 if ((reg & PORT_PLS_MASK) == XDEV_U3)
1002 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
1004 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
1005 if (reg & PORT_RESET)
1006 tmpbuf[0] |= USB_PORT_STAT_RESET;
1007 if (reg & PORT_POWER)
1009 * XXX: This Port power bit (for USB 3.0 hub)
1010 * we are faking in USB 2.0 hub port status;
1011 * since there's a change in bit positions in
1013 * USB 2.0 port status PP is at position[8]
1014 * USB 3.0 port status PP is at position[9]
1015 * So, we are still keeping it at position [8]
1017 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
1019 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
1021 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
1023 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
1025 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
1030 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
1031 reg = xhci_readl(status_reg);
1032 reg = xhci_port_state_to_neutral(reg);
1033 switch (le16_to_cpu(req->value)) {
1034 case USB_PORT_FEAT_ENABLE:
1036 xhci_writel(status_reg, reg);
1038 case USB_PORT_FEAT_POWER:
1040 xhci_writel(status_reg, reg);
1042 case USB_PORT_FEAT_RESET:
1044 xhci_writel(status_reg, reg);
1047 printf("unknown feature %x\n", le16_to_cpu(req->value));
1051 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
1052 reg = xhci_readl(status_reg);
1053 reg = xhci_port_state_to_neutral(reg);
1054 switch (le16_to_cpu(req->value)) {
1055 case USB_PORT_FEAT_ENABLE:
1058 case USB_PORT_FEAT_POWER:
1061 case USB_PORT_FEAT_C_RESET:
1062 case USB_PORT_FEAT_C_CONNECTION:
1063 case USB_PORT_FEAT_C_OVER_CURRENT:
1064 case USB_PORT_FEAT_C_ENABLE:
1065 xhci_clear_port_change_bit((le16_to_cpu(req->value)),
1066 le16_to_cpu(req->index),
1070 printf("unknown feature %x\n", le16_to_cpu(req->value));
1073 xhci_writel(status_reg, reg);
1076 puts("Unknown request\n");
1080 debug("scrlen = %d\n req->length = %d\n",
1081 srclen, le16_to_cpu(req->length));
1083 len = min(srclen, (int)le16_to_cpu(req->length));
1085 if (srcptr != NULL && len > 0)
1086 memcpy(buffer, srcptr, len);
1088 debug("Len is 0\n");
1090 udev->act_len = len;
1097 udev->status = USB_ST_STALLED;
1103 * Submits the INT request to XHCI Host cotroller
1105 * @param udev pointer to the USB device
1106 * @param pipe contains the DIR_IN or OUT , devnum
1107 * @param buffer buffer to be read/written based on the request
1108 * @param length length of the buffer
1109 * @param interval interval of the interrupt
1112 static int _xhci_submit_int_msg(struct usb_device *udev, unsigned long pipe,
1113 void *buffer, int length, int interval)
1115 if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
1116 printf("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
1121 * xHCI uses normal TRBs for both bulk and interrupt. When the
1122 * interrupt endpoint is to be serviced, the xHC will consume
1123 * (at most) one TD. A TD (comprised of sg list entries) can
1124 * take several service intervals to transmit.
1126 return xhci_bulk_tx(udev, pipe, length, buffer);
1130 * submit the BULK type of request to the USB Device
1132 * @param udev pointer to the USB device
1133 * @param pipe contains the DIR_IN or OUT , devnum
1134 * @param buffer buffer to be read/written based on the request
1135 * @param length length of the buffer
1136 * @return returns 0 if successful else -1 on failure
1138 static int _xhci_submit_bulk_msg(struct usb_device *udev, unsigned long pipe,
1139 void *buffer, int length)
1141 if (usb_pipetype(pipe) != PIPE_BULK) {
1142 printf("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
1146 return xhci_bulk_tx(udev, pipe, length, buffer);
1150 * submit the control type of request to the Root hub/Device based on the devnum
1152 * @param udev pointer to the USB device
1153 * @param pipe contains the DIR_IN or OUT , devnum
1154 * @param buffer buffer to be read/written based on the request
1155 * @param length length of the buffer
1156 * @param setup Request type
1157 * @param root_portnr Root port number that this device is on
1158 * @return returns 0 if successful else -1 on failure
1160 static int _xhci_submit_control_msg(struct usb_device *udev, unsigned long pipe,
1161 void *buffer, int length,
1162 struct devrequest *setup, int root_portnr)
1164 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
1167 if (usb_pipetype(pipe) != PIPE_CONTROL) {
1168 printf("non-control pipe (type=%lu)", usb_pipetype(pipe));
1172 if (usb_pipedevice(pipe) == ctrl->rootdev)
1173 return xhci_submit_root(udev, pipe, buffer, setup);
1175 if (setup->request == USB_REQ_SET_ADDRESS &&
1176 (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD)
1177 return xhci_address_device(udev, root_portnr);
1179 if (setup->request == USB_REQ_SET_CONFIGURATION &&
1180 (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1181 ret = xhci_set_configuration(udev);
1183 puts("Failed to configure xHCI endpoint\n");
1188 return xhci_ctrl_tx(udev, pipe, setup, length, buffer);
1191 static int xhci_lowlevel_init(struct xhci_ctrl *ctrl)
1193 struct xhci_hccr *hccr;
1194 struct xhci_hcor *hcor;
1202 * Program the Number of Device Slots Enabled field in the CONFIG
1203 * register with the max value of slots the HC can handle.
1205 val = (xhci_readl(&hccr->cr_hcsparams1) & HCS_SLOTS_MASK);
1206 val2 = xhci_readl(&hcor->or_config);
1207 val |= (val2 & ~HCS_SLOTS_MASK);
1208 xhci_writel(&hcor->or_config, val);
1210 /* initializing xhci data structures */
1211 if (xhci_mem_init(ctrl, hccr, hcor) < 0)
1214 reg = xhci_readl(&hccr->cr_hcsparams1);
1215 descriptor.hub.bNbrPorts = ((reg & HCS_MAX_PORTS_MASK) >>
1216 HCS_MAX_PORTS_SHIFT);
1217 printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
1219 /* Port Indicators */
1220 reg = xhci_readl(&hccr->cr_hccparams);
1221 if (HCS_INDICATOR(reg))
1222 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1223 | 0x80, &descriptor.hub.wHubCharacteristics);
1225 /* Port Power Control */
1227 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1228 | 0x01, &descriptor.hub.wHubCharacteristics);
1230 if (xhci_start(hcor)) {
1235 /* Zero'ing IRQ control register and IRQ pending register */
1236 xhci_writel(&ctrl->ir_set->irq_control, 0x0);
1237 xhci_writel(&ctrl->ir_set->irq_pending, 0x0);
1239 reg = HC_VERSION(xhci_readl(&hccr->cr_capbase));
1240 printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff);
1245 static int xhci_lowlevel_stop(struct xhci_ctrl *ctrl)
1249 xhci_reset(ctrl->hcor);
1251 debug("// Disabling event ring interrupts\n");
1252 temp = xhci_readl(&ctrl->hcor->or_usbsts);
1253 xhci_writel(&ctrl->hcor->or_usbsts, temp & ~STS_EINT);
1254 temp = xhci_readl(&ctrl->ir_set->irq_pending);
1255 xhci_writel(&ctrl->ir_set->irq_pending, ER_IRQ_DISABLE(temp));
1260 #ifndef CONFIG_DM_USB
1261 int submit_control_msg(struct usb_device *udev, unsigned long pipe,
1262 void *buffer, int length, struct devrequest *setup)
1264 struct usb_device *hop = udev;
1267 while (hop->parent->parent)
1270 return _xhci_submit_control_msg(udev, pipe, buffer, length, setup,
1274 int submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
1277 return _xhci_submit_bulk_msg(udev, pipe, buffer, length);
1280 int submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
1281 int length, int interval)
1283 return _xhci_submit_int_msg(udev, pipe, buffer, length, interval);
1287 * Intialises the XHCI host controller
1288 * and allocates the necessary data structures
1290 * @param index index to the host controller data structure
1291 * @return pointer to the intialised controller
1293 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1295 struct xhci_hccr *hccr;
1296 struct xhci_hcor *hcor;
1297 struct xhci_ctrl *ctrl;
1302 if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0)
1305 if (xhci_reset(hcor) != 0)
1308 ctrl = &xhcic[index];
1313 ret = xhci_lowlevel_init(ctrl);
1319 *controller = &xhcic[index];
1326 * Stops the XHCI host controller
1327 * and cleans up all the related data structures
1329 * @param index index to the host controller data structure
1332 int usb_lowlevel_stop(int index)
1334 struct xhci_ctrl *ctrl = (xhcic + index);
1337 xhci_lowlevel_stop(ctrl);
1338 xhci_hcd_stop(index);
1344 #endif /* CONFIG_DM_USB */
1346 #ifdef CONFIG_DM_USB
1348 static int xhci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1349 unsigned long pipe, void *buffer, int length,
1350 struct devrequest *setup)
1352 struct usb_device *uhop;
1353 struct udevice *hub;
1354 int root_portnr = 0;
1356 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1357 dev->name, udev, udev->dev->name, udev->portnr);
1359 if (device_get_uclass_id(hub) == UCLASS_USB_HUB) {
1360 /* Figure out our port number on the root hub */
1361 if (usb_hub_is_root_hub(hub)) {
1362 root_portnr = udev->portnr;
1364 while (!usb_hub_is_root_hub(hub->parent))
1366 uhop = dev_get_parent_priv(hub);
1367 root_portnr = uhop->portnr;
1371 struct usb_device *hop = udev;
1374 while (hop->parent->parent)
1377 return _xhci_submit_control_msg(udev, pipe, buffer, length, setup,
1381 static int xhci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1382 unsigned long pipe, void *buffer, int length)
1384 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1385 return _xhci_submit_bulk_msg(udev, pipe, buffer, length);
1388 static int xhci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1389 unsigned long pipe, void *buffer, int length,
1392 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1393 return _xhci_submit_int_msg(udev, pipe, buffer, length, interval);
1396 static int xhci_alloc_device(struct udevice *dev, struct usb_device *udev)
1398 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1399 return _xhci_alloc_device(udev);
1402 static int xhci_update_hub_device(struct udevice *dev, struct usb_device *udev)
1404 struct xhci_ctrl *ctrl = dev_get_priv(dev);
1405 struct usb_hub_device *hub = dev_get_uclass_priv(udev->dev);
1406 struct xhci_virt_device *virt_dev;
1407 struct xhci_input_control_ctx *ctrl_ctx;
1408 struct xhci_container_ctx *out_ctx;
1409 struct xhci_container_ctx *in_ctx;
1410 struct xhci_slot_ctx *slot_ctx;
1411 int slot_id = udev->slot_id;
1412 unsigned think_time;
1414 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1416 /* Ignore root hubs */
1417 if (usb_hub_is_root_hub(udev->dev))
1420 virt_dev = ctrl->devs[slot_id];
1423 out_ctx = virt_dev->out_ctx;
1424 in_ctx = virt_dev->in_ctx;
1426 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1427 /* Initialize the input context control */
1428 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
1429 ctrl_ctx->drop_flags = 0;
1431 xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
1434 xhci_slot_copy(ctrl, in_ctx, out_ctx);
1435 slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
1437 /* Update hub related fields */
1438 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
1439 if (hub->tt.multi && udev->speed == USB_SPEED_HIGH)
1440 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1441 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(udev->maxchild));
1443 * Set TT think time - convert from ns to FS bit times.
1444 * Note 8 FS bit times == (8 bits / 12000000 bps) ~= 666ns
1446 * 0 = 8 FS bit times, 1 = 16 FS bit times,
1447 * 2 = 24 FS bit times, 3 = 32 FS bit times.
1449 * This field shall be 0 if the device is not a high-spped hub.
1451 think_time = hub->tt.think_time;
1452 if (think_time != 0)
1453 think_time = (think_time / 666) - 1;
1454 if (udev->speed == USB_SPEED_HIGH)
1455 slot_ctx->tt_info |= cpu_to_le32(TT_THINK_TIME(think_time));
1457 return xhci_configure_endpoints(udev, false);
1460 static int xhci_get_max_xfer_size(struct udevice *dev, size_t *size)
1463 * xHCD allocates one segment which includes 64 TRBs for each endpoint
1464 * and the last TRB in this segment is configured as a link TRB to form
1465 * a TRB ring. Each TRB can transfer up to 64K bytes, however data
1466 * buffers referenced by transfer TRBs shall not span 64KB boundaries.
1467 * Hence the maximum number of TRBs we can use in one transfer is 62.
1469 *size = (TRBS_PER_SEGMENT - 2) * TRB_MAX_BUFF_SIZE;
1474 int xhci_register(struct udevice *dev, struct xhci_hccr *hccr,
1475 struct xhci_hcor *hcor)
1477 struct xhci_ctrl *ctrl = dev_get_priv(dev);
1478 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
1481 debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p\n", __func__, dev->name,
1487 * XHCI needs to issue a Address device command to setup
1488 * proper device context structures, before it can interact
1489 * with the device. So a get_descriptor will fail before any
1490 * of that is done for XHCI unlike EHCI.
1492 priv->desc_before_addr = false;
1494 ret = xhci_reset(hcor);
1500 ret = xhci_lowlevel_init(ctrl);
1507 debug("%s: failed, ret=%d\n", __func__, ret);
1511 int xhci_deregister(struct udevice *dev)
1513 struct xhci_ctrl *ctrl = dev_get_priv(dev);
1515 xhci_lowlevel_stop(ctrl);
1521 struct dm_usb_ops xhci_usb_ops = {
1522 .control = xhci_submit_control_msg,
1523 .bulk = xhci_submit_bulk_msg,
1524 .interrupt = xhci_submit_int_msg,
1525 .alloc_device = xhci_alloc_device,
1526 .update_hub_device = xhci_update_hub_device,
1527 .get_max_xfer_size = xhci_get_max_xfer_size,