1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016 Rockchip, Inc.
4 * Authors: Daniel Meng <daniel.meng@rock-chips.com>
12 #include <linux/errno.h>
13 #include <linux/compat.h>
14 #include <linux/usb/dwc3.h>
15 #include <power/regulator.h>
19 struct rockchip_xhci_platdata {
21 struct udevice *vbus_supply;
25 * Contains pointers to register base addresses
26 * for the usb controller.
28 struct rockchip_xhci {
29 struct usb_platdata usb_plat;
30 struct xhci_ctrl ctrl;
31 struct xhci_hccr *hcd;
32 struct dwc3 *dwc3_reg;
35 static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
37 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
41 * Get the base address for XHCI controller from the device node
43 plat->hcd_base = dev_read_addr(dev);
44 if (plat->hcd_base == FDT_ADDR_T_NONE) {
45 pr_err("Can't get the XHCI register base address\n");
50 ret = device_get_supply_regulator(dev, "vbus-supply",
53 debug("Can't get VBus regulator!\n");
59 * rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core
60 * @dwc: Pointer to our controller context structure
61 * @dev: Pointer to ulcass device
63 static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg,
69 /* Set dwc3 usb2 phy config */
70 reg = readl(&dwc3_reg->g_usb2phycfg[0]);
72 if (dev_read_bool(dev, "snps,dis-enblslpm-quirk"))
73 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
75 utmi_bits = dev_read_u32_default(dev, "snps,phyif-utmi-bits", -1);
76 if (utmi_bits == 16) {
77 reg |= DWC3_GUSB2PHYCFG_PHYIF;
78 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
79 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
80 } else if (utmi_bits == 8) {
81 reg &= ~DWC3_GUSB2PHYCFG_PHYIF;
82 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
83 reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
86 if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
87 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
89 if (dev_read_bool(dev, "snps,dis-u2-susphy-quirk"))
90 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
92 writel(reg, &dwc3_reg->g_usb2phycfg[0]);
95 static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci,
100 ret = dwc3_core_init(rkxhci->dwc3_reg);
102 pr_err("failed to initialize core\n");
106 rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev);
108 /* We are hard-coding DWC3 core to Host Mode */
109 dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
114 static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci)
119 static int xhci_usb_probe(struct udevice *dev)
121 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
122 struct rockchip_xhci *ctx = dev_get_priv(dev);
123 struct xhci_hcor *hcor;
126 ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
127 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
128 hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd +
129 HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)));
131 if (plat->vbus_supply) {
132 ret = regulator_set_enable(plat->vbus_supply, true);
134 pr_err("XHCI: failed to set VBus supply\n");
139 ret = rockchip_xhci_core_init(ctx, dev);
141 pr_err("XHCI: failed to initialize controller\n");
145 return xhci_register(dev, ctx->hcd, hcor);
148 static int xhci_usb_remove(struct udevice *dev)
150 struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
151 struct rockchip_xhci *ctx = dev_get_priv(dev);
154 ret = xhci_deregister(dev);
157 ret = rockchip_xhci_core_exit(ctx);
161 if (plat->vbus_supply) {
162 ret = regulator_set_enable(plat->vbus_supply, false);
164 pr_err("XHCI: failed to set VBus supply\n");
170 static const struct udevice_id xhci_usb_ids[] = {
171 { .compatible = "rockchip,rk3328-xhci" },
175 U_BOOT_DRIVER(usb_xhci) = {
176 .name = "xhci_rockchip",
178 .of_match = xhci_usb_ids,
179 .ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
180 .probe = xhci_usb_probe,
181 .remove = xhci_usb_remove,
182 .ops = &xhci_usb_ops,
183 .bind = dm_scan_fdt_dev,
184 .platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata),
185 .priv_auto_alloc_size = sizeof(struct rockchip_xhci),
186 .flags = DM_FLAG_ALLOC_PRIV_DMA,
189 static const struct udevice_id usb_phy_ids[] = {
190 { .compatible = "rockchip,rk3328-usb3-phy" },
194 U_BOOT_DRIVER(usb_phy) = {
195 .name = "usb_phy_rockchip",
196 .of_match = usb_phy_ids,