drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70 #include "xhci-trace.h"
  71
  72 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  73                 struct xhci_virt_device *virt_dev,
  74                 struct xhci_event_cmd *event);
  75
  76 /*
  77  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  78  * address of the TRB.
  79  */
  80 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  81                 union xhci_trb *trb)
  82 {
  83         unsigned long segment_offset;
  84
  85         if (!seg || !trb || trb < seg->trbs)
  86                 return 0;
  87         /* offset in TRBs */
  88         segment_offset = trb - seg->trbs;
  89         if (segment_offset > TRBS_PER_SEGMENT)
  90                 return 0;
  91         return seg->dma + (segment_offset * sizeof(*trb));
  92 }
  93
  94 /* Does this link TRB point to the first segment in a ring,
  95  * or was the previous TRB the last TRB on the last segment in the ERST?
  96  */
  97 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  98                 struct xhci_segment *seg, union xhci_trb *trb)
  99 {
 100         if (ring == xhci->event_ring)
 101                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 102                         (seg->next == xhci->event_ring->first_seg);
 103         else
 104                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 105 }
 106
 107 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 108  * segment?  I.e. would the updated event TRB pointer step off the end of the
 109  * event seg?
 110  */
 111 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 112                 struct xhci_segment *seg, union xhci_trb *trb)
 113 {
 114         if (ring == xhci->event_ring)
 115                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 116         else
 117                 return TRB_TYPE_LINK_LE32(trb->link.control);
 118 }
 119
 120 static int enqueue_is_link_trb(struct xhci_ring *ring)
 121 {
 122         struct xhci_link_trb *link = &ring->enqueue->link;
 123         return TRB_TYPE_LINK_LE32(link->control);
 124 }
 125
 126 union xhci_trb *xhci_find_next_enqueue(struct xhci_ring *ring)
 127 {
 128         /* Enqueue pointer can be left pointing to the link TRB,
 129          * we must handle that
 130          */
 131         if (TRB_TYPE_LINK_LE32(ring->enqueue->link.control))
 132                 return ring->enq_seg->next->trbs;
 133         return ring->enqueue;
 134 }
 135
 136 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 137  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 138  * effect the ring dequeue or enqueue pointers.
 139  */
 140 static void next_trb(struct xhci_hcd *xhci,
 141                 struct xhci_ring *ring,
 142                 struct xhci_segment **seg,
 143                 union xhci_trb **trb)
 144 {
 145         if (last_trb(xhci, ring, *seg, *trb)) {
 146                 *seg = (*seg)->next;
 147                 *trb = ((*seg)->trbs);
 148         } else {
 149                 (*trb)++;
 150         }
 151 }
 152
 153 /*
 154  * See Cycle bit rules. SW is the consumer for the event ring only.
 155  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 156  */
 157 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
 158 {
 159         ring->deq_updates++;
 160
 161         /*
 162          * If this is not event ring, and the dequeue pointer
 163          * is not on a link TRB, there is one more usable TRB
 164          */
 165         if (ring->type != TYPE_EVENT &&
 166                         !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
 167                 ring->num_trbs_free++;
 168
 169         do {
 170                 /*
 171                  * Update the dequeue pointer further if that was a link TRB or
 172                  * we're at the end of an event ring segment (which doesn't have
 173                  * link TRBS)
 174                  */
 175                 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
 176                         if (ring->type == TYPE_EVENT &&
 177                                         last_trb_on_last_seg(xhci, ring,
 178                                                 ring->deq_seg, ring->dequeue)) {
 179                                 ring->cycle_state ^= 1;
 180                         }
 181                         ring->deq_seg = ring->deq_seg->next;
 182                         ring->dequeue = ring->deq_seg->trbs;
 183                 } else {
 184                         ring->dequeue++;
 185                 }
 186         } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
 187 }
 188
 189 /*
 190  * See Cycle bit rules. SW is the consumer for the event ring only.
 191  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 192  *
 193  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 194  * chain bit is set), then set the chain bit in all the following link TRBs.
 195  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 196  * have their chain bit cleared (so that each Link TRB is a separate TD).
 197  *
 198  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 199  * set, but other sections talk about dealing with the chain bit set.  This was
 200  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 201  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 202  *
 203  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 204  *                      prepare_transfer()?
 205  */
 206 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 207                         bool more_trbs_coming)
 208 {
 209         u32 chain;
 210         union xhci_trb *next;
 211
 212         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 213         /* If this is not event ring, there is one less usable TRB */
 214         if (ring->type != TYPE_EVENT &&
 215                         !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
 216                 ring->num_trbs_free--;
 217         next = ++(ring->enqueue);
 218
 219         ring->enq_updates++;
 220         /* Update the dequeue pointer further if that was a link TRB or we're at
 221          * the end of an event ring segment (which doesn't have link TRBS)
 222          */
 223         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 224                 if (ring->type != TYPE_EVENT) {
 225                         /*
 226                          * If the caller doesn't plan on enqueueing more
 227                          * TDs before ringing the doorbell, then we
 228                          * don't want to give the link TRB to the
 229                          * hardware just yet.  We'll give the link TRB
 230                          * back in prepare_ring() just before we enqueue
 231                          * the TD at the top of the ring.
 232                          */
 233                         if (!chain && !more_trbs_coming)
 234                                 break;
 235
 236                         /* If we're not dealing with 0.95 hardware or
 237                          * isoc rings on AMD 0.96 host,
 238                          * carry over the chain bit of the previous TRB
 239                          * (which may mean the chain bit is cleared).
 240                          */
 241                         if (!(ring->type == TYPE_ISOC &&
 242                                         (xhci->quirks & XHCI_AMD_0x96_HOST))
 243                                                 && !xhci_link_trb_quirk(xhci)) {
 244                                 next->link.control &=
 245                                         cpu_to_le32(~TRB_CHAIN);
 246                                 next->link.control |=
 247                                         cpu_to_le32(chain);
 248                         }
 249                         /* Give this link TRB to the hardware */
 250                         wmb();
 251                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
 252
 253                         /* Toggle the cycle bit after the last ring segment. */
 254                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 255                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 256                         }
 257                 }
 258                 ring->enq_seg = ring->enq_seg->next;
 259                 ring->enqueue = ring->enq_seg->trbs;
 260                 next = ring->enqueue;
 261         }
 262 }
 263
 264 /*
 265  * Check to see if there's room to enqueue num_trbs on the ring and make sure
 266  * enqueue pointer will not advance into dequeue segment. See rules above.
 267  */
 268 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 269                 unsigned int num_trbs)
 270 {
 271         int num_trbs_in_deq_seg;
 272
 273         if (ring->num_trbs_free < num_trbs)
 274                 return 0;
 275
 276         if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
 277                 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
 278                 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
 279                         return 0;
 280         }
 281
 282         return 1;
 283 }
 284
 285 /* Ring the host controller doorbell after placing a command on the ring */
 286 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 287 {
 288         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 289                 return;
 290
 291         xhci_dbg(xhci, "// Ding dong!\n");
 292         writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 293         /* Flush PCI posted writes */
 294         readl(&xhci->dba->doorbell[0]);
 295 }
 296
 297 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
 298 {
 299         u64 temp_64;
 300         int ret;
 301
 302         xhci_dbg(xhci, "Abort command ring\n");
 303
 304         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
 305                 xhci_dbg(xhci, "The command ring isn't running, "
 306                                 "Have the command ring been stopped?\n");
 307                 return 0;
 308         }
 309
 310         temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 311         if (!(temp_64 & CMD_RING_RUNNING)) {
 312                 xhci_dbg(xhci, "Command ring had been stopped\n");
 313                 return 0;
 314         }
 315         xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
 316         xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
 317                         &xhci->op_regs->cmd_ring);
 318
 319         /* Section 4.6.1.2 of xHCI 1.0 spec says software should
 320          * time the completion od all xHCI commands, including
 321          * the Command Abort operation. If software doesn't see
 322          * CRR negated in a timely manner (e.g. longer than 5
 323          * seconds), then it should assume that the there are
 324          * larger problems with the xHC and assert HCRST.
 325          */
 326         ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring,
 327                         CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 328         if (ret < 0) {
 329                 xhci_err(xhci, "Stopped the command ring failed, "
 330                                 "maybe the host is dead\n");
 331                 xhci->xhc_state |= XHCI_STATE_DYING;
 332                 xhci_quiesce(xhci);
 333                 xhci_halt(xhci);
 334                 return -ESHUTDOWN;
 335         }
 336
 337         return 0;
 338 }
 339
 340 static int xhci_queue_cd(struct xhci_hcd *xhci,
 341                 struct xhci_command *command,
 342                 union xhci_trb *cmd_trb)
 343 {
 344         struct xhci_cd *cd;
 345         cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
 346         if (!cd)
 347                 return -ENOMEM;
 348         INIT_LIST_HEAD(&cd->cancel_cmd_list);
 349
 350         cd->command = command;
 351         cd->cmd_trb = cmd_trb;
 352         list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
 353
 354         return 0;
 355 }
 356
 357 /*
 358  * Cancel the command which has issue.
 359  *
 360  * Some commands may hang due to waiting for acknowledgement from
 361  * usb device. It is outside of the xHC's ability to control and
 362  * will cause the command ring is blocked. When it occurs software
 363  * should intervene to recover the command ring.
 364  * See Section 4.6.1.1 and 4.6.1.2
 365  */
 366 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
 367                 union xhci_trb *cmd_trb)
 368 {
 369         int retval = 0;
 370         unsigned long flags;
 371
 372         spin_lock_irqsave(&xhci->lock, flags);
 373
 374         if (xhci->xhc_state & XHCI_STATE_DYING) {
 375                 xhci_warn(xhci, "Abort the command ring,"
 376                                 " but the xHCI is dead.\n");
 377                 retval = -ESHUTDOWN;
 378                 goto fail;
 379         }
 380
 381         /* queue the cmd desriptor to cancel_cmd_list */
 382         retval = xhci_queue_cd(xhci, command, cmd_trb);
 383         if (retval) {
 384                 xhci_warn(xhci, "Queuing command descriptor failed.\n");
 385                 goto fail;
 386         }
 387
 388         /* abort command ring */
 389         retval = xhci_abort_cmd_ring(xhci);
 390         if (retval) {
 391                 xhci_err(xhci, "Abort command ring failed\n");
 392                 if (unlikely(retval == -ESHUTDOWN)) {
 393                         spin_unlock_irqrestore(&xhci->lock, flags);
 394                         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 395                         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 396                         return retval;
 397                 }
 398         }
 399
 400 fail:
 401         spin_unlock_irqrestore(&xhci->lock, flags);
 402         return retval;
 403 }
 404
 405 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 406                 unsigned int slot_id,
 407                 unsigned int ep_index,
 408                 unsigned int stream_id)
 409 {
 410         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 411         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 412         unsigned int ep_state = ep->ep_state;
 413
 414         /* Don't ring the doorbell for this endpoint if there are pending
 415          * cancellations because we don't want to interrupt processing.
 416          * We don't want to restart any stream rings if there's a set dequeue
 417          * pointer command pending because the device can choose to start any
 418          * stream once the endpoint is on the HW schedule.
 419          * FIXME - check all the stream rings for pending cancellations.
 420          */
 421         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 422             (ep_state & EP_HALTED))
 423                 return;
 424         writel(DB_VALUE(ep_index, stream_id), db_addr);
 425         /* The CPU has better things to do at this point than wait for a
 426          * write-posting flush.  It'll get there soon enough.
 427          */
 428 }
 429
 430 /* Ring the doorbell for any rings with pending URBs */
 431 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 432                 unsigned int slot_id,
 433                 unsigned int ep_index)
 434 {
 435         unsigned int stream_id;
 436         struct xhci_virt_ep *ep;
 437
 438         ep = &xhci->devs[slot_id]->eps[ep_index];
 439
 440         /* A ring has pending URBs if its TD list is not empty */
 441         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 442                 if (ep->ring && !(list_empty(&ep->ring->td_list)))
 443                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 444                 return;
 445         }
 446
 447         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 448                         stream_id++) {
 449                 struct xhci_stream_info *stream_info = ep->stream_info;
 450                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 451                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 452                                                 stream_id);
 453         }
 454 }
 455
 456 /*
 457  * Find the segment that trb is in.  Start searching in start_seg.
 458  * If we must move past a segment that has a link TRB with a toggle cycle state
 459  * bit set, then we will toggle the value pointed at by cycle_state.
 460  */
 461 static struct xhci_segment *find_trb_seg(
 462                 struct xhci_segment *start_seg,
 463                 union xhci_trb  *trb, int *cycle_state)
 464 {
 465         struct xhci_segment *cur_seg = start_seg;
 466         struct xhci_generic_trb *generic_trb;
 467
 468         while (cur_seg->trbs > trb ||
 469                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 470                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 471                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 472                         *cycle_state ^= 0x1;
 473                 cur_seg = cur_seg->next;
 474                 if (cur_seg == start_seg)
 475                         /* Looped over the entire list.  Oops! */
 476                         return NULL;
 477         }
 478         return cur_seg;
 479 }
 480
 481
 482 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 483                 unsigned int slot_id, unsigned int ep_index,
 484                 unsigned int stream_id)
 485 {
 486         struct xhci_virt_ep *ep;
 487
 488         ep = &xhci->devs[slot_id]->eps[ep_index];
 489         /* Common case: no streams */
 490         if (!(ep->ep_state & EP_HAS_STREAMS))
 491                 return ep->ring;
 492
 493         if (stream_id == 0) {
 494                 xhci_warn(xhci,
 495                                 "WARN: Slot ID %u, ep index %u has streams, "
 496                                 "but URB has no stream ID.\n",
 497                                 slot_id, ep_index);
 498                 return NULL;
 499         }
 500
 501         if (stream_id < ep->stream_info->num_streams)
 502                 return ep->stream_info->stream_rings[stream_id];
 503
 504         xhci_warn(xhci,
 505                         "WARN: Slot ID %u, ep index %u has "
 506                         "stream IDs 1 to %u allocated, "
 507                         "but stream ID %u is requested.\n",
 508                         slot_id, ep_index,
 509                         ep->stream_info->num_streams - 1,
 510                         stream_id);
 511         return NULL;
 512 }
 513
 514 /* Get the right ring for the given URB.
 515  * If the endpoint supports streams, boundary check the URB's stream ID.
 516  * If the endpoint doesn't support streams, return the singular endpoint ring.
 517  */
 518 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 519                 struct urb *urb)
 520 {
 521         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 522                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 523 }
 524
 525 /*
 526  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 527  * Record the new state of the xHC's endpoint ring dequeue segment,
 528  * dequeue pointer, and new consumer cycle state in state.
 529  * Update our internal representation of the ring's dequeue pointer.
 530  *
 531  * We do this in three jumps:
 532  *  - First we update our new ring state to be the same as when the xHC stopped.
 533  *  - Then we traverse the ring to find the segment that contains
 534  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 535  *    any link TRBs with the toggle cycle bit set.
 536  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 537  *    if we've moved it past a link TRB with the toggle cycle bit set.
 538  *
 539  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 540  * with correct __le32 accesses they should work fine.  Only users of this are
 541  * in here.
 542  */
 543 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 544                 unsigned int slot_id, unsigned int ep_index,
 545                 unsigned int stream_id, struct xhci_td *cur_td,
 546                 struct xhci_dequeue_state *state)
 547 {
 548         struct xhci_virt_device *dev = xhci->devs[slot_id];
 549         struct xhci_ring *ep_ring;
 550         struct xhci_generic_trb *trb;
 551         struct xhci_ep_ctx *ep_ctx;
 552         dma_addr_t addr;
 553         u64 hw_dequeue;
 554
 555         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 556                         ep_index, stream_id);
 557         if (!ep_ring) {
 558                 xhci_warn(xhci, "WARN can't find new dequeue state "
 559                                 "for invalid stream ID %u.\n",
 560                                 stream_id);
 561                 return;
 562         }
 563
 564         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 565         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 566                         "Finding endpoint context");
 567         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 568         hw_dequeue = le64_to_cpu(ep_ctx->deq);
 569
 570         /* Find virtual address and segment of hardware dequeue pointer */
 571         state->new_deq_seg = ep_ring->deq_seg;
 572         state->new_deq_ptr = ep_ring->dequeue;
 573         while (xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr)
 574                         != (dma_addr_t)(hw_dequeue & ~0xf)) {
 575                 next_trb(xhci, ep_ring, &state->new_deq_seg,
 576                                         &state->new_deq_ptr);
 577                 if (state->new_deq_ptr == ep_ring->dequeue) {
 578                         WARN_ON(1);
 579                         return;
 580                 }
 581         }
 582         /*
 583          * Find cycle state for last_trb, starting at old cycle state of
 584          * hw_dequeue. If there is only one segment ring, find_trb_seg() will
 585          * return immediately and cannot toggle the cycle state if this search
 586          * wraps around, so add one more toggle manually in that case.
 587          */
 588         state->new_cycle_state = hw_dequeue & 0x1;
 589         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 590                         cur_td->last_trb < state->new_deq_ptr)
 591                 state->new_cycle_state ^= 0x1;
 592
 593         state->new_deq_ptr = cur_td->last_trb;
 594         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 595                         "Finding segment containing last TRB in TD.");
 596         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 597                         state->new_deq_ptr, &state->new_cycle_state);
 598         if (!state->new_deq_seg) {
 599                 WARN_ON(1);
 600                 return;
 601         }
 602
 603         /* Increment to find next TRB after last_trb. Cycle if appropriate. */
 604         trb = &state->new_deq_ptr->generic;
 605         if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
 606             (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
 607                 state->new_cycle_state ^= 0x1;
 608         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 609
 610         /* Don't update the ring cycle state for the producer (us). */
 611         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 612                         "Cycle state = 0x%x", state->new_cycle_state);
 613
 614         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 615                         "New dequeue segment = %p (virtual)",
 616                         state->new_deq_seg);
 617         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 618         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 619                         "New dequeue pointer = 0x%llx (DMA)",
 620                         (unsigned long long) addr);
 621 }
 622
 623 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 624  * (The last TRB actually points to the ring enqueue pointer, which is not part
 625  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 626  */
 627 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 628                 struct xhci_td *cur_td, bool flip_cycle)
 629 {
 630         struct xhci_segment *cur_seg;
 631         union xhci_trb *cur_trb;
 632
 633         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 634                         true;
 635                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 636                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 637                         /* Unchain any chained Link TRBs, but
 638                          * leave the pointers intact.
 639                          */
 640                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 641                         /* Flip the cycle bit (link TRBs can't be the first
 642                          * or last TRB).
 643                          */
 644                         if (flip_cycle)
 645                                 cur_trb->generic.field[3] ^=
 646                                         cpu_to_le32(TRB_CYCLE);
 647                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 648                                         "Cancel (unchain) link TRB");
 649                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 650                                         "Address = %p (0x%llx dma); "
 651                                         "in seg %p (0x%llx dma)",
 652                                         cur_trb,
 653                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 654                                         cur_seg,
 655                                         (unsigned long long)cur_seg->dma);
 656                 } else {
 657                         cur_trb->generic.field[0] = 0;
 658                         cur_trb->generic.field[1] = 0;
 659                         cur_trb->generic.field[2] = 0;
 660                         /* Preserve only the cycle bit of this TRB */
 661                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 662                         /* Flip the cycle bit except on the first or last TRB */
 663                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 664                                         cur_trb != cur_td->last_trb)
 665                                 cur_trb->generic.field[3] ^=
 666                                         cpu_to_le32(TRB_CYCLE);
 667                         cur_trb->generic.field[3] |= cpu_to_le32(
 668                                 TRB_TYPE(TRB_TR_NOOP));
 669                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 670                                         "TRB to noop at offset 0x%llx",
 671                                         (unsigned long long)
 672                                         xhci_trb_virt_to_dma(cur_seg, cur_trb));
 673                 }
 674                 if (cur_trb == cur_td->last_trb)
 675                         break;
 676         }
 677 }
 678
 679 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 680                 unsigned int ep_index, unsigned int stream_id,
 681                 struct xhci_segment *deq_seg,
 682                 union xhci_trb *deq_ptr, u32 cycle_state);
 683
 684 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 685                 unsigned int slot_id, unsigned int ep_index,
 686                 unsigned int stream_id,
 687                 struct xhci_dequeue_state *deq_state)
 688 {
 689         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 690
 691         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 692                         "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 693                         "new deq ptr = %p (0x%llx dma), new cycle = %u",
 694                         deq_state->new_deq_seg,
 695                         (unsigned long long)deq_state->new_deq_seg->dma,
 696                         deq_state->new_deq_ptr,
 697                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 698                         deq_state->new_cycle_state);
 699         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 700                         deq_state->new_deq_seg,
 701                         deq_state->new_deq_ptr,
 702                         (u32) deq_state->new_cycle_state);
 703         /* Stop the TD queueing code from ringing the doorbell until
 704          * this command completes.  The HC won't set the dequeue pointer
 705          * if the ring is running, and ringing the doorbell starts the
 706          * ring running.
 707          */
 708         ep->ep_state |= SET_DEQ_PENDING;
 709 }
 710
 711 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 712                 struct xhci_virt_ep *ep)
 713 {
 714         ep->ep_state &= ~EP_HALT_PENDING;
 715         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 716          * timer is running on another CPU, we don't decrement stop_cmds_pending
 717          * (since we didn't successfully stop the watchdog timer).
 718          */
 719         if (del_timer(&ep->stop_cmd_timer))
 720                 ep->stop_cmds_pending--;
 721 }
 722
 723 /* Must be called with xhci->lock held in interrupt context */
 724 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 725                 struct xhci_td *cur_td, int status)
 726 {
 727         struct usb_hcd *hcd;
 728         struct urb      *urb;
 729         struct urb_priv *urb_priv;
 730
 731         urb = cur_td->urb;
 732         urb_priv = urb->hcpriv;
 733         urb_priv->td_cnt++;
 734         hcd = bus_to_hcd(urb->dev->bus);
 735
 736         /* Only giveback urb when this is the last td in urb */
 737         if (urb_priv->td_cnt == urb_priv->length) {
 738                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 739                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 740                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 741                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 742                                         usb_amd_quirk_pll_enable();
 743                         }
 744                 }
 745                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 746
 747                 spin_unlock(&xhci->lock);
 748                 usb_hcd_giveback_urb(hcd, urb, status);
 749                 xhci_urb_free_priv(xhci, urb_priv);
 750                 spin_lock(&xhci->lock);
 751         }
 752 }
 753
 754 /*
 755  * When we get a command completion for a Stop Endpoint Command, we need to
 756  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 757  *
 758  *  1. If the HW was in the middle of processing the TD that needs to be
 759  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 760  *     in the TD with a Set Dequeue Pointer Command.
 761  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 762  *     bit cleared) so that the HW will skip over them.
 763  */
 764 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
 765                 union xhci_trb *trb, struct xhci_event_cmd *event)
 766 {
 767         unsigned int ep_index;
 768         struct xhci_virt_device *virt_dev;
 769         struct xhci_ring *ep_ring;
 770         struct xhci_virt_ep *ep;
 771         struct list_head *entry;
 772         struct xhci_td *cur_td = NULL;
 773         struct xhci_td *last_unlinked_td;
 774
 775         struct xhci_dequeue_state deq_state;
 776
 777         if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
 778                 virt_dev = xhci->devs[slot_id];
 779                 if (virt_dev)
 780                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 781                                 event);
 782                 else
 783                         xhci_warn(xhci, "Stop endpoint command "
 784                                 "completion for disabled slot %u\n",
 785                                 slot_id);
 786                 return;
 787         }
 788
 789         memset(&deq_state, 0, sizeof(deq_state));
 790         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 791         ep = &xhci->devs[slot_id]->eps[ep_index];
 792
 793         if (list_empty(&ep->cancelled_td_list)) {
 794                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 795                 ep->stopped_td = NULL;
 796                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 797                 return;
 798         }
 799
 800         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 801          * We have the xHCI lock, so nothing can modify this list until we drop
 802          * it.  We're also in the event handler, so we can't get re-interrupted
 803          * if another Stop Endpoint command completes
 804          */
 805         list_for_each(entry, &ep->cancelled_td_list) {
 806                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 807                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 808                                 "Removing canceled TD starting at 0x%llx (dma).",
 809                                 (unsigned long long)xhci_trb_virt_to_dma(
 810                                         cur_td->start_seg, cur_td->first_trb));
 811                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 812                 if (!ep_ring) {
 813                         /* This shouldn't happen unless a driver is mucking
 814                          * with the stream ID after submission.  This will
 815                          * leave the TD on the hardware ring, and the hardware
 816                          * will try to execute it, and may access a buffer
 817                          * that has already been freed.  In the best case, the
 818                          * hardware will execute it, and the event handler will
 819                          * ignore the completion event for that TD, since it was
 820                          * removed from the td_list for that endpoint.  In
 821                          * short, don't muck with the stream ID after
 822                          * submission.
 823                          */
 824                         xhci_warn(xhci, "WARN Cancelled URB %p "
 825                                         "has invalid stream ID %u.\n",
 826                                         cur_td->urb,
 827                                         cur_td->urb->stream_id);
 828                         goto remove_finished_td;
 829                 }
 830                 /*
 831                  * If we stopped on the TD we need to cancel, then we have to
 832                  * move the xHC endpoint ring dequeue pointer past this TD.
 833                  */
 834                 if (cur_td == ep->stopped_td)
 835                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 836                                         cur_td->urb->stream_id,
 837                                         cur_td, &deq_state);
 838                 else
 839                         td_to_noop(xhci, ep_ring, cur_td, false);
 840 remove_finished_td:
 841                 /*
 842                  * The event handler won't see a completion for this TD anymore,
 843                  * so remove it from the endpoint ring's TD list.  Keep it in
 844                  * the cancelled TD list for URB completion later.
 845                  */
 846                 list_del_init(&cur_td->td_list);
 847         }
 848         last_unlinked_td = cur_td;
 849         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 850
 851         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 852         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 853                 xhci_queue_new_dequeue_state(xhci,
 854                                 slot_id, ep_index,
 855                                 ep->stopped_td->urb->stream_id,
 856                                 &deq_state);
 857                 xhci_ring_cmd_db(xhci);
 858         } else {
 859                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 860                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 861         }
 862
 863         /* Clear stopped_td if endpoint is not halted */
 864         if (!(ep->ep_state & EP_HALTED))
 865                 ep->stopped_td = NULL;
 866
 867         /*
 868          * Drop the lock and complete the URBs in the cancelled TD list.
 869          * New TDs to be cancelled might be added to the end of the list before
 870          * we can complete all the URBs for the TDs we already unlinked.
 871          * So stop when we've completed the URB for the last TD we unlinked.
 872          */
 873         do {
 874                 cur_td = list_entry(ep->cancelled_td_list.next,
 875                                 struct xhci_td, cancelled_td_list);
 876                 list_del_init(&cur_td->cancelled_td_list);
 877
 878                 /* Clean up the cancelled URB */
 879                 /* Doesn't matter what we pass for status, since the core will
 880                  * just overwrite it (because the URB has been unlinked).
 881                  */
 882                 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
 883
 884                 /* Stop processing the cancelled list if the watchdog timer is
 885                  * running.
 886                  */
 887                 if (xhci->xhc_state & XHCI_STATE_DYING)
 888                         return;
 889         } while (cur_td != last_unlinked_td);
 890
 891         /* Return to the event handler with xhci->lock re-acquired */
 892 }
 893
 894 /* Watchdog timer function for when a stop endpoint command fails to complete.
 895  * In this case, we assume the host controller is broken or dying or dead.  The
 896  * host may still be completing some other events, so we have to be careful to
 897  * let the event ring handler and the URB dequeueing/enqueueing functions know
 898  * through xhci->state.
 899  *
 900  * The timer may also fire if the host takes a very long time to respond to the
 901  * command, and the stop endpoint command completion handler cannot delete the
 902  * timer before the timer function is called.  Another endpoint cancellation may
 903  * sneak in before the timer function can grab the lock, and that may queue
 904  * another stop endpoint command and add the timer back.  So we cannot use a
 905  * simple flag to say whether there is a pending stop endpoint command for a
 906  * particular endpoint.
 907  *
 908  * Instead we use a combination of that flag and a counter for the number of
 909  * pending stop endpoint commands.  If the timer is the tail end of the last
 910  * stop endpoint command, and the endpoint's command is still pending, we assume
 911  * the host is dying.
 912  */
 913 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 914 {
 915         struct xhci_hcd *xhci;
 916         struct xhci_virt_ep *ep;
 917         struct xhci_virt_ep *temp_ep;
 918         struct xhci_ring *ring;
 919         struct xhci_td *cur_td;
 920         int ret, i, j;
 921         unsigned long flags;
 922
 923         ep = (struct xhci_virt_ep *) arg;
 924         xhci = ep->xhci;
 925
 926         spin_lock_irqsave(&xhci->lock, flags);
 927
 928         ep->stop_cmds_pending--;
 929         if (xhci->xhc_state & XHCI_STATE_DYING) {
 930                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 931                                 "Stop EP timer ran, but another timer marked "
 932                                 "xHCI as DYING, exiting.");
 933                 spin_unlock_irqrestore(&xhci->lock, flags);
 934                 return;
 935         }
 936         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 937                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 938                                 "Stop EP timer ran, but no command pending, "
 939                                 "exiting.");
 940                 spin_unlock_irqrestore(&xhci->lock, flags);
 941                 return;
 942         }
 943
 944         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 945         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 946         /* Oops, HC is dead or dying or at least not responding to the stop
 947          * endpoint command.
 948          */
 949         xhci->xhc_state |= XHCI_STATE_DYING;
 950         /* Disable interrupts from the host controller and start halting it */
 951         xhci_quiesce(xhci);
 952         spin_unlock_irqrestore(&xhci->lock, flags);
 953
 954         ret = xhci_halt(xhci);
 955
 956         spin_lock_irqsave(&xhci->lock, flags);
 957         if (ret < 0) {
 958                 /* This is bad; the host is not responding to commands and it's
 959                  * not allowing itself to be halted.  At least interrupts are
 960                  * disabled. If we call usb_hc_died(), it will attempt to
 961                  * disconnect all device drivers under this host.  Those
 962                  * disconnect() methods will wait for all URBs to be unlinked,
 963                  * so we must complete them.
 964                  */
 965                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 966                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 967                 /* We could turn all TDs on the rings to no-ops.  This won't
 968                  * help if the host has cached part of the ring, and is slow if
 969                  * we want to preserve the cycle bit.  Skip it and hope the host
 970                  * doesn't touch the memory.
 971                  */
 972         }
 973         for (i = 0; i < MAX_HC_SLOTS; i++) {
 974                 if (!xhci->devs[i])
 975                         continue;
 976                 for (j = 0; j < 31; j++) {
 977                         temp_ep = &xhci->devs[i]->eps[j];
 978                         ring = temp_ep->ring;
 979                         if (!ring)
 980                                 continue;
 981                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 982                                         "Killing URBs for slot ID %u, "
 983                                         "ep index %u", i, j);
 984                         while (!list_empty(&ring->td_list)) {
 985                                 cur_td = list_first_entry(&ring->td_list,
 986                                                 struct xhci_td,
 987                                                 td_list);
 988                                 list_del_init(&cur_td->td_list);
 989                                 if (!list_empty(&cur_td->cancelled_td_list))
 990                                         list_del_init(&cur_td->cancelled_td_list);
 991                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 992                                                 -ESHUTDOWN);
 993                         }
 994                         while (!list_empty(&temp_ep->cancelled_td_list)) {
 995                                 cur_td = list_first_entry(
 996                                                 &temp_ep->cancelled_td_list,
 997                                                 struct xhci_td,
 998                                                 cancelled_td_list);
 999                                 list_del_init(&cur_td->cancelled_td_list);
1000                                 xhci_giveback_urb_in_irq(xhci, cur_td,
1001                                                 -ESHUTDOWN);
1002                         }
1003                 }
1004         }
1005         spin_unlock_irqrestore(&xhci->lock, flags);
1006         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1007                         "Calling usb_hc_died()");
1008         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1009         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1010                         "xHCI host controller is dead.");
1011 }
1012
1013
1014 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1015                 struct xhci_virt_device *dev,
1016                 struct xhci_ring *ep_ring,
1017                 unsigned int ep_index)
1018 {
1019         union xhci_trb *dequeue_temp;
1020         int num_trbs_free_temp;
1021         bool revert = false;
1022
1023         num_trbs_free_temp = ep_ring->num_trbs_free;
1024         dequeue_temp = ep_ring->dequeue;
1025
1026         /* If we get two back-to-back stalls, and the first stalled transfer
1027          * ends just before a link TRB, the dequeue pointer will be left on
1028          * the link TRB by the code in the while loop.  So we have to update
1029          * the dequeue pointer one segment further, or we'll jump off
1030          * the segment into la-la-land.
1031          */
1032         if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
1033                 ep_ring->deq_seg = ep_ring->deq_seg->next;
1034                 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1035         }
1036
1037         while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1038                 /* We have more usable TRBs */
1039                 ep_ring->num_trbs_free++;
1040                 ep_ring->dequeue++;
1041                 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
1042                                 ep_ring->dequeue)) {
1043                         if (ep_ring->dequeue ==
1044                                         dev->eps[ep_index].queued_deq_ptr)
1045                                 break;
1046                         ep_ring->deq_seg = ep_ring->deq_seg->next;
1047                         ep_ring->dequeue = ep_ring->deq_seg->trbs;
1048                 }
1049                 if (ep_ring->dequeue == dequeue_temp) {
1050                         revert = true;
1051                         break;
1052                 }
1053         }
1054
1055         if (revert) {
1056                 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1057                 ep_ring->num_trbs_free = num_trbs_free_temp;
1058         }
1059 }
1060
1061 /*
1062  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1063  * we need to clear the set deq pending flag in the endpoint ring state, so that
1064  * the TD queueing code can ring the doorbell again.  We also need to ring the
1065  * endpoint doorbell to restart the ring, but only if there aren't more
1066  * cancellations pending.
1067  */
1068 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1069                 union xhci_trb *trb, u32 cmd_comp_code)
1070 {
1071         unsigned int ep_index;
1072         unsigned int stream_id;
1073         struct xhci_ring *ep_ring;
1074         struct xhci_virt_device *dev;
1075         struct xhci_ep_ctx *ep_ctx;
1076         struct xhci_slot_ctx *slot_ctx;
1077
1078         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1079         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1080         dev = xhci->devs[slot_id];
1081
1082         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1083         if (!ep_ring) {
1084                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
1085                                 "freed stream ID %u\n",
1086                                 stream_id);
1087                 /* XXX: Harmless??? */
1088                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1089                 return;
1090         }
1091
1092         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1093         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1094
1095         if (cmd_comp_code != COMP_SUCCESS) {
1096                 unsigned int ep_state;
1097                 unsigned int slot_state;
1098
1099                 switch (cmd_comp_code) {
1100                 case COMP_TRB_ERR:
1101                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
1102                                         "of stream ID configuration\n");
1103                         break;
1104                 case COMP_CTX_STATE:
1105                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
1106                                         "to incorrect slot or ep state.\n");
1107                         ep_state = le32_to_cpu(ep_ctx->ep_info);
1108                         ep_state &= EP_STATE_MASK;
1109                         slot_state = le32_to_cpu(slot_ctx->dev_state);
1110                         slot_state = GET_SLOT_STATE(slot_state);
1111                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1112                                         "Slot state = %u, EP state = %u",
1113                                         slot_state, ep_state);
1114                         break;
1115                 case COMP_EBADSLT:
1116                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
1117                                         "slot %u was not enabled.\n", slot_id);
1118                         break;
1119                 default:
1120                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
1121                                         "completion code of %u.\n",
1122                                   cmd_comp_code);
1123                         break;
1124                 }
1125                 /* OK what do we do now?  The endpoint state is hosed, and we
1126                  * should never get to this point if the synchronization between
1127                  * queueing, and endpoint state are correct.  This might happen
1128                  * if the device gets disconnected after we've finished
1129                  * cancelling URBs, which might not be an error...
1130                  */
1131         } else {
1132                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1133                         "Successful Set TR Deq Ptr cmd, deq = @%08llx",
1134                          le64_to_cpu(ep_ctx->deq));
1135                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
1136                                          dev->eps[ep_index].queued_deq_ptr) ==
1137                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
1138                         /* Update the ring's dequeue segment and dequeue pointer
1139                          * to reflect the new position.
1140                          */
1141                         update_ring_for_set_deq_completion(xhci, dev,
1142                                 ep_ring, ep_index);
1143                 } else {
1144                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1145                                         "Ptr command & xHCI internal state.\n");
1146                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1147                                         dev->eps[ep_index].queued_deq_seg,
1148                                         dev->eps[ep_index].queued_deq_ptr);
1149                 }
1150         }
1151
1152         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1153         dev->eps[ep_index].queued_deq_seg = NULL;
1154         dev->eps[ep_index].queued_deq_ptr = NULL;
1155         /* Restart any rings with pending URBs */
1156         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1157 }
1158
1159 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1160                 union xhci_trb *trb, u32 cmd_comp_code)
1161 {
1162         unsigned int ep_index;
1163
1164         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1165         /* This command will only fail if the endpoint wasn't halted,
1166          * but we don't care.
1167          */
1168         xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1169                 "Ignoring reset ep completion code of %u", cmd_comp_code);
1170
1171         /* HW with the reset endpoint quirk needs to have a configure endpoint
1172          * command complete before the endpoint can be used.  Queue that here
1173          * because the HW can't handle two commands being queued in a row.
1174          */
1175         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1176                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1177                                 "Queueing configure endpoint command");
1178                 xhci_queue_configure_endpoint(xhci,
1179                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1180                                 false);
1181                 xhci_ring_cmd_db(xhci);
1182         } else {
1183                 /* Clear our internal halted state */
1184                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1185         }
1186 }
1187
1188 /* Complete the command and detele it from the devcie's command queue.
1189  */
1190 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1191                 struct xhci_command *command, u32 status)
1192 {
1193         command->status = status;
1194         list_del(&command->cmd_list);
1195         if (command->completion)
1196                 complete(command->completion);
1197         else
1198                 xhci_free_command(xhci, command);
1199 }
1200
1201
1202 /* Check to see if a command in the device's command queue matches this one.
1203  * Signal the completion or free the command, and return 1.  Return 0 if the
1204  * completed command isn't at the head of the command list.
1205  */
1206 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1207                 struct xhci_virt_device *virt_dev,
1208                 struct xhci_event_cmd *event)
1209 {
1210         struct xhci_command *command;
1211
1212         if (list_empty(&virt_dev->cmd_list))
1213                 return 0;
1214
1215         command = list_entry(virt_dev->cmd_list.next,
1216                         struct xhci_command, cmd_list);
1217         if (xhci->cmd_ring->dequeue != command->command_trb)
1218                 return 0;
1219
1220         xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1221                         GET_COMP_CODE(le32_to_cpu(event->status)));
1222         return 1;
1223 }
1224
1225 /*
1226  * Finding the command trb need to be cancelled and modifying it to
1227  * NO OP command. And if the command is in device's command wait
1228  * list, finishing and freeing it.
1229  *
1230  * If we can't find the command trb, we think it had already been
1231  * executed.
1232  */
1233 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1234 {
1235         struct xhci_segment *cur_seg;
1236         union xhci_trb *cmd_trb;
1237         u32 cycle_state;
1238
1239         if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1240                 return;
1241
1242         /* find the current segment of command ring */
1243         cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1244                         xhci->cmd_ring->dequeue, &cycle_state);
1245
1246         if (!cur_seg) {
1247                 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1248                                 xhci->cmd_ring->dequeue,
1249                                 (unsigned long long)
1250                                 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1251                                         xhci->cmd_ring->dequeue));
1252                 xhci_debug_ring(xhci, xhci->cmd_ring);
1253                 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1254                 return;
1255         }
1256
1257         /* find the command trb matched by cd from command ring */
1258         for (cmd_trb = xhci->cmd_ring->dequeue;
1259                         cmd_trb != xhci->cmd_ring->enqueue;
1260                         next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1261                 /* If the trb is link trb, continue */
1262                 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1263                         continue;
1264
1265                 if (cur_cd->cmd_trb == cmd_trb) {
1266
1267                         /* If the command in device's command list, we should
1268                          * finish it and free the command structure.
1269                          */
1270                         if (cur_cd->command)
1271                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1272                                         cur_cd->command, COMP_CMD_STOP);
1273
1274                         /* get cycle state from the origin command trb */
1275                         cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1276                                 & TRB_CYCLE;
1277
1278                         /* modify the command trb to NO OP command */
1279                         cmd_trb->generic.field[0] = 0;
1280                         cmd_trb->generic.field[1] = 0;
1281                         cmd_trb->generic.field[2] = 0;
1282                         cmd_trb->generic.field[3] = cpu_to_le32(
1283                                         TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1284                         break;
1285                 }
1286         }
1287 }
1288
1289 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1290 {
1291         struct xhci_cd *cur_cd, *next_cd;
1292
1293         if (list_empty(&xhci->cancel_cmd_list))
1294                 return;
1295
1296         list_for_each_entry_safe(cur_cd, next_cd,
1297                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1298                 xhci_cmd_to_noop(xhci, cur_cd);
1299                 list_del(&cur_cd->cancel_cmd_list);
1300                 kfree(cur_cd);
1301         }
1302 }
1303
1304 /*
1305  * traversing the cancel_cmd_list. If the command descriptor according
1306  * to cmd_trb is found, the function free it and return 1, otherwise
1307  * return 0.
1308  */
1309 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1310                 union xhci_trb *cmd_trb)
1311 {
1312         struct xhci_cd *cur_cd, *next_cd;
1313
1314         if (list_empty(&xhci->cancel_cmd_list))
1315                 return 0;
1316
1317         list_for_each_entry_safe(cur_cd, next_cd,
1318                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1319                 if (cur_cd->cmd_trb == cmd_trb) {
1320                         if (cur_cd->command)
1321                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1322                                         cur_cd->command, COMP_CMD_STOP);
1323                         list_del(&cur_cd->cancel_cmd_list);
1324                         kfree(cur_cd);
1325                         return 1;
1326                 }
1327         }
1328
1329         return 0;
1330 }
1331
1332 /*
1333  * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1334  * trb pointed by the command ring dequeue pointer is the trb we want to
1335  * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1336  * traverse the cancel_cmd_list to trun the all of the commands according
1337  * to command descriptor to NO-OP trb.
1338  */
1339 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1340                 int cmd_trb_comp_code)
1341 {
1342         int cur_trb_is_good = 0;
1343
1344         /* Searching the cmd trb pointed by the command ring dequeue
1345          * pointer in command descriptor list. If it is found, free it.
1346          */
1347         cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1348                         xhci->cmd_ring->dequeue);
1349
1350         if (cmd_trb_comp_code == COMP_CMD_ABORT)
1351                 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1352         else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1353                 /* traversing the cancel_cmd_list and canceling
1354                  * the command according to command descriptor
1355                  */
1356                 xhci_cancel_cmd_in_cd_list(xhci);
1357
1358                 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1359                 /*
1360                  * ring command ring doorbell again to restart the
1361                  * command ring
1362                  */
1363                 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1364                         xhci_ring_cmd_db(xhci);
1365         }
1366         return cur_trb_is_good;
1367 }
1368
1369 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1370                 u32 cmd_comp_code)
1371 {
1372         if (cmd_comp_code == COMP_SUCCESS)
1373                 xhci->slot_id = slot_id;
1374         else
1375                 xhci->slot_id = 0;
1376         complete(&xhci->addr_dev);
1377 }
1378
1379 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1380 {
1381         struct xhci_virt_device *virt_dev;
1382
1383         virt_dev = xhci->devs[slot_id];
1384         if (!virt_dev)
1385                 return;
1386         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1387                 /* Delete default control endpoint resources */
1388                 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1389         xhci_free_virt_device(xhci, slot_id);
1390 }
1391
1392 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1393                 struct xhci_event_cmd *event, u32 cmd_comp_code)
1394 {
1395         struct xhci_virt_device *virt_dev;
1396         struct xhci_input_control_ctx *ctrl_ctx;
1397         unsigned int ep_index;
1398         unsigned int ep_state;
1399         u32 add_flags, drop_flags;
1400
1401         virt_dev = xhci->devs[slot_id];
1402         if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1403                 return;
1404         /*
1405          * Configure endpoint commands can come from the USB core
1406          * configuration or alt setting changes, or because the HW
1407          * needed an extra configure endpoint command after a reset
1408          * endpoint command or streams were being configured.
1409          * If the command was for a halted endpoint, the xHCI driver
1410          * is not waiting on the configure endpoint command.
1411          */
1412         ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1413         if (!ctrl_ctx) {
1414                 xhci_warn(xhci, "Could not get input context, bad type.\n");
1415                 return;
1416         }
1417
1418         add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1419         drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1420         /* Input ctx add_flags are the endpoint index plus one */
1421         ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1422
1423         /* A usb_set_interface() call directly after clearing a halted
1424          * condition may race on this quirky hardware.  Not worth
1425          * worrying about, since this is prototype hardware.  Not sure
1426          * if this will work for streams, but streams support was
1427          * untested on this prototype.
1428          */
1429         if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1430                         ep_index != (unsigned int) -1 &&
1431                         add_flags - SLOT_FLAG == drop_flags) {
1432                 ep_state = virt_dev->eps[ep_index].ep_state;
1433                 if (!(ep_state & EP_HALTED))
1434                         goto bandwidth_change;
1435                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1436                                 "Completed config ep cmd - "
1437                                 "last ep index = %d, state = %d",
1438                                 ep_index, ep_state);
1439                 /* Clear internal halted state and restart ring(s) */
1440                 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1441                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1442                 return;
1443         }
1444 bandwidth_change:
1445         xhci_dbg_trace(xhci,  trace_xhci_dbg_context_change,
1446                         "Completed config ep cmd");
1447         virt_dev->cmd_status = cmd_comp_code;
1448         complete(&virt_dev->cmd_completion);
1449         return;
1450 }
1451
1452 static void xhci_handle_cmd_eval_ctx(struct xhci_hcd *xhci, int slot_id,
1453                 struct xhci_event_cmd *event, u32 cmd_comp_code)
1454 {
1455         struct xhci_virt_device *virt_dev;
1456
1457         virt_dev = xhci->devs[slot_id];
1458         if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1459                 return;
1460         virt_dev->cmd_status = cmd_comp_code;
1461         complete(&virt_dev->cmd_completion);
1462 }
1463
1464 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id,
1465                 u32 cmd_comp_code)
1466 {
1467         xhci->devs[slot_id]->cmd_status = cmd_comp_code;
1468         complete(&xhci->addr_dev);
1469 }
1470
1471 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1472                 struct xhci_event_cmd *event)
1473 {
1474         struct xhci_virt_device *virt_dev;
1475
1476         xhci_dbg(xhci, "Completed reset device command.\n");
1477         virt_dev = xhci->devs[slot_id];
1478         if (virt_dev)
1479                 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1480         else
1481                 xhci_warn(xhci, "Reset device command completion "
1482                                 "for disabled slot %u\n", slot_id);
1483 }
1484
1485 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1486                 struct xhci_event_cmd *event)
1487 {
1488         if (!(xhci->quirks & XHCI_NEC_HOST)) {
1489                 xhci->error_bitmask |= 1 << 6;
1490                 return;
1491         }
1492         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1493                         "NEC firmware version %2x.%02x",
1494                         NEC_FW_MAJOR(le32_to_cpu(event->status)),
1495                         NEC_FW_MINOR(le32_to_cpu(event->status)));
1496 }
1497
1498 static void handle_cmd_completion(struct xhci_hcd *xhci,
1499                 struct xhci_event_cmd *event)
1500 {
1501         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1502         u64 cmd_dma;
1503         dma_addr_t cmd_dequeue_dma;
1504         u32 cmd_comp_code;
1505         union xhci_trb *cmd_trb;
1506         u32 cmd_type;
1507
1508         cmd_dma = le64_to_cpu(event->cmd_trb);
1509         cmd_trb = xhci->cmd_ring->dequeue;
1510         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1511                         cmd_trb);
1512         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1513         if (cmd_dequeue_dma == 0) {
1514                 xhci->error_bitmask |= 1 << 4;
1515                 return;
1516         }
1517         /* Does the DMA address match our internal dequeue pointer address? */
1518         if (cmd_dma != (u64) cmd_dequeue_dma) {
1519                 xhci->error_bitmask |= 1 << 5;
1520                 return;
1521         }
1522
1523         trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event);
1524
1525         cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1526         if (cmd_comp_code == COMP_CMD_ABORT || cmd_comp_code == COMP_CMD_STOP) {
1527                 /* If the return value is 0, we think the trb pointed by
1528                  * command ring dequeue pointer is a good trb. The good
1529                  * trb means we don't want to cancel the trb, but it have
1530                  * been stopped by host. So we should handle it normally.
1531                  * Otherwise, driver should invoke inc_deq() and return.
1532                  */
1533                 if (handle_stopped_cmd_ring(xhci, cmd_comp_code)) {
1534                         inc_deq(xhci, xhci->cmd_ring);
1535                         return;
1536                 }
1537                 /* There is no command to handle if we get a stop event when the
1538                  * command ring is empty, event->cmd_trb points to the next
1539                  * unset command
1540                  */
1541                 if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1542                         return;
1543         }
1544
1545         cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1546         switch (cmd_type) {
1547         case TRB_ENABLE_SLOT:
1548                 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code);
1549                 break;
1550         case TRB_DISABLE_SLOT:
1551                 xhci_handle_cmd_disable_slot(xhci, slot_id);
1552                 break;
1553         case TRB_CONFIG_EP:
1554                 xhci_handle_cmd_config_ep(xhci, slot_id, event, cmd_comp_code);
1555                 break;
1556         case TRB_EVAL_CONTEXT:
1557                 xhci_handle_cmd_eval_ctx(xhci, slot_id, event, cmd_comp_code);
1558                 break;
1559         case TRB_ADDR_DEV:
1560                 xhci_handle_cmd_addr_dev(xhci, slot_id, cmd_comp_code);
1561                 break;
1562         case TRB_STOP_RING:
1563                 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1564                                 le32_to_cpu(cmd_trb->generic.field[3])));
1565                 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1566                 break;
1567         case TRB_SET_DEQ:
1568                 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1569                                 le32_to_cpu(cmd_trb->generic.field[3])));
1570                 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1571                 break;
1572         case TRB_CMD_NOOP:
1573                 break;
1574         case TRB_RESET_EP:
1575                 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1576                                 le32_to_cpu(cmd_trb->generic.field[3])));
1577                 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1578                 break;
1579         case TRB_RESET_DEV:
1580                 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1581                  * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1582                  */
1583                 slot_id = TRB_TO_SLOT_ID(
1584                                 le32_to_cpu(cmd_trb->generic.field[3]));
1585                 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1586                 break;
1587         case TRB_NEC_GET_FW:
1588                 xhci_handle_cmd_nec_get_fw(xhci, event);
1589                 break;
1590         default:
1591                 /* Skip over unknown commands on the event ring */
1592                 xhci->error_bitmask |= 1 << 6;
1593                 break;
1594         }
1595         inc_deq(xhci, xhci->cmd_ring);
1596 }
1597
1598 static void handle_vendor_event(struct xhci_hcd *xhci,
1599                 union xhci_trb *event)
1600 {
1601         u32 trb_type;
1602
1603         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1604         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1605         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1606                 handle_cmd_completion(xhci, &event->event_cmd);
1607 }
1608
1609 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1610  * port registers -- USB 3.0 and USB 2.0).
1611  *
1612  * Returns a zero-based port number, which is suitable for indexing into each of
1613  * the split roothubs' port arrays and bus state arrays.
1614  * Add one to it in order to call xhci_find_slot_id_by_port.
1615  */
1616 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1617                 struct xhci_hcd *xhci, u32 port_id)
1618 {
1619         unsigned int i;
1620         unsigned int num_similar_speed_ports = 0;
1621
1622         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1623          * and usb2_ports are 0-based indexes.  Count the number of similar
1624          * speed ports, up to 1 port before this port.
1625          */
1626         for (i = 0; i < (port_id - 1); i++) {
1627                 u8 port_speed = xhci->port_array[i];
1628
1629                 /*
1630                  * Skip ports that don't have known speeds, or have duplicate
1631                  * Extended Capabilities port speed entries.
1632                  */
1633                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1634                         continue;
1635
1636                 /*
1637                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1638                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1639                  * matches the device speed, it's a similar speed port.
1640                  */
1641                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1642                         num_similar_speed_ports++;
1643         }
1644         return num_similar_speed_ports;
1645 }
1646
1647 static void handle_device_notification(struct xhci_hcd *xhci,
1648                 union xhci_trb *event)
1649 {
1650         u32 slot_id;
1651         struct usb_device *udev;
1652
1653         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1654         if (!xhci->devs[slot_id]) {
1655                 xhci_warn(xhci, "Device Notification event for "
1656                                 "unused slot %u\n", slot_id);
1657                 return;
1658         }
1659
1660         xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1661                         slot_id);
1662         udev = xhci->devs[slot_id]->udev;
1663         if (udev && udev->parent)
1664                 usb_wakeup_notification(udev->parent, udev->portnum);
1665 }
1666
1667 static void handle_port_status(struct xhci_hcd *xhci,
1668                 union xhci_trb *event)
1669 {
1670         struct usb_hcd *hcd;
1671         u32 port_id;
1672         u32 temp, temp1;
1673         int max_ports;
1674         int slot_id;
1675         unsigned int faked_port_index;
1676         u8 major_revision;
1677         struct xhci_bus_state *bus_state;
1678         __le32 __iomem **port_array;
1679         bool bogus_port_status = false;
1680
1681         /* Port status change events always have a successful completion code */
1682         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1683                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1684                 xhci->error_bitmask |= 1 << 8;
1685         }
1686         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1687         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1688
1689         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1690         if ((port_id <= 0) || (port_id > max_ports)) {
1691                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1692                 inc_deq(xhci, xhci->event_ring);
1693                 return;
1694         }
1695
1696         /* Figure out which usb_hcd this port is attached to:
1697          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1698          */
1699         major_revision = xhci->port_array[port_id - 1];
1700
1701         /* Find the right roothub. */
1702         hcd = xhci_to_hcd(xhci);
1703         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1704                 hcd = xhci->shared_hcd;
1705
1706         if (major_revision == 0) {
1707                 xhci_warn(xhci, "Event for port %u not in "
1708                                 "Extended Capabilities, ignoring.\n",
1709                                 port_id);
1710                 bogus_port_status = true;
1711                 goto cleanup;
1712         }
1713         if (major_revision == DUPLICATE_ENTRY) {
1714                 xhci_warn(xhci, "Event for port %u duplicated in"
1715                                 "Extended Capabilities, ignoring.\n",
1716                                 port_id);
1717                 bogus_port_status = true;
1718                 goto cleanup;
1719         }
1720
1721         /*
1722          * Hardware port IDs reported by a Port Status Change Event include USB
1723          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1724          * resume event, but we first need to translate the hardware port ID
1725          * into the index into the ports on the correct split roothub, and the
1726          * correct bus_state structure.
1727          */
1728         bus_state = &xhci->bus_state[hcd_index(hcd)];
1729         if (hcd->speed == HCD_USB3)
1730                 port_array = xhci->usb3_ports;
1731         else
1732                 port_array = xhci->usb2_ports;
1733         /* Find the faked port hub number */
1734         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1735                         port_id);
1736
1737         temp = readl(port_array[faked_port_index]);
1738         if (hcd->state == HC_STATE_SUSPENDED) {
1739                 xhci_dbg(xhci, "resume root hub\n");
1740                 usb_hcd_resume_root_hub(hcd);
1741         }
1742
1743         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1744                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1745
1746                 temp1 = readl(&xhci->op_regs->command);
1747                 if (!(temp1 & CMD_RUN)) {
1748                         xhci_warn(xhci, "xHC is not running.\n");
1749                         goto cleanup;
1750                 }
1751
1752                 if (DEV_SUPERSPEED(temp)) {
1753                         xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1754                         /* Set a flag to say the port signaled remote wakeup,
1755                          * so we can tell the difference between the end of
1756                          * device and host initiated resume.
1757                          */
1758                         bus_state->port_remote_wakeup |= 1 << faked_port_index;
1759                         xhci_test_and_clear_bit(xhci, port_array,
1760                                         faked_port_index, PORT_PLC);
1761                         xhci_set_link_state(xhci, port_array, faked_port_index,
1762                                                 XDEV_U0);
1763                         /* Need to wait until the next link state change
1764                          * indicates the device is actually in U0.
1765                          */
1766                         bogus_port_status = true;
1767                         goto cleanup;
1768                 } else {
1769                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1770                         bus_state->resume_done[faked_port_index] = jiffies +
1771                                 msecs_to_jiffies(20);
1772                         set_bit(faked_port_index, &bus_state->resuming_ports);
1773                         mod_timer(&hcd->rh_timer,
1774                                   bus_state->resume_done[faked_port_index]);
1775                         /* Do the rest in GetPortStatus */
1776                 }
1777         }
1778
1779         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1780                         DEV_SUPERSPEED(temp)) {
1781                 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1782                 /* We've just brought the device into U0 through either the
1783                  * Resume state after a device remote wakeup, or through the
1784                  * U3Exit state after a host-initiated resume.  If it's a device
1785                  * initiated remote wake, don't pass up the link state change,
1786                  * so the roothub behavior is consistent with external
1787                  * USB 3.0 hub behavior.
1788                  */
1789                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1790                                 faked_port_index + 1);
1791                 if (slot_id && xhci->devs[slot_id])
1792                         xhci_ring_device(xhci, slot_id);
1793                 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1794                         bus_state->port_remote_wakeup &=
1795                                 ~(1 << faked_port_index);
1796                         xhci_test_and_clear_bit(xhci, port_array,
1797                                         faked_port_index, PORT_PLC);
1798                         usb_wakeup_notification(hcd->self.root_hub,
1799                                         faked_port_index + 1);
1800                         bogus_port_status = true;
1801                         goto cleanup;
1802                 }
1803         }
1804
1805         /*
1806          * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1807          * RExit to a disconnect state).  If so, let the the driver know it's
1808          * out of the RExit state.
1809          */
1810         if (!DEV_SUPERSPEED(temp) &&
1811                         test_and_clear_bit(faked_port_index,
1812                                 &bus_state->rexit_ports)) {
1813                 complete(&bus_state->rexit_done[faked_port_index]);
1814                 bogus_port_status = true;
1815                 goto cleanup;
1816         }
1817
1818         if (hcd->speed != HCD_USB3)
1819                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1820                                         PORT_PLC);
1821
1822 cleanup:
1823         /* Update event ring dequeue pointer before dropping the lock */
1824         inc_deq(xhci, xhci->event_ring);
1825
1826         /* Don't make the USB core poll the roothub if we got a bad port status
1827          * change event.  Besides, at that point we can't tell which roothub
1828          * (USB 2.0 or USB 3.0) to kick.
1829          */
1830         if (bogus_port_status)
1831                 return;
1832
1833         /*
1834          * xHCI port-status-change events occur when the "or" of all the
1835          * status-change bits in the portsc register changes from 0 to 1.
1836          * New status changes won't cause an event if any other change
1837          * bits are still set.  When an event occurs, switch over to
1838          * polling to avoid losing status changes.
1839          */
1840         xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1841         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1842         spin_unlock(&xhci->lock);
1843         /* Pass this up to the core */
1844         usb_hcd_poll_rh_status(hcd);
1845         spin_lock(&xhci->lock);
1846 }
1847
1848 /*
1849  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1850  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1851  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1852  * returns 0.
1853  */
1854 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1855                 union xhci_trb  *start_trb,
1856                 union xhci_trb  *end_trb,
1857                 dma_addr_t      suspect_dma)
1858 {
1859         dma_addr_t start_dma;
1860         dma_addr_t end_seg_dma;
1861         dma_addr_t end_trb_dma;
1862         struct xhci_segment *cur_seg;
1863
1864         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1865         cur_seg = start_seg;
1866
1867         do {
1868                 if (start_dma == 0)
1869                         return NULL;
1870                 /* We may get an event for a Link TRB in the middle of a TD */
1871                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1872                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1873                 /* If the end TRB isn't in this segment, this is set to 0 */
1874                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1875
1876                 if (end_trb_dma > 0) {
1877                         /* The end TRB is in this segment, so suspect should be here */
1878                         if (start_dma <= end_trb_dma) {
1879                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1880                                         return cur_seg;
1881                         } else {
1882                                 /* Case for one segment with
1883                                  * a TD wrapped around to the top
1884                                  */
1885                                 if ((suspect_dma >= start_dma &&
1886                                                         suspect_dma <= end_seg_dma) ||
1887                                                 (suspect_dma >= cur_seg->dma &&
1888                                                  suspect_dma <= end_trb_dma))
1889                                         return cur_seg;
1890                         }
1891                         return NULL;
1892                 } else {
1893                         /* Might still be somewhere in this segment */
1894                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1895                                 return cur_seg;
1896                 }
1897                 cur_seg = cur_seg->next;
1898                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1899         } while (cur_seg != start_seg);
1900
1901         return NULL;
1902 }
1903
1904 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1905                 unsigned int slot_id, unsigned int ep_index,
1906                 unsigned int stream_id,
1907                 struct xhci_td *td, union xhci_trb *event_trb)
1908 {
1909         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1910         ep->ep_state |= EP_HALTED;
1911         ep->stopped_td = td;
1912         ep->stopped_stream = stream_id;
1913
1914         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1915         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1916
1917         ep->stopped_td = NULL;
1918         ep->stopped_stream = 0;
1919
1920         xhci_ring_cmd_db(xhci);
1921 }
1922
1923 /* Check if an error has halted the endpoint ring.  The class driver will
1924  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1925  * However, a babble and other errors also halt the endpoint ring, and the class
1926  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1927  * Ring Dequeue Pointer command manually.
1928  */
1929 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1930                 struct xhci_ep_ctx *ep_ctx,
1931                 unsigned int trb_comp_code)
1932 {
1933         /* TRB completion codes that may require a manual halt cleanup */
1934         if (trb_comp_code == COMP_TX_ERR ||
1935                         trb_comp_code == COMP_BABBLE ||
1936                         trb_comp_code == COMP_SPLIT_ERR)
1937                 /* The 0.96 spec says a babbling control endpoint
1938                  * is not halted. The 0.96 spec says it is.  Some HW
1939                  * claims to be 0.95 compliant, but it halts the control
1940                  * endpoint anyway.  Check if a babble halted the
1941                  * endpoint.
1942                  */
1943                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1944                     cpu_to_le32(EP_STATE_HALTED))
1945                         return 1;
1946
1947         return 0;
1948 }
1949
1950 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1951 {
1952         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1953                 /* Vendor defined "informational" completion code,
1954                  * treat as not-an-error.
1955                  */
1956                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1957                                 trb_comp_code);
1958                 xhci_dbg(xhci, "Treating code as success.\n");
1959                 return 1;
1960         }
1961         return 0;
1962 }
1963
1964 /*
1965  * Finish the td processing, remove the td from td list;
1966  * Return 1 if the urb can be given back.
1967  */
1968 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1969         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1970         struct xhci_virt_ep *ep, int *status, bool skip)
1971 {
1972         struct xhci_virt_device *xdev;
1973         struct xhci_ring *ep_ring;
1974         unsigned int slot_id;
1975         int ep_index;
1976         struct urb *urb = NULL;
1977         struct xhci_ep_ctx *ep_ctx;
1978         int ret = 0;
1979         struct urb_priv *urb_priv;
1980         u32 trb_comp_code;
1981
1982         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1983         xdev = xhci->devs[slot_id];
1984         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1985         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1986         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1987         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1988
1989         if (skip)
1990                 goto td_cleanup;
1991
1992         if (trb_comp_code == COMP_STOP_INVAL ||
1993                         trb_comp_code == COMP_STOP) {
1994                 /* The Endpoint Stop Command completion will take care of any
1995                  * stopped TDs.  A stopped TD may be restarted, so don't update
1996                  * the ring dequeue pointer or take this TD off any lists yet.
1997                  */
1998                 ep->stopped_td = td;
1999                 return 0;
2000         } else {
2001                 if (trb_comp_code == COMP_STALL ||
2002                     xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2003                                                       trb_comp_code)) {
2004                         /* Issue a reset endpoint command to clear the host side
2005                          * halt, followed by a set dequeue command to move the
2006                          * dequeue pointer past the TD.
2007                          * The class driver clears the device side halt later.
2008                          */
2009                         xhci_cleanup_halted_endpoint(xhci,
2010                                         slot_id, ep_index, ep_ring->stream_id,
2011                                         td, event_trb);
2012                 } else {
2013                         /* Update ring dequeue pointer */
2014                         while (ep_ring->dequeue != td->last_trb)
2015                                 inc_deq(xhci, ep_ring);
2016                         inc_deq(xhci, ep_ring);
2017                 }
2018
2019 td_cleanup:
2020                 /* Clean up the endpoint's TD list */
2021                 urb = td->urb;
2022                 urb_priv = urb->hcpriv;
2023
2024                 /* Do one last check of the actual transfer length.
2025                  * If the host controller said we transferred more data than
2026                  * the buffer length, urb->actual_length will be a very big
2027                  * number (since it's unsigned).  Play it safe and say we didn't
2028                  * transfer anything.
2029                  */
2030                 if (urb->actual_length > urb->transfer_buffer_length) {
2031                         xhci_warn(xhci, "URB transfer length is wrong, "
2032                                         "xHC issue? req. len = %u, "
2033                                         "act. len = %u\n",
2034                                         urb->transfer_buffer_length,
2035                                         urb->actual_length);
2036                         urb->actual_length = 0;
2037                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2038                                 *status = -EREMOTEIO;
2039                         else
2040                                 *status = 0;
2041                 }
2042                 list_del_init(&td->td_list);
2043                 /* Was this TD slated to be cancelled but completed anyway? */
2044                 if (!list_empty(&td->cancelled_td_list))
2045                         list_del_init(&td->cancelled_td_list);
2046
2047                 urb_priv->td_cnt++;
2048                 /* Giveback the urb when all the tds are completed */
2049                 if (urb_priv->td_cnt == urb_priv->length) {
2050                         ret = 1;
2051                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2052                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
2053                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
2054                                         == 0) {
2055                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
2056                                                 usb_amd_quirk_pll_enable();
2057                                 }
2058                         }
2059                 }
2060         }
2061
2062         return ret;
2063 }
2064
2065 /*
2066  * Process control tds, update urb status and actual_length.
2067  */
2068 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
2069         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2070         struct xhci_virt_ep *ep, int *status)
2071 {
2072         struct xhci_virt_device *xdev;
2073         struct xhci_ring *ep_ring;
2074         unsigned int slot_id;
2075         int ep_index;
2076         struct xhci_ep_ctx *ep_ctx;
2077         u32 trb_comp_code;
2078
2079         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2080         xdev = xhci->devs[slot_id];
2081         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2082         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2083         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2084         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2085
2086         switch (trb_comp_code) {
2087         case COMP_SUCCESS:
2088                 if (event_trb == ep_ring->dequeue) {
2089                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
2090                                         "without IOC set??\n");
2091                         *status = -ESHUTDOWN;
2092                 } else if (event_trb != td->last_trb) {
2093                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
2094                                         "without IOC set??\n");
2095                         *status = -ESHUTDOWN;
2096                 } else {
2097                         *status = 0;
2098                 }
2099                 break;
2100         case COMP_SHORT_TX:
2101                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2102                         *status = -EREMOTEIO;
2103                 else
2104                         *status = 0;
2105                 break;
2106         case COMP_STOP_INVAL:
2107         case COMP_STOP:
2108                 return finish_td(xhci, td, event_trb, event, ep, status, false);
2109         default:
2110                 if (!xhci_requires_manual_halt_cleanup(xhci,
2111                                         ep_ctx, trb_comp_code))
2112                         break;
2113                 xhci_dbg(xhci, "TRB error code %u, "
2114                                 "halted endpoint index = %u\n",
2115                                 trb_comp_code, ep_index);
2116                 /* else fall through */
2117         case COMP_STALL:
2118                 /* Did we transfer part of the data (middle) phase? */
2119                 if (event_trb != ep_ring->dequeue &&
2120                                 event_trb != td->last_trb)
2121                         td->urb->actual_length =
2122                                 td->urb->transfer_buffer_length -
2123                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2124                 else
2125                         td->urb->actual_length = 0;
2126
2127                 return finish_td(xhci, td, event_trb, event, ep, status, false);
2128         }
2129         /*
2130          * Did we transfer any data, despite the errors that might have
2131          * happened?  I.e. did we get past the setup stage?
2132          */
2133         if (event_trb != ep_ring->dequeue) {
2134                 /* The event was for the status stage */
2135                 if (event_trb == td->last_trb) {
2136                         if (td->urb->actual_length != 0) {
2137                                 /* Don't overwrite a previously set error code
2138                                  */
2139                                 if ((*status == -EINPROGRESS || *status == 0) &&
2140                                                 (td->urb->transfer_flags
2141                                                  & URB_SHORT_NOT_OK))
2142                                         /* Did we already see a short data
2143                                          * stage? */
2144                                         *status = -EREMOTEIO;
2145                         } else {
2146                                 td->urb->actual_length =
2147                                         td->urb->transfer_buffer_length;
2148                         }
2149                 } else {
2150                 /* Maybe the event was for the data stage? */
2151                         td->urb->actual_length =
2152                                 td->urb->transfer_buffer_length -
2153                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2154                         xhci_dbg(xhci, "Waiting for status "
2155                                         "stage event\n");
2156                         return 0;
2157                 }
2158         }
2159
2160         return finish_td(xhci, td, event_trb, event, ep, status, false);
2161 }
2162
2163 /*
2164  * Process isochronous tds, update urb packet status and actual_length.
2165  */
2166 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2167         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2168         struct xhci_virt_ep *ep, int *status)
2169 {
2170         struct xhci_ring *ep_ring;
2171         struct urb_priv *urb_priv;
2172         int idx;
2173         int len = 0;
2174         union xhci_trb *cur_trb;
2175         struct xhci_segment *cur_seg;
2176         struct usb_iso_packet_descriptor *frame;
2177         u32 trb_comp_code;
2178         bool skip_td = false;
2179
2180         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2181         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2182         urb_priv = td->urb->hcpriv;
2183         idx = urb_priv->td_cnt;
2184         frame = &td->urb->iso_frame_desc[idx];
2185
2186         /* handle completion code */
2187         switch (trb_comp_code) {
2188         case COMP_SUCCESS:
2189                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2190                         frame->status = 0;
2191                         break;
2192                 }
2193                 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2194                         trb_comp_code = COMP_SHORT_TX;
2195         case COMP_SHORT_TX:
2196                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2197                                 -EREMOTEIO : 0;
2198                 break;
2199         case COMP_BW_OVER:
2200                 frame->status = -ECOMM;
2201                 skip_td = true;
2202                 break;
2203         case COMP_BUFF_OVER:
2204         case COMP_BABBLE:
2205                 frame->status = -EOVERFLOW;
2206                 skip_td = true;
2207                 break;
2208         case COMP_DEV_ERR:
2209         case COMP_STALL:
2210         case COMP_TX_ERR:
2211                 frame->status = -EPROTO;
2212                 skip_td = true;
2213                 break;
2214         case COMP_STOP:
2215         case COMP_STOP_INVAL:
2216                 break;
2217         default:
2218                 frame->status = -1;
2219                 break;
2220         }
2221
2222         if (trb_comp_code == COMP_SUCCESS || skip_td) {
2223                 frame->actual_length = frame->length;
2224                 td->urb->actual_length += frame->length;
2225         } else {
2226                 for (cur_trb = ep_ring->dequeue,
2227                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2228                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2229                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2230                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2231                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2232                 }
2233                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2234                         EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2235
2236                 if (trb_comp_code != COMP_STOP_INVAL) {
2237                         frame->actual_length = len;
2238                         td->urb->actual_length += len;
2239                 }
2240         }
2241
2242         return finish_td(xhci, td, event_trb, event, ep, status, false);
2243 }
2244
2245 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2246                         struct xhci_transfer_event *event,
2247                         struct xhci_virt_ep *ep, int *status)
2248 {
2249         struct xhci_ring *ep_ring;
2250         struct urb_priv *urb_priv;
2251         struct usb_iso_packet_descriptor *frame;
2252         int idx;
2253
2254         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2255         urb_priv = td->urb->hcpriv;
2256         idx = urb_priv->td_cnt;
2257         frame = &td->urb->iso_frame_desc[idx];
2258
2259         /* The transfer is partly done. */
2260         frame->status = -EXDEV;
2261
2262         /* calc actual length */
2263         frame->actual_length = 0;
2264
2265         /* Update ring dequeue pointer */
2266         while (ep_ring->dequeue != td->last_trb)
2267                 inc_deq(xhci, ep_ring);
2268         inc_deq(xhci, ep_ring);
2269
2270         return finish_td(xhci, td, NULL, event, ep, status, true);
2271 }
2272
2273 /*
2274  * Process bulk and interrupt tds, update urb status and actual_length.
2275  */
2276 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2277         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2278         struct xhci_virt_ep *ep, int *status)
2279 {
2280         struct xhci_ring *ep_ring;
2281         union xhci_trb *cur_trb;
2282         struct xhci_segment *cur_seg;
2283         u32 trb_comp_code;
2284
2285         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2286         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2287
2288         switch (trb_comp_code) {
2289         case COMP_SUCCESS:
2290                 /* Double check that the HW transferred everything. */
2291                 if (event_trb != td->last_trb ||
2292                     EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2293                         xhci_warn(xhci, "WARN Successful completion "
2294                                         "on short TX\n");
2295                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2296                                 *status = -EREMOTEIO;
2297                         else
2298                                 *status = 0;
2299                         if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2300                                 trb_comp_code = COMP_SHORT_TX;
2301                 } else {
2302                         *status = 0;
2303                 }
2304                 break;
2305         case COMP_SHORT_TX:
2306                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2307                         *status = -EREMOTEIO;
2308                 else
2309                         *status = 0;
2310                 break;
2311         default:
2312                 /* Others already handled above */
2313                 break;
2314         }
2315         if (trb_comp_code == COMP_SHORT_TX)
2316                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2317                                 "%d bytes untransferred\n",
2318                                 td->urb->ep->desc.bEndpointAddress,
2319                                 td->urb->transfer_buffer_length,
2320                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2321         /* Fast path - was this the last TRB in the TD for this URB? */
2322         if (event_trb == td->last_trb) {
2323                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2324                         td->urb->actual_length =
2325                                 td->urb->transfer_buffer_length -
2326                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2327                         if (td->urb->transfer_buffer_length <
2328                                         td->urb->actual_length) {
2329                                 xhci_warn(xhci, "HC gave bad length "
2330                                                 "of %d bytes left\n",
2331                                           EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2332                                 td->urb->actual_length = 0;
2333                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2334                                         *status = -EREMOTEIO;
2335                                 else
2336                                         *status = 0;
2337                         }
2338                         /* Don't overwrite a previously set error code */
2339                         if (*status == -EINPROGRESS) {
2340                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2341                                         *status = -EREMOTEIO;
2342                                 else
2343                                         *status = 0;
2344                         }
2345                 } else {
2346                         td->urb->actual_length =
2347                                 td->urb->transfer_buffer_length;
2348                         /* Ignore a short packet completion if the
2349                          * untransferred length was zero.
2350                          */
2351                         if (*status == -EREMOTEIO)
2352                                 *status = 0;
2353                 }
2354         } else {
2355                 /* Slow path - walk the list, starting from the dequeue
2356                  * pointer, to get the actual length transferred.
2357                  */
2358                 td->urb->actual_length = 0;
2359                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2360                                 cur_trb != event_trb;
2361                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2362                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2363                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2364                                 td->urb->actual_length +=
2365                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2366                 }
2367                 /* If the ring didn't stop on a Link or No-op TRB, add
2368                  * in the actual bytes transferred from the Normal TRB
2369                  */
2370                 if (trb_comp_code != COMP_STOP_INVAL)
2371                         td->urb->actual_length +=
2372                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2373                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2374         }
2375
2376         return finish_td(xhci, td, event_trb, event, ep, status, false);
2377 }
2378
2379 /*
2380  * If this function returns an error condition, it means it got a Transfer
2381  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2382  * At this point, the host controller is probably hosed and should be reset.
2383  */
2384 static int handle_tx_event(struct xhci_hcd *xhci,
2385                 struct xhci_transfer_event *event)
2386         __releases(&xhci->lock)
2387         __acquires(&xhci->lock)
2388 {
2389         struct xhci_virt_device *xdev;
2390         struct xhci_virt_ep *ep;
2391         struct xhci_ring *ep_ring;
2392         unsigned int slot_id;
2393         int ep_index;
2394         struct xhci_td *td = NULL;
2395         dma_addr_t event_dma;
2396         struct xhci_segment *event_seg;
2397         union xhci_trb *event_trb;
2398         struct urb *urb = NULL;
2399         int status = -EINPROGRESS;
2400         struct urb_priv *urb_priv;
2401         struct xhci_ep_ctx *ep_ctx;
2402         struct list_head *tmp;
2403         u32 trb_comp_code;
2404         int ret = 0;
2405         int td_num = 0;
2406
2407         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2408         xdev = xhci->devs[slot_id];
2409         if (!xdev) {
2410                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2411                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2412                          (unsigned long long) xhci_trb_virt_to_dma(
2413                                  xhci->event_ring->deq_seg,
2414                                  xhci->event_ring->dequeue),
2415                          lower_32_bits(le64_to_cpu(event->buffer)),
2416                          upper_32_bits(le64_to_cpu(event->buffer)),
2417                          le32_to_cpu(event->transfer_len),
2418                          le32_to_cpu(event->flags));
2419                 xhci_dbg(xhci, "Event ring:\n");
2420                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2421                 return -ENODEV;
2422         }
2423
2424         /* Endpoint ID is 1 based, our index is zero based */
2425         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2426         ep = &xdev->eps[ep_index];
2427         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2428         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2429         if (!ep_ring ||
2430             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2431             EP_STATE_DISABLED) {
2432                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2433                                 "or incorrect stream ring\n");
2434                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2435                          (unsigned long long) xhci_trb_virt_to_dma(
2436                                  xhci->event_ring->deq_seg,
2437                                  xhci->event_ring->dequeue),
2438                          lower_32_bits(le64_to_cpu(event->buffer)),
2439                          upper_32_bits(le64_to_cpu(event->buffer)),
2440                          le32_to_cpu(event->transfer_len),
2441                          le32_to_cpu(event->flags));
2442                 xhci_dbg(xhci, "Event ring:\n");
2443                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2444                 return -ENODEV;
2445         }
2446
2447         /* Count current td numbers if ep->skip is set */
2448         if (ep->skip) {
2449                 list_for_each(tmp, &ep_ring->td_list)
2450                         td_num++;
2451         }
2452
2453         event_dma = le64_to_cpu(event->buffer);
2454         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2455         /* Look for common error cases */
2456         switch (trb_comp_code) {
2457         /* Skip codes that require special handling depending on
2458          * transfer type
2459          */
2460         case COMP_SUCCESS:
2461                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2462                         break;
2463                 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2464                         trb_comp_code = COMP_SHORT_TX;
2465                 else
2466                         xhci_warn_ratelimited(xhci,
2467                                         "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2468         case COMP_SHORT_TX:
2469                 break;
2470         case COMP_STOP:
2471                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2472                 break;
2473         case COMP_STOP_INVAL:
2474                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2475                 break;
2476         case COMP_STALL:
2477                 xhci_dbg(xhci, "Stalled endpoint\n");
2478                 ep->ep_state |= EP_HALTED;
2479                 status = -EPIPE;
2480                 break;
2481         case COMP_TRB_ERR:
2482                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2483                 status = -EILSEQ;
2484                 break;
2485         case COMP_SPLIT_ERR:
2486         case COMP_TX_ERR:
2487                 xhci_dbg(xhci, "Transfer error on endpoint\n");
2488                 status = -EPROTO;
2489                 break;
2490         case COMP_BABBLE:
2491                 xhci_dbg(xhci, "Babble error on endpoint\n");
2492                 status = -EOVERFLOW;
2493                 break;
2494         case COMP_DB_ERR:
2495                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2496                 status = -ENOSR;
2497                 break;
2498         case COMP_BW_OVER:
2499                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2500                 break;
2501         case COMP_BUFF_OVER:
2502                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2503                 break;
2504         case COMP_UNDERRUN:
2505                 /*
2506                  * When the Isoch ring is empty, the xHC will generate
2507                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2508                  * Underrun Event for OUT Isoch endpoint.
2509                  */
2510                 xhci_dbg(xhci, "underrun event on endpoint\n");
2511                 if (!list_empty(&ep_ring->td_list))
2512                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2513                                         "still with TDs queued?\n",
2514                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2515                                  ep_index);
2516                 goto cleanup;
2517         case COMP_OVERRUN:
2518                 xhci_dbg(xhci, "overrun event on endpoint\n");
2519                 if (!list_empty(&ep_ring->td_list))
2520                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2521                                         "still with TDs queued?\n",
2522                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2523                                  ep_index);
2524                 goto cleanup;
2525         case COMP_DEV_ERR:
2526                 xhci_warn(xhci, "WARN: detect an incompatible device");
2527                 status = -EPROTO;
2528                 break;
2529         case COMP_MISSED_INT:
2530                 /*
2531                  * When encounter missed service error, one or more isoc tds
2532                  * may be missed by xHC.
2533                  * Set skip flag of the ep_ring; Complete the missed tds as
2534                  * short transfer when process the ep_ring next time.
2535                  */
2536                 ep->skip = true;
2537                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2538                 goto cleanup;
2539         default:
2540                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2541                         status = 0;
2542                         break;
2543                 }
2544                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2545                                 "busted\n");
2546                 goto cleanup;
2547         }
2548
2549         do {
2550                 /* This TRB should be in the TD at the head of this ring's
2551                  * TD list.
2552                  */
2553                 if (list_empty(&ep_ring->td_list)) {
2554                         /*
2555                          * A stopped endpoint may generate an extra completion
2556                          * event if the device was suspended.  Don't print
2557                          * warnings.
2558                          */
2559                         if (!(trb_comp_code == COMP_STOP ||
2560                                                 trb_comp_code == COMP_STOP_INVAL)) {
2561                                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2562                                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2563                                                 ep_index);
2564                                 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2565                                                 (le32_to_cpu(event->flags) &
2566                                                  TRB_TYPE_BITMASK)>>10);
2567                                 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2568                         }
2569                         if (ep->skip) {
2570                                 ep->skip = false;
2571                                 xhci_dbg(xhci, "td_list is empty while skip "
2572                                                 "flag set. Clear skip flag.\n");
2573                         }
2574                         ret = 0;
2575                         goto cleanup;
2576                 }
2577
2578                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2579                 if (ep->skip && td_num == 0) {
2580                         ep->skip = false;
2581                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2582                                                 "Clear skip flag.\n");
2583                         ret = 0;
2584                         goto cleanup;
2585                 }
2586
2587                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2588                 if (ep->skip)
2589                         td_num--;
2590
2591                 /* Is this a TRB in the currently executing TD? */
2592                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2593                                 td->last_trb, event_dma);
2594
2595                 /*
2596                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2597                  * is not in the current TD pointed by ep_ring->dequeue because
2598                  * that the hardware dequeue pointer still at the previous TRB
2599                  * of the current TD. The previous TRB maybe a Link TD or the
2600                  * last TRB of the previous TD. The command completion handle
2601                  * will take care the rest.
2602                  */
2603                 if (!event_seg && (trb_comp_code == COMP_STOP ||
2604                                    trb_comp_code == COMP_STOP_INVAL)) {
2605                         ret = 0;
2606                         goto cleanup;
2607                 }
2608
2609                 if (!event_seg) {
2610                         if (!ep->skip ||
2611                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2612                                 /* Some host controllers give a spurious
2613                                  * successful event after a short transfer.
2614                                  * Ignore it.
2615                                  */
2616                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2617                                                 ep_ring->last_td_was_short) {
2618                                         ep_ring->last_td_was_short = false;
2619                                         ret = 0;
2620                                         goto cleanup;
2621                                 }
2622                                 /* HC is busted, give up! */
2623                                 xhci_err(xhci,
2624                                         "ERROR Transfer event TRB DMA ptr not "
2625                                         "part of current TD\n");
2626                                 return -ESHUTDOWN;
2627                         }
2628
2629                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2630                         goto cleanup;
2631                 }
2632                 if (trb_comp_code == COMP_SHORT_TX)
2633                         ep_ring->last_td_was_short = true;
2634                 else
2635                         ep_ring->last_td_was_short = false;
2636
2637                 if (ep->skip) {
2638                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2639                         ep->skip = false;
2640                 }
2641
2642                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2643                                                 sizeof(*event_trb)];
2644                 /*
2645                  * No-op TRB should not trigger interrupts.
2646                  * If event_trb is a no-op TRB, it means the
2647                  * corresponding TD has been cancelled. Just ignore
2648                  * the TD.
2649                  */
2650                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2651                         xhci_dbg(xhci,
2652                                  "event_trb is a no-op TRB. Skip it\n");
2653                         goto cleanup;
2654                 }
2655
2656                 /* Now update the urb's actual_length and give back to
2657                  * the core
2658                  */
2659                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2660                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2661                                                  &status);
2662                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2663                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2664                                                  &status);
2665                 else
2666                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2667                                                  ep, &status);
2668
2669 cleanup:
2670                 /*
2671                  * Do not update event ring dequeue pointer if ep->skip is set.
2672                  * Will roll back to continue process missed tds.
2673                  */
2674                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2675                         inc_deq(xhci, xhci->event_ring);
2676                 }
2677
2678                 if (ret) {
2679                         urb = td->urb;
2680                         urb_priv = urb->hcpriv;
2681
2682                         xhci_urb_free_priv(xhci, urb_priv);
2683
2684                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2685                         if ((urb->actual_length != urb->transfer_buffer_length &&
2686                                                 (urb->transfer_flags &
2687                                                  URB_SHORT_NOT_OK)) ||
2688                                         (status != 0 &&
2689                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2690                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2691                                                 "expected = %d, status = %d\n",
2692                                                 urb, urb->actual_length,
2693                                                 urb->transfer_buffer_length,
2694                                                 status);
2695                         spin_unlock(&xhci->lock);
2696                         /* EHCI, UHCI, and OHCI always unconditionally set the
2697                          * urb->status of an isochronous endpoint to 0.
2698                          */
2699                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2700                                 status = 0;
2701                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2702                         spin_lock(&xhci->lock);
2703                 }
2704
2705         /*
2706          * If ep->skip is set, it means there are missed tds on the
2707          * endpoint ring need to take care of.
2708          * Process them as short transfer until reach the td pointed by
2709          * the event.
2710          */
2711         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2712
2713         return 0;
2714 }
2715
2716 /*
2717  * This function handles all OS-owned events on the event ring.  It may drop
2718  * xhci->lock between event processing (e.g. to pass up port status changes).
2719  * Returns >0 for "possibly more events to process" (caller should call again),
2720  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2721  */
2722 static int xhci_handle_event(struct xhci_hcd *xhci)
2723 {
2724         union xhci_trb *event;
2725         int update_ptrs = 1;
2726         int ret;
2727
2728         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2729                 xhci->error_bitmask |= 1 << 1;
2730                 return 0;
2731         }
2732
2733         event = xhci->event_ring->dequeue;
2734         /* Does the HC or OS own the TRB? */
2735         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2736             xhci->event_ring->cycle_state) {
2737                 xhci->error_bitmask |= 1 << 2;
2738                 return 0;
2739         }
2740
2741         /*
2742          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2743          * speculative reads of the event's flags/data below.
2744          */
2745         rmb();
2746         /* FIXME: Handle more event types. */
2747         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2748         case TRB_TYPE(TRB_COMPLETION):
2749                 handle_cmd_completion(xhci, &event->event_cmd);
2750                 break;
2751         case TRB_TYPE(TRB_PORT_STATUS):
2752                 handle_port_status(xhci, event);
2753                 update_ptrs = 0;
2754                 break;
2755         case TRB_TYPE(TRB_TRANSFER):
2756                 ret = handle_tx_event(xhci, &event->trans_event);
2757                 if (ret < 0)
2758                         xhci->error_bitmask |= 1 << 9;
2759                 else
2760                         update_ptrs = 0;
2761                 break;
2762         case TRB_TYPE(TRB_DEV_NOTE):
2763                 handle_device_notification(xhci, event);
2764                 break;
2765         default:
2766                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2767                     TRB_TYPE(48))
2768                         handle_vendor_event(xhci, event);
2769                 else
2770                         xhci->error_bitmask |= 1 << 3;
2771         }
2772         /* Any of the above functions may drop and re-acquire the lock, so check
2773          * to make sure a watchdog timer didn't mark the host as non-responsive.
2774          */
2775         if (xhci->xhc_state & XHCI_STATE_DYING) {
2776                 xhci_dbg(xhci, "xHCI host dying, returning from "
2777                                 "event handler.\n");
2778                 return 0;
2779         }
2780
2781         if (update_ptrs)
2782                 /* Update SW event ring dequeue pointer */
2783                 inc_deq(xhci, xhci->event_ring);
2784
2785         /* Are there more items on the event ring?  Caller will call us again to
2786          * check.
2787          */
2788         return 1;
2789 }
2790
2791 /*
2792  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2793  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2794  * indicators of an event TRB error, but we check the status *first* to be safe.
2795  */
2796 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2797 {
2798         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2799         u32 status;
2800         u64 temp_64;
2801         union xhci_trb *event_ring_deq;
2802         dma_addr_t deq;
2803
2804         spin_lock(&xhci->lock);
2805         /* Check if the xHC generated the interrupt, or the irq is shared */
2806         status = readl(&xhci->op_regs->status);
2807         if (status == 0xffffffff)
2808                 goto hw_died;
2809
2810         if (!(status & STS_EINT)) {
2811                 spin_unlock(&xhci->lock);
2812                 return IRQ_NONE;
2813         }
2814         if (status & STS_FATAL) {
2815                 xhci_warn(xhci, "WARNING: Host System Error\n");
2816                 xhci_halt(xhci);
2817 hw_died:
2818                 spin_unlock(&xhci->lock);
2819                 return -ESHUTDOWN;
2820         }
2821
2822         /*
2823          * Clear the op reg interrupt status first,
2824          * so we can receive interrupts from other MSI-X interrupters.
2825          * Write 1 to clear the interrupt status.
2826          */
2827         status |= STS_EINT;
2828         writel(status, &xhci->op_regs->status);
2829         /* FIXME when MSI-X is supported and there are multiple vectors */
2830         /* Clear the MSI-X event interrupt status */
2831
2832         if (hcd->irq) {
2833                 u32 irq_pending;
2834                 /* Acknowledge the PCI interrupt */
2835                 irq_pending = readl(&xhci->ir_set->irq_pending);
2836                 irq_pending |= IMAN_IP;
2837                 writel(irq_pending, &xhci->ir_set->irq_pending);
2838         }
2839
2840         if (xhci->xhc_state & XHCI_STATE_DYING) {
2841                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2842                                 "Shouldn't IRQs be disabled?\n");
2843                 /* Clear the event handler busy flag (RW1C);
2844                  * the event ring should be empty.
2845                  */
2846                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2847                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2848                                 &xhci->ir_set->erst_dequeue);
2849                 spin_unlock(&xhci->lock);
2850
2851                 return IRQ_HANDLED;
2852         }
2853
2854         event_ring_deq = xhci->event_ring->dequeue;
2855         /* FIXME this should be a delayed service routine
2856          * that clears the EHB.
2857          */
2858         while (xhci_handle_event(xhci) > 0) {}
2859
2860         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2861         /* If necessary, update the HW's version of the event ring deq ptr. */
2862         if (event_ring_deq != xhci->event_ring->dequeue) {
2863                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2864                                 xhci->event_ring->dequeue);
2865                 if (deq == 0)
2866                         xhci_warn(xhci, "WARN something wrong with SW event "
2867                                         "ring dequeue ptr.\n");
2868                 /* Update HC event ring dequeue pointer */
2869                 temp_64 &= ERST_PTR_MASK;
2870                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2871         }
2872
2873         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2874         temp_64 |= ERST_EHB;
2875         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2876
2877         spin_unlock(&xhci->lock);
2878
2879         return IRQ_HANDLED;
2880 }
2881
2882 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2883 {
2884         return xhci_irq(hcd);
2885 }
2886
2887 /****           Endpoint Ring Operations        ****/
2888
2889 /*
2890  * Generic function for queueing a TRB on a ring.
2891  * The caller must have checked to make sure there's room on the ring.
2892  *
2893  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2894  *                      prepare_transfer()?
2895  */
2896 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2897                 bool more_trbs_coming,
2898                 u32 field1, u32 field2, u32 field3, u32 field4)
2899 {
2900         struct xhci_generic_trb *trb;
2901
2902         trb = &ring->enqueue->generic;
2903         trb->field[0] = cpu_to_le32(field1);
2904         trb->field[1] = cpu_to_le32(field2);
2905         trb->field[2] = cpu_to_le32(field3);
2906         trb->field[3] = cpu_to_le32(field4);
2907         inc_enq(xhci, ring, more_trbs_coming);
2908 }
2909
2910 /*
2911  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2912  * FIXME allocate segments if the ring is full.
2913  */
2914 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2915                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2916 {
2917         unsigned int num_trbs_needed;
2918
2919         /* Make sure the endpoint has been added to xHC schedule */
2920         switch (ep_state) {
2921         case EP_STATE_DISABLED:
2922                 /*
2923                  * USB core changed config/interfaces without notifying us,
2924                  * or hardware is reporting the wrong state.
2925                  */
2926                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2927                 return -ENOENT;
2928         case EP_STATE_ERROR:
2929                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2930                 /* FIXME event handling code for error needs to clear it */
2931                 /* XXX not sure if this should be -ENOENT or not */
2932                 return -EINVAL;
2933         case EP_STATE_HALTED:
2934                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2935         case EP_STATE_STOPPED:
2936         case EP_STATE_RUNNING:
2937                 break;
2938         default:
2939                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2940                 /*
2941                  * FIXME issue Configure Endpoint command to try to get the HC
2942                  * back into a known state.
2943                  */
2944                 return -EINVAL;
2945         }
2946
2947         while (1) {
2948                 if (room_on_ring(xhci, ep_ring, num_trbs))
2949                         break;
2950
2951                 if (ep_ring == xhci->cmd_ring) {
2952                         xhci_err(xhci, "Do not support expand command ring\n");
2953                         return -ENOMEM;
2954                 }
2955
2956                 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2957                                 "ERROR no room on ep ring, try ring expansion");
2958                 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2959                 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2960                                         mem_flags)) {
2961                         xhci_err(xhci, "Ring expansion failed\n");
2962                         return -ENOMEM;
2963                 }
2964         }
2965
2966         if (enqueue_is_link_trb(ep_ring)) {
2967                 struct xhci_ring *ring = ep_ring;
2968                 union xhci_trb *next;
2969
2970                 next = ring->enqueue;
2971
2972                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2973                         /* If we're not dealing with 0.95 hardware or isoc rings
2974                          * on AMD 0.96 host, clear the chain bit.
2975                          */
2976                         if (!xhci_link_trb_quirk(xhci) &&
2977                                         !(ring->type == TYPE_ISOC &&
2978                                          (xhci->quirks & XHCI_AMD_0x96_HOST)))
2979                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2980                         else
2981                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
2982
2983                         wmb();
2984                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
2985
2986                         /* Toggle the cycle bit after the last ring segment. */
2987                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2988                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2989                         }
2990                         ring->enq_seg = ring->enq_seg->next;
2991                         ring->enqueue = ring->enq_seg->trbs;
2992                         next = ring->enqueue;
2993                 }
2994         }
2995
2996         return 0;
2997 }
2998
2999 static int prepare_transfer(struct xhci_hcd *xhci,
3000                 struct xhci_virt_device *xdev,
3001                 unsigned int ep_index,
3002                 unsigned int stream_id,
3003                 unsigned int num_trbs,
3004                 struct urb *urb,
3005                 unsigned int td_index,
3006                 gfp_t mem_flags)
3007 {
3008         int ret;
3009         struct urb_priv *urb_priv;
3010         struct xhci_td  *td;
3011         struct xhci_ring *ep_ring;
3012         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3013
3014         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
3015         if (!ep_ring) {
3016                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3017                                 stream_id);
3018                 return -EINVAL;
3019         }
3020
3021         ret = prepare_ring(xhci, ep_ring,
3022                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3023                            num_trbs, mem_flags);
3024         if (ret)
3025                 return ret;
3026
3027         urb_priv = urb->hcpriv;
3028         td = urb_priv->td[td_index];
3029
3030         INIT_LIST_HEAD(&td->td_list);
3031         INIT_LIST_HEAD(&td->cancelled_td_list);
3032
3033         if (td_index == 0) {
3034                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3035                 if (unlikely(ret))
3036                         return ret;
3037         }
3038
3039         td->urb = urb;
3040         /* Add this TD to the tail of the endpoint ring's TD list */
3041         list_add_tail(&td->td_list, &ep_ring->td_list);
3042         td->start_seg = ep_ring->enq_seg;
3043         td->first_trb = ep_ring->enqueue;
3044
3045         urb_priv->td[td_index] = td;
3046
3047         return 0;
3048 }
3049
3050 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
3051 {
3052         int num_sgs, num_trbs, running_total, temp, i;
3053         struct scatterlist *sg;
3054
3055         sg = NULL;
3056         num_sgs = urb->num_mapped_sgs;
3057         temp = urb->transfer_buffer_length;
3058
3059         num_trbs = 0;
3060         for_each_sg(urb->sg, sg, num_sgs, i) {
3061                 unsigned int len = sg_dma_len(sg);
3062
3063                 /* Scatter gather list entries may cross 64KB boundaries */
3064                 running_total = TRB_MAX_BUFF_SIZE -
3065                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
3066                 running_total &= TRB_MAX_BUFF_SIZE - 1;
3067                 if (running_total != 0)
3068                         num_trbs++;
3069
3070                 /* How many more 64KB chunks to transfer, how many more TRBs? */
3071                 while (running_total < sg_dma_len(sg) && running_total < temp) {
3072                         num_trbs++;
3073                         running_total += TRB_MAX_BUFF_SIZE;
3074                 }
3075                 len = min_t(int, len, temp);
3076                 temp -= len;
3077                 if (temp == 0)
3078                         break;
3079         }
3080         return num_trbs;
3081 }
3082
3083 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
3084 {
3085         if (num_trbs != 0)
3086                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
3087                                 "TRBs, %d left\n", __func__,
3088                                 urb->ep->desc.bEndpointAddress, num_trbs);
3089         if (running_total != urb->transfer_buffer_length)
3090                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3091                                 "queued %#x (%d), asked for %#x (%d)\n",
3092                                 __func__,
3093                                 urb->ep->desc.bEndpointAddress,
3094                                 running_total, running_total,
3095                                 urb->transfer_buffer_length,
3096                                 urb->transfer_buffer_length);
3097 }
3098
3099 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3100                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3101                 struct xhci_generic_trb *start_trb)
3102 {
3103         /*
3104          * Pass all the TRBs to the hardware at once and make sure this write
3105          * isn't reordered.
3106          */
3107         wmb();
3108         if (start_cycle)
3109                 start_trb->field[3] |= cpu_to_le32(start_cycle);
3110         else
3111                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3112         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3113 }
3114
3115 /*
3116  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
3117  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
3118  * (comprised of sg list entries) can take several service intervals to
3119  * transmit.
3120  */
3121 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3122                 struct urb *urb, int slot_id, unsigned int ep_index)
3123 {
3124         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3125                         xhci->devs[slot_id]->out_ctx, ep_index);
3126         int xhci_interval;
3127         int ep_interval;
3128
3129         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3130         ep_interval = urb->interval;
3131         /* Convert to microframes */
3132         if (urb->dev->speed == USB_SPEED_LOW ||
3133                         urb->dev->speed == USB_SPEED_FULL)
3134                 ep_interval *= 8;
3135         /* FIXME change this to a warning and a suggestion to use the new API
3136          * to set the polling interval (once the API is added).
3137          */
3138         if (xhci_interval != ep_interval) {
3139                 dev_dbg_ratelimited(&urb->dev->dev,
3140                                 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3141                                 ep_interval, ep_interval == 1 ? "" : "s",
3142                                 xhci_interval, xhci_interval == 1 ? "" : "s");
3143                 urb->interval = xhci_interval;
3144                 /* Convert back to frames for LS/FS devices */
3145                 if (urb->dev->speed == USB_SPEED_LOW ||
3146                                 urb->dev->speed == USB_SPEED_FULL)
3147                         urb->interval /= 8;
3148         }
3149         return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3150 }
3151
3152 /*
3153  * The TD size is the number of bytes remaining in the TD (including this TRB),
3154  * right shifted by 10.
3155  * It must fit in bits 21:17, so it can't be bigger than 31.
3156  */
3157 static u32 xhci_td_remainder(unsigned int remainder)
3158 {
3159         u32 max = (1 << (21 - 17 + 1)) - 1;
3160
3161         if ((remainder >> 10) >= max)
3162                 return max << 17;
3163         else
3164                 return (remainder >> 10) << 17;
3165 }
3166
3167 /*
3168  * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3169  * packets remaining in the TD (*not* including this TRB).
3170  *
3171  * Total TD packet count = total_packet_count =
3172  *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3173  *
3174  * Packets transferred up to and including this TRB = packets_transferred =
3175  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3176  *
3177  * TD size = total_packet_count - packets_transferred
3178  *
3179  * It must fit in bits 21:17, so it can't be bigger than 31.
3180  * The last TRB in a TD must have the TD size set to zero.
3181  */
3182 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3183                 unsigned int total_packet_count, struct urb *urb,
3184                 unsigned int num_trbs_left)
3185 {
3186         int packets_transferred;
3187
3188         /* One TRB with a zero-length data packet. */
3189         if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3190                 return 0;
3191
3192         /* All the TRB queueing functions don't count the current TRB in
3193          * running_total.
3194          */
3195         packets_transferred = (running_total + trb_buff_len) /
3196                 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3197
3198         if ((total_packet_count - packets_transferred) > 31)
3199                 return 31 << 17;
3200         return (total_packet_count - packets_transferred) << 17;
3201 }
3202
3203 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3204                 struct urb *urb, int slot_id, unsigned int ep_index)
3205 {
3206         struct xhci_ring *ep_ring;
3207         unsigned int num_trbs;
3208         struct urb_priv *urb_priv;
3209         struct xhci_td *td;
3210         struct scatterlist *sg;
3211         int num_sgs;
3212         int trb_buff_len, this_sg_len, running_total;
3213         unsigned int total_packet_count;
3214         bool first_trb;
3215         u64 addr;
3216         bool more_trbs_coming;
3217
3218         struct xhci_generic_trb *start_trb;
3219         int start_cycle;
3220
3221         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3222         if (!ep_ring)
3223                 return -EINVAL;
3224
3225         num_trbs = count_sg_trbs_needed(xhci, urb);
3226         num_sgs = urb->num_mapped_sgs;
3227         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3228                         usb_endpoint_maxp(&urb->ep->desc));
3229
3230         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3231                         ep_index, urb->stream_id,
3232                         num_trbs, urb, 0, mem_flags);
3233         if (trb_buff_len < 0)
3234                 return trb_buff_len;
3235
3236         urb_priv = urb->hcpriv;
3237         td = urb_priv->td[0];
3238
3239         /*
3240          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3241          * until we've finished creating all the other TRBs.  The ring's cycle
3242          * state may change as we enqueue the other TRBs, so save it too.
3243          */
3244         start_trb = &ep_ring->enqueue->generic;
3245         start_cycle = ep_ring->cycle_state;
3246
3247         running_total = 0;
3248         /*
3249          * How much data is in the first TRB?
3250          *
3251          * There are three forces at work for TRB buffer pointers and lengths:
3252          * 1. We don't want to walk off the end of this sg-list entry buffer.
3253          * 2. The transfer length that the driver requested may be smaller than
3254          *    the amount of memory allocated for this scatter-gather list.
3255          * 3. TRBs buffers can't cross 64KB boundaries.
3256          */
3257         sg = urb->sg;
3258         addr = (u64) sg_dma_address(sg);
3259         this_sg_len = sg_dma_len(sg);
3260         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3261         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3262         if (trb_buff_len > urb->transfer_buffer_length)
3263                 trb_buff_len = urb->transfer_buffer_length;
3264
3265         first_trb = true;
3266         /* Queue the first TRB, even if it's zero-length */
3267         do {
3268                 u32 field = 0;
3269                 u32 length_field = 0;
3270                 u32 remainder = 0;
3271
3272                 /* Don't change the cycle bit of the first TRB until later */
3273                 if (first_trb) {
3274                         first_trb = false;
3275                         if (start_cycle == 0)
3276                                 field |= 0x1;
3277                 } else
3278                         field |= ep_ring->cycle_state;
3279
3280                 /* Chain all the TRBs together; clear the chain bit in the last
3281                  * TRB to indicate it's the last TRB in the chain.
3282                  */
3283                 if (num_trbs > 1) {
3284                         field |= TRB_CHAIN;
3285                 } else {
3286                         /* FIXME - add check for ZERO_PACKET flag before this */
3287                         td->last_trb = ep_ring->enqueue;
3288                         field |= TRB_IOC;
3289                 }
3290
3291                 /* Only set interrupt on short packet for IN endpoints */
3292                 if (usb_urb_dir_in(urb))
3293                         field |= TRB_ISP;
3294
3295                 if (TRB_MAX_BUFF_SIZE -
3296                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3297                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3298                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3299                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3300                                         (unsigned int) addr + trb_buff_len);
3301                 }
3302
3303                 /* Set the TRB length, TD size, and interrupter fields. */
3304                 if (xhci->hci_version < 0x100) {
3305                         remainder = xhci_td_remainder(
3306                                         urb->transfer_buffer_length -
3307                                         running_total);
3308                 } else {
3309                         remainder = xhci_v1_0_td_remainder(running_total,
3310                                         trb_buff_len, total_packet_count, urb,
3311                                         num_trbs - 1);
3312                 }
3313                 length_field = TRB_LEN(trb_buff_len) |
3314                         remainder |
3315                         TRB_INTR_TARGET(0);
3316
3317                 if (num_trbs > 1)
3318                         more_trbs_coming = true;
3319                 else
3320                         more_trbs_coming = false;
3321                 queue_trb(xhci, ep_ring, more_trbs_coming,
3322                                 lower_32_bits(addr),
3323                                 upper_32_bits(addr),
3324                                 length_field,
3325                                 field | TRB_TYPE(TRB_NORMAL));
3326                 --num_trbs;
3327                 running_total += trb_buff_len;
3328
3329                 /* Calculate length for next transfer --
3330                  * Are we done queueing all the TRBs for this sg entry?
3331                  */
3332                 this_sg_len -= trb_buff_len;
3333                 if (this_sg_len == 0) {
3334                         --num_sgs;
3335                         if (num_sgs == 0)
3336                                 break;
3337                         sg = sg_next(sg);
3338                         addr = (u64) sg_dma_address(sg);
3339                         this_sg_len = sg_dma_len(sg);
3340                 } else {
3341                         addr += trb_buff_len;
3342                 }
3343
3344                 trb_buff_len = TRB_MAX_BUFF_SIZE -
3345                         (addr & (TRB_MAX_BUFF_SIZE - 1));
3346                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3347                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3348                         trb_buff_len =
3349                                 urb->transfer_buffer_length - running_total;
3350         } while (running_total < urb->transfer_buffer_length);
3351
3352         check_trb_math(urb, num_trbs, running_total);
3353         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3354                         start_cycle, start_trb);
3355         return 0;
3356 }
3357
3358 /* This is very similar to what ehci-q.c qtd_fill() does */
3359 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3360                 struct urb *urb, int slot_id, unsigned int ep_index)
3361 {
3362         struct xhci_ring *ep_ring;
3363         struct urb_priv *urb_priv;
3364         struct xhci_td *td;
3365         int num_trbs;
3366         struct xhci_generic_trb *start_trb;
3367         bool first_trb;
3368         bool more_trbs_coming;
3369         int start_cycle;
3370         u32 field, length_field;
3371
3372         int running_total, trb_buff_len, ret;
3373         unsigned int total_packet_count;
3374         u64 addr;
3375
3376         if (urb->num_sgs)
3377                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3378
3379         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3380         if (!ep_ring)
3381                 return -EINVAL;
3382
3383         num_trbs = 0;
3384         /* How much data is (potentially) left before the 64KB boundary? */
3385         running_total = TRB_MAX_BUFF_SIZE -
3386                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3387         running_total &= TRB_MAX_BUFF_SIZE - 1;
3388
3389         /* If there's some data on this 64KB chunk, or we have to send a
3390          * zero-length transfer, we need at least one TRB
3391          */
3392         if (running_total != 0 || urb->transfer_buffer_length == 0)
3393                 num_trbs++;
3394         /* How many more 64KB chunks to transfer, how many more TRBs? */
3395         while (running_total < urb->transfer_buffer_length) {
3396                 num_trbs++;
3397                 running_total += TRB_MAX_BUFF_SIZE;
3398         }
3399         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3400
3401         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3402                         ep_index, urb->stream_id,
3403                         num_trbs, urb, 0, mem_flags);
3404         if (ret < 0)
3405                 return ret;
3406
3407         urb_priv = urb->hcpriv;
3408         td = urb_priv->td[0];
3409
3410         /*
3411          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3412          * until we've finished creating all the other TRBs.  The ring's cycle
3413          * state may change as we enqueue the other TRBs, so save it too.
3414          */
3415         start_trb = &ep_ring->enqueue->generic;
3416         start_cycle = ep_ring->cycle_state;
3417
3418         running_total = 0;
3419         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3420                         usb_endpoint_maxp(&urb->ep->desc));
3421         /* How much data is in the first TRB? */
3422         addr = (u64) urb->transfer_dma;
3423         trb_buff_len = TRB_MAX_BUFF_SIZE -
3424                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3425         if (trb_buff_len > urb->transfer_buffer_length)
3426                 trb_buff_len = urb->transfer_buffer_length;
3427
3428         first_trb = true;
3429
3430         /* Queue the first TRB, even if it's zero-length */
3431         do {
3432                 u32 remainder = 0;
3433                 field = 0;
3434
3435                 /* Don't change the cycle bit of the first TRB until later */
3436                 if (first_trb) {
3437                         first_trb = false;
3438                         if (start_cycle == 0)
3439                                 field |= 0x1;
3440                 } else
3441                         field |= ep_ring->cycle_state;
3442
3443                 /* Chain all the TRBs together; clear the chain bit in the last
3444                  * TRB to indicate it's the last TRB in the chain.
3445                  */
3446                 if (num_trbs > 1) {
3447                         field |= TRB_CHAIN;
3448                 } else {
3449                         /* FIXME - add check for ZERO_PACKET flag before this */
3450                         td->last_trb = ep_ring->enqueue;
3451                         field |= TRB_IOC;
3452                 }
3453
3454                 /* Only set interrupt on short packet for IN endpoints */
3455                 if (usb_urb_dir_in(urb))
3456                         field |= TRB_ISP;
3457
3458                 /* Set the TRB length, TD size, and interrupter fields. */
3459                 if (xhci->hci_version < 0x100) {
3460                         remainder = xhci_td_remainder(
3461                                         urb->transfer_buffer_length -
3462                                         running_total);
3463                 } else {
3464                         remainder = xhci_v1_0_td_remainder(running_total,
3465                                         trb_buff_len, total_packet_count, urb,
3466                                         num_trbs - 1);
3467                 }
3468                 length_field = TRB_LEN(trb_buff_len) |
3469                         remainder |
3470                         TRB_INTR_TARGET(0);
3471
3472                 if (num_trbs > 1)
3473                         more_trbs_coming = true;
3474                 else
3475                         more_trbs_coming = false;
3476                 queue_trb(xhci, ep_ring, more_trbs_coming,
3477                                 lower_32_bits(addr),
3478                                 upper_32_bits(addr),
3479                                 length_field,
3480                                 field | TRB_TYPE(TRB_NORMAL));
3481                 --num_trbs;
3482                 running_total += trb_buff_len;
3483
3484                 /* Calculate length for next transfer */
3485                 addr += trb_buff_len;
3486                 trb_buff_len = urb->transfer_buffer_length - running_total;
3487                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3488                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3489         } while (running_total < urb->transfer_buffer_length);
3490
3491         check_trb_math(urb, num_trbs, running_total);
3492         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3493                         start_cycle, start_trb);
3494         return 0;
3495 }
3496
3497 /* Caller must have locked xhci->lock */
3498 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3499                 struct urb *urb, int slot_id, unsigned int ep_index)
3500 {
3501         struct xhci_ring *ep_ring;
3502         int num_trbs;
3503         int ret;
3504         struct usb_ctrlrequest *setup;
3505         struct xhci_generic_trb *start_trb;
3506         int start_cycle;
3507         u32 field, length_field;
3508         struct urb_priv *urb_priv;
3509         struct xhci_td *td;
3510
3511         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3512         if (!ep_ring)
3513                 return -EINVAL;
3514
3515         /*
3516          * Need to copy setup packet into setup TRB, so we can't use the setup
3517          * DMA address.
3518          */
3519         if (!urb->setup_packet)
3520                 return -EINVAL;
3521
3522         /* 1 TRB for setup, 1 for status */
3523         num_trbs = 2;
3524         /*
3525          * Don't need to check if we need additional event data and normal TRBs,
3526          * since data in control transfers will never get bigger than 16MB
3527          * XXX: can we get a buffer that crosses 64KB boundaries?
3528          */
3529         if (urb->transfer_buffer_length > 0)
3530                 num_trbs++;
3531         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3532                         ep_index, urb->stream_id,
3533                         num_trbs, urb, 0, mem_flags);
3534         if (ret < 0)
3535                 return ret;
3536
3537         urb_priv = urb->hcpriv;
3538         td = urb_priv->td[0];
3539
3540         /*
3541          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3542          * until we've finished creating all the other TRBs.  The ring's cycle
3543          * state may change as we enqueue the other TRBs, so save it too.
3544          */
3545         start_trb = &ep_ring->enqueue->generic;
3546         start_cycle = ep_ring->cycle_state;
3547
3548         /* Queue setup TRB - see section 6.4.1.2.1 */
3549         /* FIXME better way to translate setup_packet into two u32 fields? */
3550         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3551         field = 0;
3552         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3553         if (start_cycle == 0)
3554                 field |= 0x1;
3555
3556         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3557         if (xhci->hci_version == 0x100) {
3558                 if (urb->transfer_buffer_length > 0) {
3559                         if (setup->bRequestType & USB_DIR_IN)
3560                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3561                         else
3562                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3563                 }
3564         }
3565
3566         queue_trb(xhci, ep_ring, true,
3567                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3568                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3569                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3570                   /* Immediate data in pointer */
3571                   field);
3572
3573         /* If there's data, queue data TRBs */
3574         /* Only set interrupt on short packet for IN endpoints */
3575         if (usb_urb_dir_in(urb))
3576                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3577         else
3578                 field = TRB_TYPE(TRB_DATA);
3579
3580         length_field = TRB_LEN(urb->transfer_buffer_length) |
3581                 xhci_td_remainder(urb->transfer_buffer_length) |
3582                 TRB_INTR_TARGET(0);
3583         if (urb->transfer_buffer_length > 0) {
3584                 if (setup->bRequestType & USB_DIR_IN)
3585                         field |= TRB_DIR_IN;
3586                 queue_trb(xhci, ep_ring, true,
3587                                 lower_32_bits(urb->transfer_dma),
3588                                 upper_32_bits(urb->transfer_dma),
3589                                 length_field,
3590                                 field | ep_ring->cycle_state);
3591         }
3592
3593         /* Save the DMA address of the last TRB in the TD */
3594         td->last_trb = ep_ring->enqueue;
3595
3596         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3597         /* If the device sent data, the status stage is an OUT transfer */
3598         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3599                 field = 0;
3600         else
3601                 field = TRB_DIR_IN;
3602         queue_trb(xhci, ep_ring, false,
3603                         0,
3604                         0,
3605                         TRB_INTR_TARGET(0),
3606                         /* Event on completion */
3607                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3608
3609         giveback_first_trb(xhci, slot_id, ep_index, 0,
3610                         start_cycle, start_trb);
3611         return 0;
3612 }
3613
3614 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3615                 struct urb *urb, int i)
3616 {
3617         int num_trbs = 0;
3618         u64 addr, td_len;
3619
3620         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3621         td_len = urb->iso_frame_desc[i].length;
3622
3623         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3624                         TRB_MAX_BUFF_SIZE);
3625         if (num_trbs == 0)
3626                 num_trbs++;
3627
3628         return num_trbs;
3629 }
3630
3631 /*
3632  * The transfer burst count field of the isochronous TRB defines the number of
3633  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3634  * devices can burst up to bMaxBurst number of packets per service interval.
3635  * This field is zero based, meaning a value of zero in the field means one
3636  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3637  * zero.  Only xHCI 1.0 host controllers support this field.
3638  */
3639 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3640                 struct usb_device *udev,
3641                 struct urb *urb, unsigned int total_packet_count)
3642 {
3643         unsigned int max_burst;
3644
3645         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3646                 return 0;
3647
3648         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3649         return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3650 }
3651
3652 /*
3653  * Returns the number of packets in the last "burst" of packets.  This field is
3654  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3655  * the last burst packet count is equal to the total number of packets in the
3656  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3657  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3658  * contain 1 to (bMaxBurst + 1) packets.
3659  */
3660 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3661                 struct usb_device *udev,
3662                 struct urb *urb, unsigned int total_packet_count)
3663 {
3664         unsigned int max_burst;
3665         unsigned int residue;
3666
3667         if (xhci->hci_version < 0x100)
3668                 return 0;
3669
3670         switch (udev->speed) {
3671         case USB_SPEED_SUPER:
3672                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3673                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3674                 residue = total_packet_count % (max_burst + 1);
3675                 /* If residue is zero, the last burst contains (max_burst + 1)
3676                  * number of packets, but the TLBPC field is zero-based.
3677                  */
3678                 if (residue == 0)
3679                         return max_burst;
3680                 return residue - 1;
3681         default:
3682                 if (total_packet_count == 0)
3683                         return 0;
3684                 return total_packet_count - 1;
3685         }
3686 }
3687
3688 /* This is for isoc transfer */
3689 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3690                 struct urb *urb, int slot_id, unsigned int ep_index)
3691 {
3692         struct xhci_ring *ep_ring;
3693         struct urb_priv *urb_priv;
3694         struct xhci_td *td;
3695         int num_tds, trbs_per_td;
3696         struct xhci_generic_trb *start_trb;
3697         bool first_trb;
3698         int start_cycle;
3699         u32 field, length_field;
3700         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3701         u64 start_addr, addr;
3702         int i, j;
3703         bool more_trbs_coming;
3704
3705         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3706
3707         num_tds = urb->number_of_packets;
3708         if (num_tds < 1) {
3709                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3710                 return -EINVAL;
3711         }
3712
3713         start_addr = (u64) urb->transfer_dma;
3714         start_trb = &ep_ring->enqueue->generic;
3715         start_cycle = ep_ring->cycle_state;
3716
3717         urb_priv = urb->hcpriv;
3718         /* Queue the first TRB, even if it's zero-length */
3719         for (i = 0; i < num_tds; i++) {
3720                 unsigned int total_packet_count;
3721                 unsigned int burst_count;
3722                 unsigned int residue;
3723
3724                 first_trb = true;
3725                 running_total = 0;
3726                 addr = start_addr + urb->iso_frame_desc[i].offset;
3727                 td_len = urb->iso_frame_desc[i].length;
3728                 td_remain_len = td_len;
3729                 total_packet_count = DIV_ROUND_UP(td_len,
3730                                 GET_MAX_PACKET(
3731                                         usb_endpoint_maxp(&urb->ep->desc)));
3732                 /* A zero-length transfer still involves at least one packet. */
3733                 if (total_packet_count == 0)
3734                         total_packet_count++;
3735                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3736                                 total_packet_count);
3737                 residue = xhci_get_last_burst_packet_count(xhci,
3738                                 urb->dev, urb, total_packet_count);
3739
3740                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3741
3742                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3743                                 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3744                 if (ret < 0) {
3745                         if (i == 0)
3746                                 return ret;
3747                         goto cleanup;
3748                 }
3749
3750                 td = urb_priv->td[i];
3751                 for (j = 0; j < trbs_per_td; j++) {
3752                         u32 remainder = 0;
3753                         field = 0;
3754
3755                         if (first_trb) {
3756                                 field = TRB_TBC(burst_count) |
3757                                         TRB_TLBPC(residue);
3758                                 /* Queue the isoc TRB */
3759                                 field |= TRB_TYPE(TRB_ISOC);
3760                                 /* Assume URB_ISO_ASAP is set */
3761                                 field |= TRB_SIA;
3762                                 if (i == 0) {
3763                                         if (start_cycle == 0)
3764                                                 field |= 0x1;
3765                                 } else
3766                                         field |= ep_ring->cycle_state;
3767                                 first_trb = false;
3768                         } else {
3769                                 /* Queue other normal TRBs */
3770                                 field |= TRB_TYPE(TRB_NORMAL);
3771                                 field |= ep_ring->cycle_state;
3772                         }
3773
3774                         /* Only set interrupt on short packet for IN EPs */
3775                         if (usb_urb_dir_in(urb))
3776                                 field |= TRB_ISP;
3777
3778                         /* Chain all the TRBs together; clear the chain bit in
3779                          * the last TRB to indicate it's the last TRB in the
3780                          * chain.
3781                          */
3782                         if (j < trbs_per_td - 1) {
3783                                 field |= TRB_CHAIN;
3784                                 more_trbs_coming = true;
3785                         } else {
3786                                 td->last_trb = ep_ring->enqueue;
3787                                 field |= TRB_IOC;
3788                                 if (xhci->hci_version == 0x100 &&
3789                                                 !(xhci->quirks &
3790                                                         XHCI_AVOID_BEI)) {
3791                                         /* Set BEI bit except for the last td */
3792                                         if (i < num_tds - 1)
3793                                                 field |= TRB_BEI;
3794                                 }
3795                                 more_trbs_coming = false;
3796                         }
3797
3798                         /* Calculate TRB length */
3799                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3800                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3801                         if (trb_buff_len > td_remain_len)
3802                                 trb_buff_len = td_remain_len;
3803
3804                         /* Set the TRB length, TD size, & interrupter fields. */
3805                         if (xhci->hci_version < 0x100) {
3806                                 remainder = xhci_td_remainder(
3807                                                 td_len - running_total);
3808                         } else {
3809                                 remainder = xhci_v1_0_td_remainder(
3810                                                 running_total, trb_buff_len,
3811                                                 total_packet_count, urb,
3812                                                 (trbs_per_td - j - 1));
3813                         }
3814                         length_field = TRB_LEN(trb_buff_len) |
3815                                 remainder |
3816                                 TRB_INTR_TARGET(0);
3817
3818                         queue_trb(xhci, ep_ring, more_trbs_coming,
3819                                 lower_32_bits(addr),
3820                                 upper_32_bits(addr),
3821                                 length_field,
3822                                 field);
3823                         running_total += trb_buff_len;
3824
3825                         addr += trb_buff_len;
3826                         td_remain_len -= trb_buff_len;
3827                 }
3828
3829                 /* Check TD length */
3830                 if (running_total != td_len) {
3831                         xhci_err(xhci, "ISOC TD length unmatch\n");
3832                         ret = -EINVAL;
3833                         goto cleanup;
3834                 }
3835         }
3836
3837         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3838                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3839                         usb_amd_quirk_pll_disable();
3840         }
3841         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3842
3843         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3844                         start_cycle, start_trb);
3845         return 0;
3846 cleanup:
3847         /* Clean up a partially enqueued isoc transfer. */
3848
3849         for (i--; i >= 0; i--)
3850                 list_del_init(&urb_priv->td[i]->td_list);
3851
3852         /* Use the first TD as a temporary variable to turn the TDs we've queued
3853          * into No-ops with a software-owned cycle bit. That way the hardware
3854          * won't accidentally start executing bogus TDs when we partially
3855          * overwrite them.  td->first_trb and td->start_seg are already set.
3856          */
3857         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3858         /* Every TRB except the first & last will have its cycle bit flipped. */
3859         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3860
3861         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3862         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3863         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3864         ep_ring->cycle_state = start_cycle;
3865         ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3866         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3867         return ret;
3868 }
3869
3870 /*
3871  * Check transfer ring to guarantee there is enough room for the urb.
3872  * Update ISO URB start_frame and interval.
3873  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3874  * update the urb->start_frame by now.
3875  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3876  */
3877 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3878                 struct urb *urb, int slot_id, unsigned int ep_index)
3879 {
3880         struct xhci_virt_device *xdev;
3881         struct xhci_ring *ep_ring;
3882         struct xhci_ep_ctx *ep_ctx;
3883         int start_frame;
3884         int xhci_interval;
3885         int ep_interval;
3886         int num_tds, num_trbs, i;
3887         int ret;
3888
3889         xdev = xhci->devs[slot_id];
3890         ep_ring = xdev->eps[ep_index].ring;
3891         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3892
3893         num_trbs = 0;
3894         num_tds = urb->number_of_packets;
3895         for (i = 0; i < num_tds; i++)
3896                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3897
3898         /* Check the ring to guarantee there is enough room for the whole urb.
3899          * Do not insert any td of the urb to the ring if the check failed.
3900          */
3901         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3902                            num_trbs, mem_flags);
3903         if (ret)
3904                 return ret;
3905
3906         start_frame = readl(&xhci->run_regs->microframe_index);
3907         start_frame &= 0x3fff;
3908
3909         urb->start_frame = start_frame;
3910         if (urb->dev->speed == USB_SPEED_LOW ||
3911                         urb->dev->speed == USB_SPEED_FULL)
3912                 urb->start_frame >>= 3;
3913
3914         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3915         ep_interval = urb->interval;
3916         /* Convert to microframes */
3917         if (urb->dev->speed == USB_SPEED_LOW ||
3918                         urb->dev->speed == USB_SPEED_FULL)
3919                 ep_interval *= 8;
3920         /* FIXME change this to a warning and a suggestion to use the new API
3921          * to set the polling interval (once the API is added).
3922          */
3923         if (xhci_interval != ep_interval) {
3924                 dev_dbg_ratelimited(&urb->dev->dev,
3925                                 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3926                                 ep_interval, ep_interval == 1 ? "" : "s",
3927                                 xhci_interval, xhci_interval == 1 ? "" : "s");
3928                 urb->interval = xhci_interval;
3929                 /* Convert back to frames for LS/FS devices */
3930                 if (urb->dev->speed == USB_SPEED_LOW ||
3931                                 urb->dev->speed == USB_SPEED_FULL)
3932                         urb->interval /= 8;
3933         }
3934         ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3935
3936         return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3937 }
3938
3939 /****           Command Ring Operations         ****/
3940
3941 /* Generic function for queueing a command TRB on the command ring.
3942  * Check to make sure there's room on the command ring for one command TRB.
3943  * Also check that there's room reserved for commands that must not fail.
3944  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3945  * then only check for the number of reserved spots.
3946  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3947  * because the command event handler may want to resubmit a failed command.
3948  */
3949 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3950                 u32 field3, u32 field4, bool command_must_succeed)
3951 {
3952         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3953         int ret;
3954
3955         if (!command_must_succeed)
3956                 reserved_trbs++;
3957
3958         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3959                         reserved_trbs, GFP_ATOMIC);
3960         if (ret < 0) {
3961                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3962                 if (command_must_succeed)
3963                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3964                                         "unfailable commands failed.\n");
3965                 return ret;
3966         }
3967         queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3968                         field4 | xhci->cmd_ring->cycle_state);
3969         return 0;
3970 }
3971
3972 /* Queue a slot enable or disable request on the command ring */
3973 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3974 {
3975         return queue_command(xhci, 0, 0, 0,
3976                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3977 }
3978
3979 /* Queue an address device command TRB */
3980 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3981                               u32 slot_id, enum xhci_setup_dev setup)
3982 {
3983         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3984                         upper_32_bits(in_ctx_ptr), 0,
3985                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
3986                         | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
3987 }
3988
3989 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3990                 u32 field1, u32 field2, u32 field3, u32 field4)
3991 {
3992         return queue_command(xhci, field1, field2, field3, field4, false);
3993 }
3994
3995 /* Queue a reset device command TRB */
3996 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3997 {
3998         return queue_command(xhci, 0, 0, 0,
3999                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4000                         false);
4001 }
4002
4003 /* Queue a configure endpoint command TRB */
4004 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
4005                 u32 slot_id, bool command_must_succeed)
4006 {
4007         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
4008                         upper_32_bits(in_ctx_ptr), 0,
4009                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4010                         command_must_succeed);
4011 }
4012
4013 /* Queue an evaluate context command TRB */
4014 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
4015                 u32 slot_id, bool command_must_succeed)
4016 {
4017         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
4018                         upper_32_bits(in_ctx_ptr), 0,
4019                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4020                         command_must_succeed);
4021 }
4022
4023 /*
4024  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4025  * activity on an endpoint that is about to be suspended.
4026  */
4027 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
4028                 unsigned int ep_index, int suspend)
4029 {
4030         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4031         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4032         u32 type = TRB_TYPE(TRB_STOP_RING);
4033         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4034
4035         return queue_command(xhci, 0, 0, 0,
4036                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
4037 }
4038
4039 /* Set Transfer Ring Dequeue Pointer command.
4040  * This should not be used for endpoints that have streams enabled.
4041  */
4042 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
4043                 unsigned int ep_index, unsigned int stream_id,
4044                 struct xhci_segment *deq_seg,
4045                 union xhci_trb *deq_ptr, u32 cycle_state)
4046 {
4047         dma_addr_t addr;
4048         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4049         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4050         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
4051         u32 type = TRB_TYPE(TRB_SET_DEQ);
4052         struct xhci_virt_ep *ep;
4053
4054         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
4055         if (addr == 0) {
4056                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4057                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4058                                 deq_seg, deq_ptr);
4059                 return 0;
4060         }
4061         ep = &xhci->devs[slot_id]->eps[ep_index];
4062         if ((ep->ep_state & SET_DEQ_PENDING)) {
4063                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4064                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4065                 return 0;
4066         }
4067         ep->queued_deq_seg = deq_seg;
4068         ep->queued_deq_ptr = deq_ptr;
4069         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
4070                         upper_32_bits(addr), trb_stream_id,
4071                         trb_slot_id | trb_ep_index | type, false);
4072 }
4073
4074 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
4075                 unsigned int ep_index)
4076 {
4077         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4078         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4079         u32 type = TRB_TYPE(TRB_RESET_EP);
4080
4081         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
4082                         false);
4083 }