2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
70 #include "xhci-trace.h"
73 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
76 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
79 unsigned long segment_offset;
81 if (!seg || !trb || trb < seg->trbs)
84 segment_offset = trb - seg->trbs;
85 if (segment_offset >= TRBS_PER_SEGMENT)
87 return seg->dma + (segment_offset * sizeof(*trb));
90 /* Does this link TRB point to the first segment in a ring,
91 * or was the previous TRB the last TRB on the last segment in the ERST?
93 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
94 struct xhci_segment *seg, union xhci_trb *trb)
96 if (ring == xhci->event_ring)
97 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
98 (seg->next == xhci->event_ring->first_seg);
100 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
103 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
104 * segment? I.e. would the updated event TRB pointer step off the end of the
107 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
108 struct xhci_segment *seg, union xhci_trb *trb)
110 if (ring == xhci->event_ring)
111 return trb == &seg->trbs[TRBS_PER_SEGMENT];
113 return TRB_TYPE_LINK_LE32(trb->link.control);
116 static int enqueue_is_link_trb(struct xhci_ring *ring)
118 struct xhci_link_trb *link = &ring->enqueue->link;
119 return TRB_TYPE_LINK_LE32(link->control);
122 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
123 * TRB is in a new segment. This does not skip over link TRBs, and it does not
124 * effect the ring dequeue or enqueue pointers.
126 static void next_trb(struct xhci_hcd *xhci,
127 struct xhci_ring *ring,
128 struct xhci_segment **seg,
129 union xhci_trb **trb)
131 if (last_trb(xhci, ring, *seg, *trb)) {
133 *trb = ((*seg)->trbs);
140 * See Cycle bit rules. SW is the consumer for the event ring only.
141 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
143 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
148 * If this is not event ring, and the dequeue pointer
149 * is not on a link TRB, there is one more usable TRB
151 if (ring->type != TYPE_EVENT &&
152 !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
153 ring->num_trbs_free++;
157 * Update the dequeue pointer further if that was a link TRB or
158 * we're at the end of an event ring segment (which doesn't have
161 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
162 if (ring->type == TYPE_EVENT &&
163 last_trb_on_last_seg(xhci, ring,
164 ring->deq_seg, ring->dequeue)) {
165 ring->cycle_state ^= 1;
167 ring->deq_seg = ring->deq_seg->next;
168 ring->dequeue = ring->deq_seg->trbs;
172 } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
176 * See Cycle bit rules. SW is the consumer for the event ring only.
177 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
179 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
180 * chain bit is set), then set the chain bit in all the following link TRBs.
181 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
182 * have their chain bit cleared (so that each Link TRB is a separate TD).
184 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
185 * set, but other sections talk about dealing with the chain bit set. This was
186 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
187 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
189 * @more_trbs_coming: Will you enqueue more TRBs before calling
190 * prepare_transfer()?
192 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
193 bool more_trbs_coming)
196 union xhci_trb *next;
198 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
199 /* If this is not event ring, there is one less usable TRB */
200 if (ring->type != TYPE_EVENT &&
201 !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
202 ring->num_trbs_free--;
203 next = ++(ring->enqueue);
206 /* Update the dequeue pointer further if that was a link TRB or we're at
207 * the end of an event ring segment (which doesn't have link TRBS)
209 while (last_trb(xhci, ring, ring->enq_seg, next)) {
210 if (ring->type != TYPE_EVENT) {
212 * If the caller doesn't plan on enqueueing more
213 * TDs before ringing the doorbell, then we
214 * don't want to give the link TRB to the
215 * hardware just yet. We'll give the link TRB
216 * back in prepare_ring() just before we enqueue
217 * the TD at the top of the ring.
219 if (!chain && !more_trbs_coming)
222 /* If we're not dealing with 0.95 hardware or
223 * isoc rings on AMD 0.96 host,
224 * carry over the chain bit of the previous TRB
225 * (which may mean the chain bit is cleared).
227 if (!(ring->type == TYPE_ISOC &&
228 (xhci->quirks & XHCI_AMD_0x96_HOST))
229 && !xhci_link_trb_quirk(xhci)) {
230 next->link.control &=
231 cpu_to_le32(~TRB_CHAIN);
232 next->link.control |=
235 /* Give this link TRB to the hardware */
237 next->link.control ^= cpu_to_le32(TRB_CYCLE);
239 /* Toggle the cycle bit after the last ring segment. */
240 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
241 ring->cycle_state = (ring->cycle_state ? 0 : 1);
244 ring->enq_seg = ring->enq_seg->next;
245 ring->enqueue = ring->enq_seg->trbs;
246 next = ring->enqueue;
251 * Check to see if there's room to enqueue num_trbs on the ring and make sure
252 * enqueue pointer will not advance into dequeue segment. See rules above.
254 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
255 unsigned int num_trbs)
257 int num_trbs_in_deq_seg;
259 if (ring->num_trbs_free < num_trbs)
262 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
263 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
264 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
271 /* Ring the host controller doorbell after placing a command on the ring */
272 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
274 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
277 xhci_dbg(xhci, "// Ding dong!\n");
278 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
279 /* Flush PCI posted writes */
280 readl(&xhci->dba->doorbell[0]);
283 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
288 xhci_dbg(xhci, "Abort command ring\n");
290 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
291 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
292 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
293 &xhci->op_regs->cmd_ring);
295 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
296 * time the completion od all xHCI commands, including
297 * the Command Abort operation. If software doesn't see
298 * CRR negated in a timely manner (e.g. longer than 5
299 * seconds), then it should assume that the there are
300 * larger problems with the xHC and assert HCRST.
302 ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring,
303 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
305 /* we are about to kill xhci, give it one more chance */
306 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
307 &xhci->op_regs->cmd_ring);
309 ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring,
310 CMD_RING_RUNNING, 0, 3 * 1000 * 1000);
314 xhci_err(xhci, "Stopped the command ring failed, "
315 "maybe the host is dead\n");
316 xhci->xhc_state |= XHCI_STATE_DYING;
325 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
326 unsigned int slot_id,
327 unsigned int ep_index,
328 unsigned int stream_id)
330 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
331 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
332 unsigned int ep_state = ep->ep_state;
334 /* Don't ring the doorbell for this endpoint if there are pending
335 * cancellations because we don't want to interrupt processing.
336 * We don't want to restart any stream rings if there's a set dequeue
337 * pointer command pending because the device can choose to start any
338 * stream once the endpoint is on the HW schedule.
339 * FIXME - check all the stream rings for pending cancellations.
341 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
342 (ep_state & EP_HALTED))
344 writel(DB_VALUE(ep_index, stream_id), db_addr);
345 /* The CPU has better things to do at this point than wait for a
346 * write-posting flush. It'll get there soon enough.
350 /* Ring the doorbell for any rings with pending URBs */
351 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
352 unsigned int slot_id,
353 unsigned int ep_index)
355 unsigned int stream_id;
356 struct xhci_virt_ep *ep;
358 ep = &xhci->devs[slot_id]->eps[ep_index];
360 /* A ring has pending URBs if its TD list is not empty */
361 if (!(ep->ep_state & EP_HAS_STREAMS)) {
362 if (ep->ring && !(list_empty(&ep->ring->td_list)))
363 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
367 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
369 struct xhci_stream_info *stream_info = ep->stream_info;
370 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
371 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
376 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
377 unsigned int slot_id, unsigned int ep_index,
378 unsigned int stream_id)
380 struct xhci_virt_ep *ep;
382 ep = &xhci->devs[slot_id]->eps[ep_index];
383 /* Common case: no streams */
384 if (!(ep->ep_state & EP_HAS_STREAMS))
387 if (stream_id == 0) {
389 "WARN: Slot ID %u, ep index %u has streams, "
390 "but URB has no stream ID.\n",
395 if (stream_id < ep->stream_info->num_streams)
396 return ep->stream_info->stream_rings[stream_id];
399 "WARN: Slot ID %u, ep index %u has "
400 "stream IDs 1 to %u allocated, "
401 "but stream ID %u is requested.\n",
403 ep->stream_info->num_streams - 1,
408 /* Get the right ring for the given URB.
409 * If the endpoint supports streams, boundary check the URB's stream ID.
410 * If the endpoint doesn't support streams, return the singular endpoint ring.
412 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
415 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
416 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
420 * Move the xHC's endpoint ring dequeue pointer past cur_td.
421 * Record the new state of the xHC's endpoint ring dequeue segment,
422 * dequeue pointer, and new consumer cycle state in state.
423 * Update our internal representation of the ring's dequeue pointer.
425 * We do this in three jumps:
426 * - First we update our new ring state to be the same as when the xHC stopped.
427 * - Then we traverse the ring to find the segment that contains
428 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
429 * any link TRBs with the toggle cycle bit set.
430 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
431 * if we've moved it past a link TRB with the toggle cycle bit set.
433 * Some of the uses of xhci_generic_trb are grotty, but if they're done
434 * with correct __le32 accesses they should work fine. Only users of this are
437 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
438 unsigned int slot_id, unsigned int ep_index,
439 unsigned int stream_id, struct xhci_td *cur_td,
440 struct xhci_dequeue_state *state)
442 struct xhci_virt_device *dev = xhci->devs[slot_id];
443 struct xhci_virt_ep *ep = &dev->eps[ep_index];
444 struct xhci_ring *ep_ring;
445 struct xhci_segment *new_seg;
446 union xhci_trb *new_deq;
449 bool cycle_found = false;
450 bool td_last_trb_found = false;
452 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
453 ep_index, stream_id);
455 xhci_warn(xhci, "WARN can't find new dequeue state "
456 "for invalid stream ID %u.\n",
461 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
462 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
463 "Finding endpoint context");
464 /* 4.6.9 the css flag is written to the stream context for streams */
465 if (ep->ep_state & EP_HAS_STREAMS) {
466 struct xhci_stream_ctx *ctx =
467 &ep->stream_info->stream_ctx_array[stream_id];
468 hw_dequeue = le64_to_cpu(ctx->stream_ring);
470 struct xhci_ep_ctx *ep_ctx
471 = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
472 hw_dequeue = le64_to_cpu(ep_ctx->deq);
475 new_seg = ep_ring->deq_seg;
476 new_deq = ep_ring->dequeue;
477 state->new_cycle_state = hw_dequeue & 0x1;
480 * We want to find the pointer, segment and cycle state of the new trb
481 * (the one after current TD's last_trb). We know the cycle state at
482 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
486 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
487 == (dma_addr_t)(hw_dequeue & ~0xf)) {
489 if (td_last_trb_found)
492 if (new_deq == cur_td->last_trb)
493 td_last_trb_found = true;
496 TRB_TYPE_LINK_LE32(new_deq->generic.field[3]) &&
497 new_deq->generic.field[3] & cpu_to_le32(LINK_TOGGLE))
498 state->new_cycle_state ^= 0x1;
500 next_trb(xhci, ep_ring, &new_seg, &new_deq);
502 /* Search wrapped around, bail out */
503 if (new_deq == ep->ring->dequeue) {
504 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
505 state->new_deq_seg = NULL;
506 state->new_deq_ptr = NULL;
510 } while (!cycle_found || !td_last_trb_found);
512 state->new_deq_seg = new_seg;
513 state->new_deq_ptr = new_deq;
515 /* Don't update the ring cycle state for the producer (us). */
516 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
517 "Cycle state = 0x%x", state->new_cycle_state);
519 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
520 "New dequeue segment = %p (virtual)",
522 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
523 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
524 "New dequeue pointer = 0x%llx (DMA)",
525 (unsigned long long) addr);
528 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
529 * (The last TRB actually points to the ring enqueue pointer, which is not part
530 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
532 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
533 struct xhci_td *cur_td, bool flip_cycle)
535 struct xhci_segment *cur_seg;
536 union xhci_trb *cur_trb;
538 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
540 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
541 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
542 /* Unchain any chained Link TRBs, but
543 * leave the pointers intact.
545 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
546 /* Flip the cycle bit (link TRBs can't be the first
550 cur_trb->generic.field[3] ^=
551 cpu_to_le32(TRB_CYCLE);
552 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
553 "Cancel (unchain) link TRB");
554 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
555 "Address = %p (0x%llx dma); "
556 "in seg %p (0x%llx dma)",
558 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
560 (unsigned long long)cur_seg->dma);
562 cur_trb->generic.field[0] = 0;
563 cur_trb->generic.field[1] = 0;
564 cur_trb->generic.field[2] = 0;
565 /* Preserve only the cycle bit of this TRB */
566 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
567 /* Flip the cycle bit except on the first or last TRB */
568 if (flip_cycle && cur_trb != cur_td->first_trb &&
569 cur_trb != cur_td->last_trb)
570 cur_trb->generic.field[3] ^=
571 cpu_to_le32(TRB_CYCLE);
572 cur_trb->generic.field[3] |= cpu_to_le32(
573 TRB_TYPE(TRB_TR_NOOP));
574 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
575 "TRB to noop at offset 0x%llx",
577 xhci_trb_virt_to_dma(cur_seg, cur_trb));
579 if (cur_trb == cur_td->last_trb)
584 static int queue_set_tr_deq(struct xhci_hcd *xhci,
585 struct xhci_command *cmd, int slot_id,
586 unsigned int ep_index, unsigned int stream_id,
587 struct xhci_segment *deq_seg,
588 union xhci_trb *deq_ptr, u32 cycle_state);
590 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
591 struct xhci_command *cmd,
592 unsigned int slot_id, unsigned int ep_index,
593 unsigned int stream_id,
594 struct xhci_dequeue_state *deq_state)
596 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
598 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
599 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
600 "new deq ptr = %p (0x%llx dma), new cycle = %u",
601 deq_state->new_deq_seg,
602 (unsigned long long)deq_state->new_deq_seg->dma,
603 deq_state->new_deq_ptr,
604 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
605 deq_state->new_cycle_state);
606 queue_set_tr_deq(xhci, cmd, slot_id, ep_index, stream_id,
607 deq_state->new_deq_seg,
608 deq_state->new_deq_ptr,
609 (u32) deq_state->new_cycle_state);
610 /* Stop the TD queueing code from ringing the doorbell until
611 * this command completes. The HC won't set the dequeue pointer
612 * if the ring is running, and ringing the doorbell starts the
615 ep->ep_state |= SET_DEQ_PENDING;
618 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
619 struct xhci_virt_ep *ep)
621 ep->ep_state &= ~EP_HALT_PENDING;
622 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
623 * timer is running on another CPU, we don't decrement stop_cmds_pending
624 * (since we didn't successfully stop the watchdog timer).
626 if (del_timer(&ep->stop_cmd_timer))
627 ep->stop_cmds_pending--;
630 /* Must be called with xhci->lock held in interrupt context */
631 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
632 struct xhci_td *cur_td, int status)
636 struct urb_priv *urb_priv;
639 urb_priv = urb->hcpriv;
641 hcd = bus_to_hcd(urb->dev->bus);
643 /* Only giveback urb when this is the last td in urb */
644 if (urb_priv->td_cnt == urb_priv->length) {
645 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
646 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
647 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
648 if (xhci->quirks & XHCI_AMD_PLL_FIX)
649 usb_amd_quirk_pll_enable();
652 usb_hcd_unlink_urb_from_ep(hcd, urb);
654 spin_unlock(&xhci->lock);
655 usb_hcd_giveback_urb(hcd, urb, status);
656 xhci_urb_free_priv(xhci, urb_priv);
657 spin_lock(&xhci->lock);
662 * When we get a command completion for a Stop Endpoint Command, we need to
663 * unlink any cancelled TDs from the ring. There are two ways to do that:
665 * 1. If the HW was in the middle of processing the TD that needs to be
666 * cancelled, then we must move the ring's dequeue pointer past the last TRB
667 * in the TD with a Set Dequeue Pointer Command.
668 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
669 * bit cleared) so that the HW will skip over them.
671 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
672 union xhci_trb *trb, struct xhci_event_cmd *event)
674 unsigned int ep_index;
675 struct xhci_ring *ep_ring;
676 struct xhci_virt_ep *ep;
677 struct list_head *entry;
678 struct xhci_td *cur_td = NULL;
679 struct xhci_td *last_unlinked_td;
681 struct xhci_dequeue_state deq_state;
683 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
684 if (!xhci->devs[slot_id])
685 xhci_warn(xhci, "Stop endpoint command "
686 "completion for disabled slot %u\n",
691 memset(&deq_state, 0, sizeof(deq_state));
692 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
693 ep = &xhci->devs[slot_id]->eps[ep_index];
695 if (list_empty(&ep->cancelled_td_list)) {
696 xhci_stop_watchdog_timer_in_irq(xhci, ep);
697 ep->stopped_td = NULL;
698 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
702 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
703 * We have the xHCI lock, so nothing can modify this list until we drop
704 * it. We're also in the event handler, so we can't get re-interrupted
705 * if another Stop Endpoint command completes
707 list_for_each(entry, &ep->cancelled_td_list) {
708 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
709 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
710 "Removing canceled TD starting at 0x%llx (dma).",
711 (unsigned long long)xhci_trb_virt_to_dma(
712 cur_td->start_seg, cur_td->first_trb));
713 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
715 /* This shouldn't happen unless a driver is mucking
716 * with the stream ID after submission. This will
717 * leave the TD on the hardware ring, and the hardware
718 * will try to execute it, and may access a buffer
719 * that has already been freed. In the best case, the
720 * hardware will execute it, and the event handler will
721 * ignore the completion event for that TD, since it was
722 * removed from the td_list for that endpoint. In
723 * short, don't muck with the stream ID after
726 xhci_warn(xhci, "WARN Cancelled URB %p "
727 "has invalid stream ID %u.\n",
729 cur_td->urb->stream_id);
730 goto remove_finished_td;
733 * If we stopped on the TD we need to cancel, then we have to
734 * move the xHC endpoint ring dequeue pointer past this TD.
736 if (cur_td == ep->stopped_td)
737 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
738 cur_td->urb->stream_id,
741 td_to_noop(xhci, ep_ring, cur_td, false);
744 * The event handler won't see a completion for this TD anymore,
745 * so remove it from the endpoint ring's TD list. Keep it in
746 * the cancelled TD list for URB completion later.
748 list_del_init(&cur_td->td_list);
750 last_unlinked_td = cur_td;
751 xhci_stop_watchdog_timer_in_irq(xhci, ep);
753 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
754 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
755 struct xhci_command *command;
756 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
757 xhci_queue_new_dequeue_state(xhci, command,
759 ep->stopped_td->urb->stream_id,
761 xhci_ring_cmd_db(xhci);
763 /* Otherwise ring the doorbell(s) to restart queued transfers */
764 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
767 /* Clear stopped_td if endpoint is not halted */
768 if (!(ep->ep_state & EP_HALTED))
769 ep->stopped_td = NULL;
772 * Drop the lock and complete the URBs in the cancelled TD list.
773 * New TDs to be cancelled might be added to the end of the list before
774 * we can complete all the URBs for the TDs we already unlinked.
775 * So stop when we've completed the URB for the last TD we unlinked.
778 cur_td = list_entry(ep->cancelled_td_list.next,
779 struct xhci_td, cancelled_td_list);
780 list_del_init(&cur_td->cancelled_td_list);
782 /* Clean up the cancelled URB */
783 /* Doesn't matter what we pass for status, since the core will
784 * just overwrite it (because the URB has been unlinked).
786 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
788 /* Stop processing the cancelled list if the watchdog timer is
791 if (xhci->xhc_state & XHCI_STATE_DYING)
793 } while (cur_td != last_unlinked_td);
795 /* Return to the event handler with xhci->lock re-acquired */
798 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
800 struct xhci_td *cur_td;
802 while (!list_empty(&ring->td_list)) {
803 cur_td = list_first_entry(&ring->td_list,
804 struct xhci_td, td_list);
805 list_del_init(&cur_td->td_list);
806 if (!list_empty(&cur_td->cancelled_td_list))
807 list_del_init(&cur_td->cancelled_td_list);
808 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
812 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
813 int slot_id, int ep_index)
815 struct xhci_td *cur_td;
816 struct xhci_virt_ep *ep;
817 struct xhci_ring *ring;
819 ep = &xhci->devs[slot_id]->eps[ep_index];
820 if ((ep->ep_state & EP_HAS_STREAMS) ||
821 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
824 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
826 ring = ep->stream_info->stream_rings[stream_id];
830 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
831 "Killing URBs for slot ID %u, ep index %u, stream %u",
832 slot_id, ep_index, stream_id);
833 xhci_kill_ring_urbs(xhci, ring);
839 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
840 "Killing URBs for slot ID %u, ep index %u",
842 xhci_kill_ring_urbs(xhci, ring);
844 while (!list_empty(&ep->cancelled_td_list)) {
845 cur_td = list_first_entry(&ep->cancelled_td_list,
846 struct xhci_td, cancelled_td_list);
847 list_del_init(&cur_td->cancelled_td_list);
848 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
852 /* Watchdog timer function for when a stop endpoint command fails to complete.
853 * In this case, we assume the host controller is broken or dying or dead. The
854 * host may still be completing some other events, so we have to be careful to
855 * let the event ring handler and the URB dequeueing/enqueueing functions know
856 * through xhci->state.
858 * The timer may also fire if the host takes a very long time to respond to the
859 * command, and the stop endpoint command completion handler cannot delete the
860 * timer before the timer function is called. Another endpoint cancellation may
861 * sneak in before the timer function can grab the lock, and that may queue
862 * another stop endpoint command and add the timer back. So we cannot use a
863 * simple flag to say whether there is a pending stop endpoint command for a
864 * particular endpoint.
866 * Instead we use a combination of that flag and a counter for the number of
867 * pending stop endpoint commands. If the timer is the tail end of the last
868 * stop endpoint command, and the endpoint's command is still pending, we assume
871 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
873 struct xhci_hcd *xhci;
874 struct xhci_virt_ep *ep;
878 ep = (struct xhci_virt_ep *) arg;
881 spin_lock_irqsave(&xhci->lock, flags);
883 ep->stop_cmds_pending--;
884 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
885 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
886 "Stop EP timer ran, but no command pending, "
888 spin_unlock_irqrestore(&xhci->lock, flags);
892 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
893 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
894 /* Oops, HC is dead or dying or at least not responding to the stop
897 xhci->xhc_state |= XHCI_STATE_DYING;
898 /* Disable interrupts from the host controller and start halting it */
900 spin_unlock_irqrestore(&xhci->lock, flags);
902 ret = xhci_halt(xhci);
904 spin_lock_irqsave(&xhci->lock, flags);
906 /* This is bad; the host is not responding to commands and it's
907 * not allowing itself to be halted. At least interrupts are
908 * disabled. If we call usb_hc_died(), it will attempt to
909 * disconnect all device drivers under this host. Those
910 * disconnect() methods will wait for all URBs to be unlinked,
911 * so we must complete them.
913 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
914 xhci_warn(xhci, "Completing active URBs anyway.\n");
915 /* We could turn all TDs on the rings to no-ops. This won't
916 * help if the host has cached part of the ring, and is slow if
917 * we want to preserve the cycle bit. Skip it and hope the host
918 * doesn't touch the memory.
921 for (i = 0; i < MAX_HC_SLOTS; i++) {
924 for (j = 0; j < 31; j++)
925 xhci_kill_endpoint_urbs(xhci, i, j);
927 spin_unlock_irqrestore(&xhci->lock, flags);
928 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
929 "Calling usb_hc_died()");
930 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
931 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
932 "xHCI host controller is dead.");
936 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
937 struct xhci_virt_device *dev,
938 struct xhci_ring *ep_ring,
939 unsigned int ep_index)
941 union xhci_trb *dequeue_temp;
942 int num_trbs_free_temp;
945 num_trbs_free_temp = ep_ring->num_trbs_free;
946 dequeue_temp = ep_ring->dequeue;
948 /* If we get two back-to-back stalls, and the first stalled transfer
949 * ends just before a link TRB, the dequeue pointer will be left on
950 * the link TRB by the code in the while loop. So we have to update
951 * the dequeue pointer one segment further, or we'll jump off
952 * the segment into la-la-land.
954 if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
955 ep_ring->deq_seg = ep_ring->deq_seg->next;
956 ep_ring->dequeue = ep_ring->deq_seg->trbs;
959 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
960 /* We have more usable TRBs */
961 ep_ring->num_trbs_free++;
963 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
965 if (ep_ring->dequeue ==
966 dev->eps[ep_index].queued_deq_ptr)
968 ep_ring->deq_seg = ep_ring->deq_seg->next;
969 ep_ring->dequeue = ep_ring->deq_seg->trbs;
971 if (ep_ring->dequeue == dequeue_temp) {
978 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
979 ep_ring->num_trbs_free = num_trbs_free_temp;
984 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
985 * we need to clear the set deq pending flag in the endpoint ring state, so that
986 * the TD queueing code can ring the doorbell again. We also need to ring the
987 * endpoint doorbell to restart the ring, but only if there aren't more
988 * cancellations pending.
990 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
991 union xhci_trb *trb, u32 cmd_comp_code)
993 unsigned int ep_index;
994 unsigned int stream_id;
995 struct xhci_ring *ep_ring;
996 struct xhci_virt_device *dev;
997 struct xhci_virt_ep *ep;
998 struct xhci_ep_ctx *ep_ctx;
999 struct xhci_slot_ctx *slot_ctx;
1001 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1002 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1003 dev = xhci->devs[slot_id];
1004 ep = &dev->eps[ep_index];
1006 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1008 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1010 /* XXX: Harmless??? */
1011 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1015 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1016 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1018 if (cmd_comp_code != COMP_SUCCESS) {
1019 unsigned int ep_state;
1020 unsigned int slot_state;
1022 switch (cmd_comp_code) {
1024 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1026 case COMP_CTX_STATE:
1027 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1028 ep_state = le32_to_cpu(ep_ctx->ep_info);
1029 ep_state &= EP_STATE_MASK;
1030 slot_state = le32_to_cpu(slot_ctx->dev_state);
1031 slot_state = GET_SLOT_STATE(slot_state);
1032 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1033 "Slot state = %u, EP state = %u",
1034 slot_state, ep_state);
1037 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1041 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1045 /* OK what do we do now? The endpoint state is hosed, and we
1046 * should never get to this point if the synchronization between
1047 * queueing, and endpoint state are correct. This might happen
1048 * if the device gets disconnected after we've finished
1049 * cancelling URBs, which might not be an error...
1053 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1054 if (ep->ep_state & EP_HAS_STREAMS) {
1055 struct xhci_stream_ctx *ctx =
1056 &ep->stream_info->stream_ctx_array[stream_id];
1057 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1059 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1061 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1062 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1063 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1064 ep->queued_deq_ptr) == deq) {
1065 /* Update the ring's dequeue segment and dequeue pointer
1066 * to reflect the new position.
1068 update_ring_for_set_deq_completion(xhci, dev,
1071 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1072 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1073 ep->queued_deq_seg, ep->queued_deq_ptr);
1077 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1078 dev->eps[ep_index].queued_deq_seg = NULL;
1079 dev->eps[ep_index].queued_deq_ptr = NULL;
1080 /* Restart any rings with pending URBs */
1081 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1084 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1085 union xhci_trb *trb, u32 cmd_comp_code)
1087 unsigned int ep_index;
1089 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1090 /* This command will only fail if the endpoint wasn't halted,
1091 * but we don't care.
1093 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1094 "Ignoring reset ep completion code of %u", cmd_comp_code);
1096 /* HW with the reset endpoint quirk needs to have a configure endpoint
1097 * command complete before the endpoint can be used. Queue that here
1098 * because the HW can't handle two commands being queued in a row.
1100 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1101 struct xhci_command *command;
1102 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1103 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1104 "Queueing configure endpoint command");
1105 xhci_queue_configure_endpoint(xhci, command,
1106 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1108 xhci_ring_cmd_db(xhci);
1110 /* Clear our internal halted state */
1111 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1115 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1118 if (cmd_comp_code == COMP_SUCCESS)
1119 xhci->slot_id = slot_id;
1124 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1126 struct xhci_virt_device *virt_dev;
1128 virt_dev = xhci->devs[slot_id];
1131 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1132 /* Delete default control endpoint resources */
1133 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1134 xhci_free_virt_device(xhci, slot_id);
1137 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1138 struct xhci_event_cmd *event, u32 cmd_comp_code)
1140 struct xhci_virt_device *virt_dev;
1141 struct xhci_input_control_ctx *ctrl_ctx;
1142 unsigned int ep_index;
1143 unsigned int ep_state;
1144 u32 add_flags, drop_flags;
1147 * Configure endpoint commands can come from the USB core
1148 * configuration or alt setting changes, or because the HW
1149 * needed an extra configure endpoint command after a reset
1150 * endpoint command or streams were being configured.
1151 * If the command was for a halted endpoint, the xHCI driver
1152 * is not waiting on the configure endpoint command.
1154 virt_dev = xhci->devs[slot_id];
1155 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1157 xhci_warn(xhci, "Could not get input context, bad type.\n");
1161 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1162 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1163 /* Input ctx add_flags are the endpoint index plus one */
1164 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1166 /* A usb_set_interface() call directly after clearing a halted
1167 * condition may race on this quirky hardware. Not worth
1168 * worrying about, since this is prototype hardware. Not sure
1169 * if this will work for streams, but streams support was
1170 * untested on this prototype.
1172 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1173 ep_index != (unsigned int) -1 &&
1174 add_flags - SLOT_FLAG == drop_flags) {
1175 ep_state = virt_dev->eps[ep_index].ep_state;
1176 if (!(ep_state & EP_HALTED))
1178 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1179 "Completed config ep cmd - "
1180 "last ep index = %d, state = %d",
1181 ep_index, ep_state);
1182 /* Clear internal halted state and restart ring(s) */
1183 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1184 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1190 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1191 struct xhci_event_cmd *event)
1193 xhci_dbg(xhci, "Completed reset device command.\n");
1194 if (!xhci->devs[slot_id])
1195 xhci_warn(xhci, "Reset device command completion "
1196 "for disabled slot %u\n", slot_id);
1199 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1200 struct xhci_event_cmd *event)
1202 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1203 xhci->error_bitmask |= 1 << 6;
1206 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1207 "NEC firmware version %2x.%02x",
1208 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1209 NEC_FW_MINOR(le32_to_cpu(event->status)));
1212 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1214 list_del(&cmd->cmd_list);
1216 if (cmd->completion) {
1217 cmd->status = status;
1218 complete(cmd->completion);
1224 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1226 struct xhci_command *cur_cmd, *tmp_cmd;
1227 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1228 xhci_complete_del_and_free_cmd(cur_cmd, COMP_CMD_ABORT);
1232 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
1233 * If there are other commands waiting then restart the ring and kick the timer.
1234 * This must be called with command ring stopped and xhci->lock held.
1236 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1237 struct xhci_command *cur_cmd)
1239 struct xhci_command *i_cmd, *tmp_cmd;
1242 /* Turn all aborted commands in list to no-ops, then restart */
1243 list_for_each_entry_safe(i_cmd, tmp_cmd, &xhci->cmd_list,
1246 if (i_cmd->status != COMP_CMD_ABORT)
1249 i_cmd->status = COMP_CMD_STOP;
1251 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
1252 i_cmd->command_trb);
1253 /* get cycle state from the original cmd trb */
1254 cycle_state = le32_to_cpu(
1255 i_cmd->command_trb->generic.field[3]) & TRB_CYCLE;
1256 /* modify the command trb to no-op command */
1257 i_cmd->command_trb->generic.field[0] = 0;
1258 i_cmd->command_trb->generic.field[1] = 0;
1259 i_cmd->command_trb->generic.field[2] = 0;
1260 i_cmd->command_trb->generic.field[3] = cpu_to_le32(
1261 TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1264 * caller waiting for completion is called when command
1265 * completion event is received for these no-op commands
1269 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1271 /* ring command ring doorbell to restart the command ring */
1272 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
1273 !(xhci->xhc_state & XHCI_STATE_DYING)) {
1274 xhci->current_cmd = cur_cmd;
1275 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
1276 xhci_ring_cmd_db(xhci);
1282 void xhci_handle_command_timeout(unsigned long data)
1284 struct xhci_hcd *xhci;
1286 unsigned long flags;
1288 struct xhci_command *cur_cmd = NULL;
1289 xhci = (struct xhci_hcd *) data;
1291 spin_lock_irqsave(&xhci->lock, flags);
1294 * If timeout work is pending, or current_cmd is NULL, it means we
1295 * raced with command completion. Command is handled so just return.
1297 if (!xhci->current_cmd || timer_pending(&xhci->cmd_timer)) {
1298 spin_unlock_irqrestore(&xhci->lock, flags);
1302 /* mark this command to be cancelled */
1303 cur_cmd = xhci->current_cmd;
1304 cur_cmd->status = COMP_CMD_ABORT;
1306 /* Make sure command ring is running before aborting it */
1307 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1308 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1309 (hw_ring_state & CMD_RING_RUNNING)) {
1310 xhci_dbg(xhci, "Command timeout\n");
1311 ret = xhci_abort_cmd_ring(xhci);
1312 if (unlikely(ret == -ESHUTDOWN)) {
1313 xhci_err(xhci, "Abort command ring failed\n");
1314 xhci_cleanup_command_queue(xhci);
1315 spin_unlock_irqrestore(&xhci->lock, flags);
1316 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1317 xhci_dbg(xhci, "xHCI host controller is dead.\n");
1322 goto time_out_completed;
1324 /* command timeout on stopped ring, ring can't be aborted */
1325 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1326 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1329 spin_unlock_irqrestore(&xhci->lock, flags);
1333 static void handle_cmd_completion(struct xhci_hcd *xhci,
1334 struct xhci_event_cmd *event)
1336 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1338 dma_addr_t cmd_dequeue_dma;
1340 union xhci_trb *cmd_trb;
1341 struct xhci_command *cmd;
1344 cmd_dma = le64_to_cpu(event->cmd_trb);
1345 cmd_trb = xhci->cmd_ring->dequeue;
1346 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1348 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1349 if (cmd_dequeue_dma == 0) {
1350 xhci->error_bitmask |= 1 << 4;
1353 /* Does the DMA address match our internal dequeue pointer address? */
1354 if (cmd_dma != (u64) cmd_dequeue_dma) {
1355 xhci->error_bitmask |= 1 << 5;
1359 cmd = list_entry(xhci->cmd_list.next, struct xhci_command, cmd_list);
1361 del_timer(&xhci->cmd_timer);
1363 trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event);
1365 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1367 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1368 if (cmd_comp_code == COMP_CMD_STOP) {
1369 xhci_handle_stopped_cmd_ring(xhci, cmd);
1373 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1375 "Command completion event does not match command\n");
1380 * Host aborted the command ring, check if the current command was
1381 * supposed to be aborted, otherwise continue normally.
1382 * The command ring is stopped now, but the xHC will issue a Command
1383 * Ring Stopped event which will cause us to restart it.
1385 if (cmd_comp_code == COMP_CMD_ABORT) {
1386 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1387 if (cmd->status == COMP_CMD_ABORT) {
1388 if (xhci->current_cmd == cmd)
1389 xhci->current_cmd = NULL;
1394 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1396 case TRB_ENABLE_SLOT:
1397 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code);
1399 case TRB_DISABLE_SLOT:
1400 xhci_handle_cmd_disable_slot(xhci, slot_id);
1403 if (!cmd->completion)
1404 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1407 case TRB_EVAL_CONTEXT:
1412 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1413 le32_to_cpu(cmd_trb->generic.field[3])));
1414 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1417 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1418 le32_to_cpu(cmd_trb->generic.field[3])));
1419 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1422 /* Is this an aborted command turned to NO-OP? */
1423 if (cmd->status == COMP_CMD_STOP)
1424 cmd_comp_code = COMP_CMD_STOP;
1427 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1428 le32_to_cpu(cmd_trb->generic.field[3])));
1429 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1432 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1433 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1435 slot_id = TRB_TO_SLOT_ID(
1436 le32_to_cpu(cmd_trb->generic.field[3]));
1437 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1439 case TRB_NEC_GET_FW:
1440 xhci_handle_cmd_nec_get_fw(xhci, event);
1443 /* Skip over unknown commands on the event ring */
1444 xhci->error_bitmask |= 1 << 6;
1448 /* restart timer if this wasn't the last command */
1449 if (cmd->cmd_list.next != &xhci->cmd_list) {
1450 xhci->current_cmd = list_entry(cmd->cmd_list.next,
1451 struct xhci_command, cmd_list);
1452 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
1453 } else if (xhci->current_cmd == cmd) {
1454 xhci->current_cmd = NULL;
1458 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1460 inc_deq(xhci, xhci->cmd_ring);
1463 static void handle_vendor_event(struct xhci_hcd *xhci,
1464 union xhci_trb *event)
1468 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1469 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1470 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1471 handle_cmd_completion(xhci, &event->event_cmd);
1474 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1475 * port registers -- USB 3.0 and USB 2.0).
1477 * Returns a zero-based port number, which is suitable for indexing into each of
1478 * the split roothubs' port arrays and bus state arrays.
1479 * Add one to it in order to call xhci_find_slot_id_by_port.
1481 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1482 struct xhci_hcd *xhci, u32 port_id)
1485 unsigned int num_similar_speed_ports = 0;
1487 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1488 * and usb2_ports are 0-based indexes. Count the number of similar
1489 * speed ports, up to 1 port before this port.
1491 for (i = 0; i < (port_id - 1); i++) {
1492 u8 port_speed = xhci->port_array[i];
1495 * Skip ports that don't have known speeds, or have duplicate
1496 * Extended Capabilities port speed entries.
1498 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1502 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1503 * 1.1 ports are under the USB 2.0 hub. If the port speed
1504 * matches the device speed, it's a similar speed port.
1506 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1507 num_similar_speed_ports++;
1509 return num_similar_speed_ports;
1512 static void handle_device_notification(struct xhci_hcd *xhci,
1513 union xhci_trb *event)
1516 struct usb_device *udev;
1518 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1519 if (!xhci->devs[slot_id]) {
1520 xhci_warn(xhci, "Device Notification event for "
1521 "unused slot %u\n", slot_id);
1525 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1527 udev = xhci->devs[slot_id]->udev;
1528 if (udev && udev->parent)
1529 usb_wakeup_notification(udev->parent, udev->portnum);
1532 static void handle_port_status(struct xhci_hcd *xhci,
1533 union xhci_trb *event)
1535 struct usb_hcd *hcd;
1540 unsigned int faked_port_index;
1542 struct xhci_bus_state *bus_state;
1543 __le32 __iomem **port_array;
1544 bool bogus_port_status = false;
1546 /* Port status change events always have a successful completion code */
1547 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1548 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1549 xhci->error_bitmask |= 1 << 8;
1551 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1552 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1554 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1555 if ((port_id <= 0) || (port_id > max_ports)) {
1556 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1557 inc_deq(xhci, xhci->event_ring);
1561 /* Figure out which usb_hcd this port is attached to:
1562 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1564 major_revision = xhci->port_array[port_id - 1];
1566 /* Find the right roothub. */
1567 hcd = xhci_to_hcd(xhci);
1568 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1569 hcd = xhci->shared_hcd;
1571 if (major_revision == 0) {
1572 xhci_warn(xhci, "Event for port %u not in "
1573 "Extended Capabilities, ignoring.\n",
1575 bogus_port_status = true;
1578 if (major_revision == DUPLICATE_ENTRY) {
1579 xhci_warn(xhci, "Event for port %u duplicated in"
1580 "Extended Capabilities, ignoring.\n",
1582 bogus_port_status = true;
1587 * Hardware port IDs reported by a Port Status Change Event include USB
1588 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1589 * resume event, but we first need to translate the hardware port ID
1590 * into the index into the ports on the correct split roothub, and the
1591 * correct bus_state structure.
1593 bus_state = &xhci->bus_state[hcd_index(hcd)];
1594 if (hcd->speed == HCD_USB3)
1595 port_array = xhci->usb3_ports;
1597 port_array = xhci->usb2_ports;
1598 /* Find the faked port hub number */
1599 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1602 temp = readl(port_array[faked_port_index]);
1603 if (hcd->state == HC_STATE_SUSPENDED) {
1604 xhci_dbg(xhci, "resume root hub\n");
1605 usb_hcd_resume_root_hub(hcd);
1608 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1609 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1611 temp1 = readl(&xhci->op_regs->command);
1612 if (!(temp1 & CMD_RUN)) {
1613 xhci_warn(xhci, "xHC is not running.\n");
1617 if (DEV_SUPERSPEED(temp)) {
1618 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1619 /* Set a flag to say the port signaled remote wakeup,
1620 * so we can tell the difference between the end of
1621 * device and host initiated resume.
1623 bus_state->port_remote_wakeup |= 1 << faked_port_index;
1624 xhci_test_and_clear_bit(xhci, port_array,
1625 faked_port_index, PORT_PLC);
1626 usb_hcd_start_port_resume(&hcd->self, faked_port_index);
1627 xhci_set_link_state(xhci, port_array, faked_port_index,
1629 /* Need to wait until the next link state change
1630 * indicates the device is actually in U0.
1632 bogus_port_status = true;
1634 } else if (!test_bit(faked_port_index,
1635 &bus_state->resuming_ports)) {
1636 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1637 bus_state->resume_done[faked_port_index] = jiffies +
1638 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1639 set_bit(faked_port_index, &bus_state->resuming_ports);
1640 mod_timer(&hcd->rh_timer,
1641 bus_state->resume_done[faked_port_index]);
1642 /* Do the rest in GetPortStatus */
1646 if ((temp & PORT_PLC) &&
1647 DEV_SUPERSPEED(temp) &&
1648 ((temp & PORT_PLS_MASK) == XDEV_U0 ||
1649 (temp & PORT_PLS_MASK) == XDEV_U1 ||
1650 (temp & PORT_PLS_MASK) == XDEV_U2)) {
1651 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1652 /* We've just brought the device into U0/1/2 through either the
1653 * Resume state after a device remote wakeup, or through the
1654 * U3Exit state after a host-initiated resume. If it's a device
1655 * initiated remote wake, don't pass up the link state change,
1656 * so the roothub behavior is consistent with external
1657 * USB 3.0 hub behavior.
1659 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1660 faked_port_index + 1);
1661 if (slot_id && xhci->devs[slot_id])
1662 xhci_ring_device(xhci, slot_id);
1663 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1664 xhci_test_and_clear_bit(xhci, port_array,
1665 faked_port_index, PORT_PLC);
1666 usb_wakeup_notification(hcd->self.root_hub,
1667 faked_port_index + 1);
1668 bogus_port_status = true;
1674 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1675 * RExit to a disconnect state). If so, let the the driver know it's
1676 * out of the RExit state.
1678 if (!DEV_SUPERSPEED(temp) && hcd->speed < HCD_USB3 &&
1679 test_and_clear_bit(faked_port_index,
1680 &bus_state->rexit_ports)) {
1681 complete(&bus_state->rexit_done[faked_port_index]);
1682 bogus_port_status = true;
1686 if (hcd->speed != HCD_USB3)
1687 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1691 /* Update event ring dequeue pointer before dropping the lock */
1692 inc_deq(xhci, xhci->event_ring);
1694 /* Don't make the USB core poll the roothub if we got a bad port status
1695 * change event. Besides, at that point we can't tell which roothub
1696 * (USB 2.0 or USB 3.0) to kick.
1698 if (bogus_port_status)
1702 * xHCI port-status-change events occur when the "or" of all the
1703 * status-change bits in the portsc register changes from 0 to 1.
1704 * New status changes won't cause an event if any other change
1705 * bits are still set. When an event occurs, switch over to
1706 * polling to avoid losing status changes.
1708 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1709 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1710 spin_unlock(&xhci->lock);
1711 /* Pass this up to the core */
1712 usb_hcd_poll_rh_status(hcd);
1713 spin_lock(&xhci->lock);
1717 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1718 * at end_trb, which may be in another segment. If the suspect DMA address is a
1719 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1722 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1723 union xhci_trb *start_trb,
1724 union xhci_trb *end_trb,
1725 dma_addr_t suspect_dma)
1727 dma_addr_t start_dma;
1728 dma_addr_t end_seg_dma;
1729 dma_addr_t end_trb_dma;
1730 struct xhci_segment *cur_seg;
1732 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1733 cur_seg = start_seg;
1738 /* We may get an event for a Link TRB in the middle of a TD */
1739 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1740 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1741 /* If the end TRB isn't in this segment, this is set to 0 */
1742 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1744 if (end_trb_dma > 0) {
1745 /* The end TRB is in this segment, so suspect should be here */
1746 if (start_dma <= end_trb_dma) {
1747 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1750 /* Case for one segment with
1751 * a TD wrapped around to the top
1753 if ((suspect_dma >= start_dma &&
1754 suspect_dma <= end_seg_dma) ||
1755 (suspect_dma >= cur_seg->dma &&
1756 suspect_dma <= end_trb_dma))
1761 /* Might still be somewhere in this segment */
1762 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1765 cur_seg = cur_seg->next;
1766 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1767 } while (cur_seg != start_seg);
1772 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1773 unsigned int slot_id, unsigned int ep_index,
1774 unsigned int stream_id,
1775 struct xhci_td *td, union xhci_trb *event_trb)
1777 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1778 struct xhci_command *command;
1779 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1783 ep->ep_state |= EP_HALTED;
1784 ep->stopped_td = td;
1785 ep->stopped_stream = stream_id;
1787 xhci_queue_reset_ep(xhci, command, slot_id, ep_index);
1788 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1790 ep->stopped_td = NULL;
1791 ep->stopped_stream = 0;
1793 xhci_ring_cmd_db(xhci);
1796 /* Check if an error has halted the endpoint ring. The class driver will
1797 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1798 * However, a babble and other errors also halt the endpoint ring, and the class
1799 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1800 * Ring Dequeue Pointer command manually.
1802 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1803 struct xhci_ep_ctx *ep_ctx,
1804 unsigned int trb_comp_code)
1806 /* TRB completion codes that may require a manual halt cleanup */
1807 if (trb_comp_code == COMP_TX_ERR ||
1808 trb_comp_code == COMP_BABBLE ||
1809 trb_comp_code == COMP_SPLIT_ERR)
1810 /* The 0.96 spec says a babbling control endpoint
1811 * is not halted. The 0.96 spec says it is. Some HW
1812 * claims to be 0.95 compliant, but it halts the control
1813 * endpoint anyway. Check if a babble halted the
1816 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1817 cpu_to_le32(EP_STATE_HALTED))
1823 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1825 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1826 /* Vendor defined "informational" completion code,
1827 * treat as not-an-error.
1829 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1831 xhci_dbg(xhci, "Treating code as success.\n");
1838 * Finish the td processing, remove the td from td list;
1839 * Return 1 if the urb can be given back.
1841 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1842 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1843 struct xhci_virt_ep *ep, int *status, bool skip)
1845 struct xhci_virt_device *xdev;
1846 struct xhci_ring *ep_ring;
1847 unsigned int slot_id;
1849 struct urb *urb = NULL;
1850 struct xhci_ep_ctx *ep_ctx;
1852 struct urb_priv *urb_priv;
1855 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1856 xdev = xhci->devs[slot_id];
1857 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1858 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1859 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1860 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1865 if (trb_comp_code == COMP_STOP_INVAL ||
1866 trb_comp_code == COMP_STOP) {
1867 /* The Endpoint Stop Command completion will take care of any
1868 * stopped TDs. A stopped TD may be restarted, so don't update
1869 * the ring dequeue pointer or take this TD off any lists yet.
1871 ep->stopped_td = td;
1874 if (trb_comp_code == COMP_STALL ||
1875 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1877 /* Issue a reset endpoint command to clear the host side
1878 * halt, followed by a set dequeue command to move the
1879 * dequeue pointer past the TD.
1880 * The class driver clears the device side halt later.
1882 xhci_cleanup_halted_endpoint(xhci,
1883 slot_id, ep_index, ep_ring->stream_id,
1886 /* Update ring dequeue pointer */
1887 while (ep_ring->dequeue != td->last_trb)
1888 inc_deq(xhci, ep_ring);
1889 inc_deq(xhci, ep_ring);
1893 /* Clean up the endpoint's TD list */
1895 urb_priv = urb->hcpriv;
1897 /* Do one last check of the actual transfer length.
1898 * If the host controller said we transferred more data than
1899 * the buffer length, urb->actual_length will be a very big
1900 * number (since it's unsigned). Play it safe and say we didn't
1901 * transfer anything.
1903 if (urb->actual_length > urb->transfer_buffer_length) {
1904 xhci_warn(xhci, "URB transfer length is wrong, "
1905 "xHC issue? req. len = %u, "
1907 urb->transfer_buffer_length,
1908 urb->actual_length);
1909 urb->actual_length = 0;
1910 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1911 *status = -EREMOTEIO;
1915 list_del_init(&td->td_list);
1916 /* Was this TD slated to be cancelled but completed anyway? */
1917 if (!list_empty(&td->cancelled_td_list))
1918 list_del_init(&td->cancelled_td_list);
1921 /* Giveback the urb when all the tds are completed */
1922 if (urb_priv->td_cnt == urb_priv->length) {
1924 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1925 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1926 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1928 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1929 usb_amd_quirk_pll_enable();
1939 * Process control tds, update urb status and actual_length.
1941 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1942 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1943 struct xhci_virt_ep *ep, int *status)
1945 struct xhci_virt_device *xdev;
1946 struct xhci_ring *ep_ring;
1947 unsigned int slot_id;
1949 struct xhci_ep_ctx *ep_ctx;
1952 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1953 xdev = xhci->devs[slot_id];
1954 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1955 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1956 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1957 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1959 switch (trb_comp_code) {
1961 if (event_trb == ep_ring->dequeue) {
1962 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1963 "without IOC set??\n");
1964 *status = -ESHUTDOWN;
1965 } else if (event_trb != td->last_trb) {
1966 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1967 "without IOC set??\n");
1968 *status = -ESHUTDOWN;
1974 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1975 *status = -EREMOTEIO;
1979 case COMP_STOP_INVAL:
1981 return finish_td(xhci, td, event_trb, event, ep, status, false);
1983 if (!xhci_requires_manual_halt_cleanup(xhci,
1984 ep_ctx, trb_comp_code))
1986 xhci_dbg(xhci, "TRB error code %u, "
1987 "halted endpoint index = %u\n",
1988 trb_comp_code, ep_index);
1989 /* else fall through */
1991 /* Did we transfer part of the data (middle) phase? */
1992 if (event_trb != ep_ring->dequeue &&
1993 event_trb != td->last_trb)
1994 td->urb->actual_length =
1995 td->urb->transfer_buffer_length -
1996 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1998 td->urb->actual_length = 0;
2000 return finish_td(xhci, td, event_trb, event, ep, status, false);
2003 * Did we transfer any data, despite the errors that might have
2004 * happened? I.e. did we get past the setup stage?
2006 if (event_trb != ep_ring->dequeue) {
2007 /* The event was for the status stage */
2008 if (event_trb == td->last_trb) {
2009 if (td->urb_length_set) {
2010 /* Don't overwrite a previously set error code
2012 if ((*status == -EINPROGRESS || *status == 0) &&
2013 (td->urb->transfer_flags
2014 & URB_SHORT_NOT_OK))
2015 /* Did we already see a short data
2017 *status = -EREMOTEIO;
2019 td->urb->actual_length =
2020 td->urb->transfer_buffer_length;
2024 * Maybe the event was for the data stage? If so, update
2025 * already the actual_length of the URB and flag it as
2026 * set, so that it is not overwritten in the event for
2029 td->urb_length_set = true;
2030 td->urb->actual_length =
2031 td->urb->transfer_buffer_length -
2032 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2033 xhci_dbg(xhci, "Waiting for status "
2039 return finish_td(xhci, td, event_trb, event, ep, status, false);
2043 * Process isochronous tds, update urb packet status and actual_length.
2045 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2046 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2047 struct xhci_virt_ep *ep, int *status)
2049 struct xhci_ring *ep_ring;
2050 struct urb_priv *urb_priv;
2053 union xhci_trb *cur_trb;
2054 struct xhci_segment *cur_seg;
2055 struct usb_iso_packet_descriptor *frame;
2057 bool skip_td = false;
2059 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2060 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2061 urb_priv = td->urb->hcpriv;
2062 idx = urb_priv->td_cnt;
2063 frame = &td->urb->iso_frame_desc[idx];
2065 /* handle completion code */
2066 switch (trb_comp_code) {
2068 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2072 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2073 trb_comp_code = COMP_SHORT_TX;
2075 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2079 frame->status = -ECOMM;
2082 case COMP_BUFF_OVER:
2084 frame->status = -EOVERFLOW;
2089 frame->status = -EPROTO;
2093 frame->status = -EPROTO;
2094 if (event_trb != td->last_trb)
2099 case COMP_STOP_INVAL:
2106 if (trb_comp_code == COMP_SUCCESS || skip_td) {
2107 frame->actual_length = frame->length;
2108 td->urb->actual_length += frame->length;
2110 for (cur_trb = ep_ring->dequeue,
2111 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2112 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2113 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2114 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2115 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2117 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2118 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2120 if (trb_comp_code != COMP_STOP_INVAL) {
2121 frame->actual_length = len;
2122 td->urb->actual_length += len;
2126 return finish_td(xhci, td, event_trb, event, ep, status, false);
2129 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2130 struct xhci_transfer_event *event,
2131 struct xhci_virt_ep *ep, int *status)
2133 struct xhci_ring *ep_ring;
2134 struct urb_priv *urb_priv;
2135 struct usb_iso_packet_descriptor *frame;
2138 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2139 urb_priv = td->urb->hcpriv;
2140 idx = urb_priv->td_cnt;
2141 frame = &td->urb->iso_frame_desc[idx];
2143 /* The transfer is partly done. */
2144 frame->status = -EXDEV;
2146 /* calc actual length */
2147 frame->actual_length = 0;
2149 /* Update ring dequeue pointer */
2150 while (ep_ring->dequeue != td->last_trb)
2151 inc_deq(xhci, ep_ring);
2152 inc_deq(xhci, ep_ring);
2154 return finish_td(xhci, td, NULL, event, ep, status, true);
2158 * Process bulk and interrupt tds, update urb status and actual_length.
2160 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2161 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2162 struct xhci_virt_ep *ep, int *status)
2164 struct xhci_ring *ep_ring;
2165 union xhci_trb *cur_trb;
2166 struct xhci_segment *cur_seg;
2169 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2170 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2172 switch (trb_comp_code) {
2174 /* Double check that the HW transferred everything. */
2175 if (event_trb != td->last_trb ||
2176 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2177 xhci_warn(xhci, "WARN Successful completion "
2179 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2180 *status = -EREMOTEIO;
2183 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2184 trb_comp_code = COMP_SHORT_TX;
2190 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2191 *status = -EREMOTEIO;
2196 /* Others already handled above */
2199 if (trb_comp_code == COMP_SHORT_TX)
2200 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2201 "%d bytes untransferred\n",
2202 td->urb->ep->desc.bEndpointAddress,
2203 td->urb->transfer_buffer_length,
2204 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2205 /* Fast path - was this the last TRB in the TD for this URB? */
2206 if (event_trb == td->last_trb) {
2207 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2208 td->urb->actual_length =
2209 td->urb->transfer_buffer_length -
2210 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2211 if (td->urb->transfer_buffer_length <
2212 td->urb->actual_length) {
2213 xhci_warn(xhci, "HC gave bad length "
2214 "of %d bytes left\n",
2215 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2216 td->urb->actual_length = 0;
2217 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2218 *status = -EREMOTEIO;
2222 /* Don't overwrite a previously set error code */
2223 if (*status == -EINPROGRESS) {
2224 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2225 *status = -EREMOTEIO;
2230 td->urb->actual_length =
2231 td->urb->transfer_buffer_length;
2232 /* Ignore a short packet completion if the
2233 * untransferred length was zero.
2235 if (*status == -EREMOTEIO)
2239 /* Slow path - walk the list, starting from the dequeue
2240 * pointer, to get the actual length transferred.
2242 td->urb->actual_length = 0;
2243 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2244 cur_trb != event_trb;
2245 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2246 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2247 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2248 td->urb->actual_length +=
2249 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2251 /* If the ring didn't stop on a Link or No-op TRB, add
2252 * in the actual bytes transferred from the Normal TRB
2254 if (trb_comp_code != COMP_STOP_INVAL)
2255 td->urb->actual_length +=
2256 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2257 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2260 return finish_td(xhci, td, event_trb, event, ep, status, false);
2264 * If this function returns an error condition, it means it got a Transfer
2265 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2266 * At this point, the host controller is probably hosed and should be reset.
2268 static int handle_tx_event(struct xhci_hcd *xhci,
2269 struct xhci_transfer_event *event)
2270 __releases(&xhci->lock)
2271 __acquires(&xhci->lock)
2273 struct xhci_virt_device *xdev;
2274 struct xhci_virt_ep *ep;
2275 struct xhci_ring *ep_ring;
2276 unsigned int slot_id;
2278 struct xhci_td *td = NULL;
2279 dma_addr_t event_dma;
2280 struct xhci_segment *event_seg;
2281 union xhci_trb *event_trb;
2282 struct urb *urb = NULL;
2283 int status = -EINPROGRESS;
2284 struct urb_priv *urb_priv;
2285 struct xhci_ep_ctx *ep_ctx;
2286 struct list_head *tmp;
2290 bool handling_skipped_tds = false;
2292 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2293 xdev = xhci->devs[slot_id];
2295 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2296 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2297 (unsigned long long) xhci_trb_virt_to_dma(
2298 xhci->event_ring->deq_seg,
2299 xhci->event_ring->dequeue),
2300 lower_32_bits(le64_to_cpu(event->buffer)),
2301 upper_32_bits(le64_to_cpu(event->buffer)),
2302 le32_to_cpu(event->transfer_len),
2303 le32_to_cpu(event->flags));
2304 xhci_dbg(xhci, "Event ring:\n");
2305 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2309 /* Endpoint ID is 1 based, our index is zero based */
2310 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2311 ep = &xdev->eps[ep_index];
2312 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2313 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2315 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2316 EP_STATE_DISABLED) {
2317 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2318 "or incorrect stream ring\n");
2319 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2320 (unsigned long long) xhci_trb_virt_to_dma(
2321 xhci->event_ring->deq_seg,
2322 xhci->event_ring->dequeue),
2323 lower_32_bits(le64_to_cpu(event->buffer)),
2324 upper_32_bits(le64_to_cpu(event->buffer)),
2325 le32_to_cpu(event->transfer_len),
2326 le32_to_cpu(event->flags));
2327 xhci_dbg(xhci, "Event ring:\n");
2328 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2332 /* Count current td numbers if ep->skip is set */
2334 list_for_each(tmp, &ep_ring->td_list)
2338 event_dma = le64_to_cpu(event->buffer);
2339 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2340 /* Look for common error cases */
2341 switch (trb_comp_code) {
2342 /* Skip codes that require special handling depending on
2346 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2348 if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
2349 ep_ring->last_td_was_short)
2350 trb_comp_code = COMP_SHORT_TX;
2352 xhci_warn_ratelimited(xhci,
2353 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2357 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2359 case COMP_STOP_INVAL:
2360 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2363 xhci_dbg(xhci, "Stalled endpoint\n");
2364 ep->ep_state |= EP_HALTED;
2368 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2371 case COMP_SPLIT_ERR:
2373 xhci_dbg(xhci, "Transfer error on endpoint\n");
2377 xhci_dbg(xhci, "Babble error on endpoint\n");
2378 status = -EOVERFLOW;
2381 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2385 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2387 case COMP_BUFF_OVER:
2388 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2392 * When the Isoch ring is empty, the xHC will generate
2393 * a Ring Overrun Event for IN Isoch endpoint or Ring
2394 * Underrun Event for OUT Isoch endpoint.
2396 xhci_dbg(xhci, "underrun event on endpoint\n");
2397 if (!list_empty(&ep_ring->td_list))
2398 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2399 "still with TDs queued?\n",
2400 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2404 xhci_dbg(xhci, "overrun event on endpoint\n");
2405 if (!list_empty(&ep_ring->td_list))
2406 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2407 "still with TDs queued?\n",
2408 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2412 xhci_warn(xhci, "WARN: detect an incompatible device");
2415 case COMP_MISSED_INT:
2417 * When encounter missed service error, one or more isoc tds
2418 * may be missed by xHC.
2419 * Set skip flag of the ep_ring; Complete the missed tds as
2420 * short transfer when process the ep_ring next time.
2423 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2427 xhci_dbg(xhci, "No Ping response error, Skip one Isoc TD\n");
2430 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2434 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2440 /* This TRB should be in the TD at the head of this ring's
2443 if (list_empty(&ep_ring->td_list)) {
2445 * Don't print wanings if it's due to a stopped endpoint
2446 * generating an extra completion event if the device
2447 * was suspended. Or, a event for the last TRB of a
2448 * short TD we already got a short event for.
2449 * The short TD is already removed from the TD list.
2452 if (!(trb_comp_code == COMP_STOP ||
2453 trb_comp_code == COMP_STOP_INVAL ||
2454 ep_ring->last_td_was_short)) {
2455 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2456 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2458 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2459 (le32_to_cpu(event->flags) &
2460 TRB_TYPE_BITMASK)>>10);
2461 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2465 xhci_dbg(xhci, "td_list is empty while skip "
2466 "flag set. Clear skip flag.\n");
2472 /* We've skipped all the TDs on the ep ring when ep->skip set */
2473 if (ep->skip && td_num == 0) {
2475 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2476 "Clear skip flag.\n");
2481 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2485 /* Is this a TRB in the currently executing TD? */
2486 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2487 td->last_trb, event_dma);
2490 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2491 * is not in the current TD pointed by ep_ring->dequeue because
2492 * that the hardware dequeue pointer still at the previous TRB
2493 * of the current TD. The previous TRB maybe a Link TD or the
2494 * last TRB of the previous TD. The command completion handle
2495 * will take care the rest.
2497 if (!event_seg && (trb_comp_code == COMP_STOP ||
2498 trb_comp_code == COMP_STOP_INVAL)) {
2505 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2506 /* Some host controllers give a spurious
2507 * successful event after a short transfer.
2510 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2511 ep_ring->last_td_was_short) {
2512 ep_ring->last_td_was_short = false;
2516 /* HC is busted, give up! */
2518 "ERROR Transfer event TRB DMA ptr not "
2519 "part of current TD\n");
2523 ret = skip_isoc_td(xhci, td, event, ep, &status);
2526 if (trb_comp_code == COMP_SHORT_TX)
2527 ep_ring->last_td_was_short = true;
2529 ep_ring->last_td_was_short = false;
2532 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2536 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2537 sizeof(*event_trb)];
2539 * No-op TRB should not trigger interrupts.
2540 * If event_trb is a no-op TRB, it means the
2541 * corresponding TD has been cancelled. Just ignore
2544 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2546 "event_trb is a no-op TRB. Skip it\n");
2550 /* Now update the urb's actual_length and give back to
2553 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2554 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2556 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2557 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2560 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2566 handling_skipped_tds = ep->skip &&
2567 trb_comp_code != COMP_MISSED_INT &&
2568 trb_comp_code != COMP_PING_ERR;
2571 * Do not update event ring dequeue pointer if we're in a loop
2572 * processing missed tds.
2574 if (!handling_skipped_tds)
2575 inc_deq(xhci, xhci->event_ring);
2579 urb_priv = urb->hcpriv;
2581 xhci_urb_free_priv(xhci, urb_priv);
2583 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2584 if ((urb->actual_length != urb->transfer_buffer_length &&
2585 (urb->transfer_flags &
2586 URB_SHORT_NOT_OK)) ||
2588 !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2589 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2590 "expected = %d, status = %d\n",
2591 urb, urb->actual_length,
2592 urb->transfer_buffer_length,
2594 spin_unlock(&xhci->lock);
2595 /* EHCI, UHCI, and OHCI always unconditionally set the
2596 * urb->status of an isochronous endpoint to 0.
2598 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2600 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2601 spin_lock(&xhci->lock);
2605 * If ep->skip is set, it means there are missed tds on the
2606 * endpoint ring need to take care of.
2607 * Process them as short transfer until reach the td pointed by
2610 } while (handling_skipped_tds);
2616 * This function handles all OS-owned events on the event ring. It may drop
2617 * xhci->lock between event processing (e.g. to pass up port status changes).
2618 * Returns >0 for "possibly more events to process" (caller should call again),
2619 * otherwise 0 if done. In future, <0 returns should indicate error code.
2621 static int xhci_handle_event(struct xhci_hcd *xhci)
2623 union xhci_trb *event;
2624 int update_ptrs = 1;
2627 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2628 xhci->error_bitmask |= 1 << 1;
2632 event = xhci->event_ring->dequeue;
2633 /* Does the HC or OS own the TRB? */
2634 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2635 xhci->event_ring->cycle_state) {
2636 xhci->error_bitmask |= 1 << 2;
2641 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2642 * speculative reads of the event's flags/data below.
2645 /* FIXME: Handle more event types. */
2646 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2647 case TRB_TYPE(TRB_COMPLETION):
2648 handle_cmd_completion(xhci, &event->event_cmd);
2650 case TRB_TYPE(TRB_PORT_STATUS):
2651 handle_port_status(xhci, event);
2654 case TRB_TYPE(TRB_TRANSFER):
2655 ret = handle_tx_event(xhci, &event->trans_event);
2657 xhci->error_bitmask |= 1 << 9;
2661 case TRB_TYPE(TRB_DEV_NOTE):
2662 handle_device_notification(xhci, event);
2665 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2667 handle_vendor_event(xhci, event);
2669 xhci->error_bitmask |= 1 << 3;
2671 /* Any of the above functions may drop and re-acquire the lock, so check
2672 * to make sure a watchdog timer didn't mark the host as non-responsive.
2674 if (xhci->xhc_state & XHCI_STATE_DYING) {
2675 xhci_dbg(xhci, "xHCI host dying, returning from "
2676 "event handler.\n");
2681 /* Update SW event ring dequeue pointer */
2682 inc_deq(xhci, xhci->event_ring);
2684 /* Are there more items on the event ring? Caller will call us again to
2691 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2692 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2693 * indicators of an event TRB error, but we check the status *first* to be safe.
2695 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2697 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2698 union xhci_trb *event_ring_deq;
2699 irqreturn_t ret = IRQ_NONE;
2700 unsigned long flags;
2705 spin_lock_irqsave(&xhci->lock, flags);
2706 /* Check if the xHC generated the interrupt, or the irq is shared */
2707 status = readl(&xhci->op_regs->status);
2708 if (status == 0xffffffff) {
2713 if (!(status & STS_EINT))
2716 if (status & STS_FATAL) {
2717 xhci_warn(xhci, "WARNING: Host System Error\n");
2724 * Clear the op reg interrupt status first,
2725 * so we can receive interrupts from other MSI-X interrupters.
2726 * Write 1 to clear the interrupt status.
2729 writel(status, &xhci->op_regs->status);
2730 /* FIXME when MSI-X is supported and there are multiple vectors */
2731 /* Clear the MSI-X event interrupt status */
2735 /* Acknowledge the PCI interrupt */
2736 irq_pending = readl(&xhci->ir_set->irq_pending);
2737 irq_pending |= IMAN_IP;
2738 writel(irq_pending, &xhci->ir_set->irq_pending);
2741 if (xhci->xhc_state & XHCI_STATE_DYING) {
2742 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2743 "Shouldn't IRQs be disabled?\n");
2744 /* Clear the event handler busy flag (RW1C);
2745 * the event ring should be empty.
2747 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2748 xhci_write_64(xhci, temp_64 | ERST_EHB,
2749 &xhci->ir_set->erst_dequeue);
2754 event_ring_deq = xhci->event_ring->dequeue;
2755 /* FIXME this should be a delayed service routine
2756 * that clears the EHB.
2758 while (xhci_handle_event(xhci) > 0) {}
2760 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2761 /* If necessary, update the HW's version of the event ring deq ptr. */
2762 if (event_ring_deq != xhci->event_ring->dequeue) {
2763 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2764 xhci->event_ring->dequeue);
2766 xhci_warn(xhci, "WARN something wrong with SW event "
2767 "ring dequeue ptr.\n");
2768 /* Update HC event ring dequeue pointer */
2769 temp_64 &= ERST_PTR_MASK;
2770 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2773 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2774 temp_64 |= ERST_EHB;
2775 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2779 spin_unlock_irqrestore(&xhci->lock, flags);
2784 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2786 return xhci_irq(hcd);
2789 /**** Endpoint Ring Operations ****/
2792 * Generic function for queueing a TRB on a ring.
2793 * The caller must have checked to make sure there's room on the ring.
2795 * @more_trbs_coming: Will you enqueue more TRBs before calling
2796 * prepare_transfer()?
2798 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2799 bool more_trbs_coming,
2800 u32 field1, u32 field2, u32 field3, u32 field4)
2802 struct xhci_generic_trb *trb;
2804 trb = &ring->enqueue->generic;
2805 trb->field[0] = cpu_to_le32(field1);
2806 trb->field[1] = cpu_to_le32(field2);
2807 trb->field[2] = cpu_to_le32(field3);
2808 trb->field[3] = cpu_to_le32(field4);
2809 inc_enq(xhci, ring, more_trbs_coming);
2813 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2814 * FIXME allocate segments if the ring is full.
2816 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2817 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2819 unsigned int num_trbs_needed;
2821 /* Make sure the endpoint has been added to xHC schedule */
2823 case EP_STATE_DISABLED:
2825 * USB core changed config/interfaces without notifying us,
2826 * or hardware is reporting the wrong state.
2828 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2830 case EP_STATE_ERROR:
2831 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2832 /* FIXME event handling code for error needs to clear it */
2833 /* XXX not sure if this should be -ENOENT or not */
2835 case EP_STATE_HALTED:
2836 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2837 case EP_STATE_STOPPED:
2838 case EP_STATE_RUNNING:
2841 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2843 * FIXME issue Configure Endpoint command to try to get the HC
2844 * back into a known state.
2850 if (room_on_ring(xhci, ep_ring, num_trbs))
2853 if (ep_ring == xhci->cmd_ring) {
2854 xhci_err(xhci, "Do not support expand command ring\n");
2858 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2859 "ERROR no room on ep ring, try ring expansion");
2860 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2861 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2863 xhci_err(xhci, "Ring expansion failed\n");
2868 if (enqueue_is_link_trb(ep_ring)) {
2869 struct xhci_ring *ring = ep_ring;
2870 union xhci_trb *next;
2872 next = ring->enqueue;
2874 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2875 /* If we're not dealing with 0.95 hardware or isoc rings
2876 * on AMD 0.96 host, clear the chain bit.
2878 if (!xhci_link_trb_quirk(xhci) &&
2879 !(ring->type == TYPE_ISOC &&
2880 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2881 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2883 next->link.control |= cpu_to_le32(TRB_CHAIN);
2886 next->link.control ^= cpu_to_le32(TRB_CYCLE);
2888 /* Toggle the cycle bit after the last ring segment. */
2889 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2890 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2892 ring->enq_seg = ring->enq_seg->next;
2893 ring->enqueue = ring->enq_seg->trbs;
2894 next = ring->enqueue;
2901 static int prepare_transfer(struct xhci_hcd *xhci,
2902 struct xhci_virt_device *xdev,
2903 unsigned int ep_index,
2904 unsigned int stream_id,
2905 unsigned int num_trbs,
2907 unsigned int td_index,
2911 struct urb_priv *urb_priv;
2913 struct xhci_ring *ep_ring;
2914 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2916 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2918 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2923 ret = prepare_ring(xhci, ep_ring,
2924 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2925 num_trbs, mem_flags);
2929 urb_priv = urb->hcpriv;
2930 td = urb_priv->td[td_index];
2932 INIT_LIST_HEAD(&td->td_list);
2933 INIT_LIST_HEAD(&td->cancelled_td_list);
2935 if (td_index == 0) {
2936 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2942 /* Add this TD to the tail of the endpoint ring's TD list */
2943 list_add_tail(&td->td_list, &ep_ring->td_list);
2944 td->start_seg = ep_ring->enq_seg;
2945 td->first_trb = ep_ring->enqueue;
2947 urb_priv->td[td_index] = td;
2952 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2954 int num_sgs, num_trbs, running_total, temp, i;
2955 struct scatterlist *sg;
2958 num_sgs = urb->num_mapped_sgs;
2959 temp = urb->transfer_buffer_length;
2962 for_each_sg(urb->sg, sg, num_sgs, i) {
2963 unsigned int len = sg_dma_len(sg);
2965 /* Scatter gather list entries may cross 64KB boundaries */
2966 running_total = TRB_MAX_BUFF_SIZE -
2967 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2968 running_total &= TRB_MAX_BUFF_SIZE - 1;
2969 if (running_total != 0)
2972 /* How many more 64KB chunks to transfer, how many more TRBs? */
2973 while (running_total < sg_dma_len(sg) && running_total < temp) {
2975 running_total += TRB_MAX_BUFF_SIZE;
2977 len = min_t(int, len, temp);
2985 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2988 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2989 "TRBs, %d left\n", __func__,
2990 urb->ep->desc.bEndpointAddress, num_trbs);
2991 if (running_total != urb->transfer_buffer_length)
2992 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2993 "queued %#x (%d), asked for %#x (%d)\n",
2995 urb->ep->desc.bEndpointAddress,
2996 running_total, running_total,
2997 urb->transfer_buffer_length,
2998 urb->transfer_buffer_length);
3001 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3002 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3003 struct xhci_generic_trb *start_trb)
3006 * Pass all the TRBs to the hardware at once and make sure this write
3011 start_trb->field[3] |= cpu_to_le32(start_cycle);
3013 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3014 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3018 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3019 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3020 * (comprised of sg list entries) can take several service intervals to
3023 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3024 struct urb *urb, int slot_id, unsigned int ep_index)
3026 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3027 xhci->devs[slot_id]->out_ctx, ep_index);
3031 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3032 ep_interval = urb->interval;
3033 /* Convert to microframes */
3034 if (urb->dev->speed == USB_SPEED_LOW ||
3035 urb->dev->speed == USB_SPEED_FULL)
3037 /* FIXME change this to a warning and a suggestion to use the new API
3038 * to set the polling interval (once the API is added).
3040 if (xhci_interval != ep_interval) {
3041 dev_dbg_ratelimited(&urb->dev->dev,
3042 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3043 ep_interval, ep_interval == 1 ? "" : "s",
3044 xhci_interval, xhci_interval == 1 ? "" : "s");
3045 urb->interval = xhci_interval;
3046 /* Convert back to frames for LS/FS devices */
3047 if (urb->dev->speed == USB_SPEED_LOW ||
3048 urb->dev->speed == USB_SPEED_FULL)
3051 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3055 * The TD size is the number of bytes remaining in the TD (including this TRB),
3056 * right shifted by 10.
3057 * It must fit in bits 21:17, so it can't be bigger than 31.
3059 static u32 xhci_td_remainder(unsigned int remainder)
3061 u32 max = (1 << (21 - 17 + 1)) - 1;
3063 if ((remainder >> 10) >= max)
3066 return (remainder >> 10) << 17;
3070 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3071 * packets remaining in the TD (*not* including this TRB).
3073 * Total TD packet count = total_packet_count =
3074 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3076 * Packets transferred up to and including this TRB = packets_transferred =
3077 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3079 * TD size = total_packet_count - packets_transferred
3081 * It must fit in bits 21:17, so it can't be bigger than 31.
3082 * The last TRB in a TD must have the TD size set to zero.
3084 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3085 unsigned int total_packet_count, struct urb *urb,
3086 unsigned int num_trbs_left)
3088 int packets_transferred;
3090 /* One TRB with a zero-length data packet. */
3091 if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3094 /* All the TRB queueing functions don't count the current TRB in
3097 packets_transferred = (running_total + trb_buff_len) /
3098 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3100 if ((total_packet_count - packets_transferred) > 31)
3102 return (total_packet_count - packets_transferred) << 17;
3105 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3106 struct urb *urb, int slot_id, unsigned int ep_index)
3108 struct xhci_ring *ep_ring;
3109 unsigned int num_trbs;
3110 struct urb_priv *urb_priv;
3112 struct scatterlist *sg;
3114 int trb_buff_len, this_sg_len, running_total, ret;
3115 unsigned int total_packet_count;
3116 bool zero_length_needed;
3120 bool more_trbs_coming;
3122 struct xhci_generic_trb *start_trb;
3125 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3129 num_trbs = count_sg_trbs_needed(xhci, urb);
3130 num_sgs = urb->num_mapped_sgs;
3131 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3132 usb_endpoint_maxp(&urb->ep->desc));
3134 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3135 ep_index, urb->stream_id,
3136 num_trbs, urb, 0, mem_flags);
3140 urb_priv = urb->hcpriv;
3142 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3143 zero_length_needed = urb->transfer_flags & URB_ZERO_PACKET &&
3144 urb_priv->length == 2;
3145 if (zero_length_needed) {
3147 xhci_dbg(xhci, "Creating zero length td.\n");
3148 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3149 ep_index, urb->stream_id,
3150 1, urb, 1, mem_flags);
3155 td = urb_priv->td[0];
3158 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3159 * until we've finished creating all the other TRBs. The ring's cycle
3160 * state may change as we enqueue the other TRBs, so save it too.
3162 start_trb = &ep_ring->enqueue->generic;
3163 start_cycle = ep_ring->cycle_state;
3167 * How much data is in the first TRB?
3169 * There are three forces at work for TRB buffer pointers and lengths:
3170 * 1. We don't want to walk off the end of this sg-list entry buffer.
3171 * 2. The transfer length that the driver requested may be smaller than
3172 * the amount of memory allocated for this scatter-gather list.
3173 * 3. TRBs buffers can't cross 64KB boundaries.
3176 addr = (u64) sg_dma_address(sg);
3177 this_sg_len = sg_dma_len(sg);
3178 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3179 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3180 if (trb_buff_len > urb->transfer_buffer_length)
3181 trb_buff_len = urb->transfer_buffer_length;
3184 last_trb_num = zero_length_needed ? 2 : 1;
3185 /* Queue the first TRB, even if it's zero-length */
3188 u32 length_field = 0;
3191 /* Don't change the cycle bit of the first TRB until later */
3194 if (start_cycle == 0)
3197 field |= ep_ring->cycle_state;
3199 /* Chain all the TRBs together; clear the chain bit in the last
3200 * TRB to indicate it's the last TRB in the chain.
3202 if (num_trbs > last_trb_num) {
3204 } else if (num_trbs == last_trb_num) {
3205 td->last_trb = ep_ring->enqueue;
3207 } else if (zero_length_needed && num_trbs == 1) {
3209 urb_priv->td[1]->last_trb = ep_ring->enqueue;
3213 /* Only set interrupt on short packet for IN endpoints */
3214 if (usb_urb_dir_in(urb))
3217 if (TRB_MAX_BUFF_SIZE -
3218 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3219 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3220 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3221 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3222 (unsigned int) addr + trb_buff_len);
3225 /* Set the TRB length, TD size, and interrupter fields. */
3226 if (xhci->hci_version < 0x100) {
3227 remainder = xhci_td_remainder(
3228 urb->transfer_buffer_length -
3231 remainder = xhci_v1_0_td_remainder(running_total,
3232 trb_buff_len, total_packet_count, urb,
3235 length_field = TRB_LEN(trb_buff_len) |
3240 more_trbs_coming = true;
3242 more_trbs_coming = false;
3243 queue_trb(xhci, ep_ring, more_trbs_coming,
3244 lower_32_bits(addr),
3245 upper_32_bits(addr),
3247 field | TRB_TYPE(TRB_NORMAL));
3249 running_total += trb_buff_len;
3251 /* Calculate length for next transfer --
3252 * Are we done queueing all the TRBs for this sg entry?
3254 this_sg_len -= trb_buff_len;
3255 if (this_sg_len == 0) {
3260 addr = (u64) sg_dma_address(sg);
3261 this_sg_len = sg_dma_len(sg);
3263 addr += trb_buff_len;
3266 trb_buff_len = TRB_MAX_BUFF_SIZE -
3267 (addr & (TRB_MAX_BUFF_SIZE - 1));
3268 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3269 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3271 urb->transfer_buffer_length - running_total;
3272 } while (num_trbs > 0);
3274 check_trb_math(urb, num_trbs, running_total);
3275 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3276 start_cycle, start_trb);
3280 /* This is very similar to what ehci-q.c qtd_fill() does */
3281 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3282 struct urb *urb, int slot_id, unsigned int ep_index)
3284 struct xhci_ring *ep_ring;
3285 struct urb_priv *urb_priv;
3288 struct xhci_generic_trb *start_trb;
3291 bool more_trbs_coming;
3292 bool zero_length_needed;
3294 u32 field, length_field;
3296 int running_total, trb_buff_len, ret;
3297 unsigned int total_packet_count;
3301 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3303 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3308 /* How much data is (potentially) left before the 64KB boundary? */
3309 running_total = TRB_MAX_BUFF_SIZE -
3310 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3311 running_total &= TRB_MAX_BUFF_SIZE - 1;
3313 /* If there's some data on this 64KB chunk, or we have to send a
3314 * zero-length transfer, we need at least one TRB
3316 if (running_total != 0 || urb->transfer_buffer_length == 0)
3318 /* How many more 64KB chunks to transfer, how many more TRBs? */
3319 while (running_total < urb->transfer_buffer_length) {
3321 running_total += TRB_MAX_BUFF_SIZE;
3324 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3325 ep_index, urb->stream_id,
3326 num_trbs, urb, 0, mem_flags);
3330 urb_priv = urb->hcpriv;
3332 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3333 zero_length_needed = urb->transfer_flags & URB_ZERO_PACKET &&
3334 urb_priv->length == 2;
3335 if (zero_length_needed) {
3337 xhci_dbg(xhci, "Creating zero length td.\n");
3338 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3339 ep_index, urb->stream_id,
3340 1, urb, 1, mem_flags);
3345 td = urb_priv->td[0];
3348 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3349 * until we've finished creating all the other TRBs. The ring's cycle
3350 * state may change as we enqueue the other TRBs, so save it too.
3352 start_trb = &ep_ring->enqueue->generic;
3353 start_cycle = ep_ring->cycle_state;
3356 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3357 usb_endpoint_maxp(&urb->ep->desc));
3358 /* How much data is in the first TRB? */
3359 addr = (u64) urb->transfer_dma;
3360 trb_buff_len = TRB_MAX_BUFF_SIZE -
3361 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3362 if (trb_buff_len > urb->transfer_buffer_length)
3363 trb_buff_len = urb->transfer_buffer_length;
3366 last_trb_num = zero_length_needed ? 2 : 1;
3367 /* Queue the first TRB, even if it's zero-length */
3372 /* Don't change the cycle bit of the first TRB until later */
3375 if (start_cycle == 0)
3378 field |= ep_ring->cycle_state;
3380 /* Chain all the TRBs together; clear the chain bit in the last
3381 * TRB to indicate it's the last TRB in the chain.
3383 if (num_trbs > last_trb_num) {
3385 } else if (num_trbs == last_trb_num) {
3386 td->last_trb = ep_ring->enqueue;
3388 } else if (zero_length_needed && num_trbs == 1) {
3390 urb_priv->td[1]->last_trb = ep_ring->enqueue;
3394 /* Only set interrupt on short packet for IN endpoints */
3395 if (usb_urb_dir_in(urb))
3398 /* Set the TRB length, TD size, and interrupter fields. */
3399 if (xhci->hci_version < 0x100) {
3400 remainder = xhci_td_remainder(
3401 urb->transfer_buffer_length -
3404 remainder = xhci_v1_0_td_remainder(running_total,
3405 trb_buff_len, total_packet_count, urb,
3408 length_field = TRB_LEN(trb_buff_len) |
3413 more_trbs_coming = true;
3415 more_trbs_coming = false;
3416 queue_trb(xhci, ep_ring, more_trbs_coming,
3417 lower_32_bits(addr),
3418 upper_32_bits(addr),
3420 field | TRB_TYPE(TRB_NORMAL));
3422 running_total += trb_buff_len;
3424 /* Calculate length for next transfer */
3425 addr += trb_buff_len;
3426 trb_buff_len = urb->transfer_buffer_length - running_total;
3427 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3428 trb_buff_len = TRB_MAX_BUFF_SIZE;
3429 } while (num_trbs > 0);
3431 check_trb_math(urb, num_trbs, running_total);
3432 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3433 start_cycle, start_trb);
3437 /* Caller must have locked xhci->lock */
3438 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3439 struct urb *urb, int slot_id, unsigned int ep_index)
3441 struct xhci_ring *ep_ring;
3444 struct usb_ctrlrequest *setup;
3445 struct xhci_generic_trb *start_trb;
3447 u32 field, length_field;
3448 struct urb_priv *urb_priv;
3451 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3456 * Need to copy setup packet into setup TRB, so we can't use the setup
3459 if (!urb->setup_packet)
3462 /* 1 TRB for setup, 1 for status */
3465 * Don't need to check if we need additional event data and normal TRBs,
3466 * since data in control transfers will never get bigger than 16MB
3467 * XXX: can we get a buffer that crosses 64KB boundaries?
3469 if (urb->transfer_buffer_length > 0)
3471 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3472 ep_index, urb->stream_id,
3473 num_trbs, urb, 0, mem_flags);
3477 urb_priv = urb->hcpriv;
3478 td = urb_priv->td[0];
3481 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3482 * until we've finished creating all the other TRBs. The ring's cycle
3483 * state may change as we enqueue the other TRBs, so save it too.
3485 start_trb = &ep_ring->enqueue->generic;
3486 start_cycle = ep_ring->cycle_state;
3488 /* Queue setup TRB - see section 6.4.1.2.1 */
3489 /* FIXME better way to translate setup_packet into two u32 fields? */
3490 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3492 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3493 if (start_cycle == 0)
3496 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3497 if (xhci->hci_version >= 0x100) {
3498 if (urb->transfer_buffer_length > 0) {
3499 if (setup->bRequestType & USB_DIR_IN)
3500 field |= TRB_TX_TYPE(TRB_DATA_IN);
3502 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3506 queue_trb(xhci, ep_ring, true,
3507 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3508 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3509 TRB_LEN(8) | TRB_INTR_TARGET(0),
3510 /* Immediate data in pointer */
3513 /* If there's data, queue data TRBs */
3514 /* Only set interrupt on short packet for IN endpoints */
3515 if (usb_urb_dir_in(urb))
3516 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3518 field = TRB_TYPE(TRB_DATA);
3520 length_field = TRB_LEN(urb->transfer_buffer_length) |
3521 xhci_td_remainder(urb->transfer_buffer_length) |
3523 if (urb->transfer_buffer_length > 0) {
3524 if (setup->bRequestType & USB_DIR_IN)
3525 field |= TRB_DIR_IN;
3526 queue_trb(xhci, ep_ring, true,
3527 lower_32_bits(urb->transfer_dma),
3528 upper_32_bits(urb->transfer_dma),
3530 field | ep_ring->cycle_state);
3533 /* Save the DMA address of the last TRB in the TD */
3534 td->last_trb = ep_ring->enqueue;
3536 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3537 /* If the device sent data, the status stage is an OUT transfer */
3538 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3542 queue_trb(xhci, ep_ring, false,
3546 /* Event on completion */
3547 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3549 giveback_first_trb(xhci, slot_id, ep_index, 0,
3550 start_cycle, start_trb);
3554 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3555 struct urb *urb, int i)
3560 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3561 td_len = urb->iso_frame_desc[i].length;
3563 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3572 * The transfer burst count field of the isochronous TRB defines the number of
3573 * bursts that are required to move all packets in this TD. Only SuperSpeed
3574 * devices can burst up to bMaxBurst number of packets per service interval.
3575 * This field is zero based, meaning a value of zero in the field means one
3576 * burst. Basically, for everything but SuperSpeed devices, this field will be
3577 * zero. Only xHCI 1.0 host controllers support this field.
3579 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3580 struct usb_device *udev,
3581 struct urb *urb, unsigned int total_packet_count)
3583 unsigned int max_burst;
3585 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3588 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3589 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3593 * Returns the number of packets in the last "burst" of packets. This field is
3594 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3595 * the last burst packet count is equal to the total number of packets in the
3596 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3597 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3598 * contain 1 to (bMaxBurst + 1) packets.
3600 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3601 struct usb_device *udev,
3602 struct urb *urb, unsigned int total_packet_count)
3604 unsigned int max_burst;
3605 unsigned int residue;
3607 if (xhci->hci_version < 0x100)
3610 switch (udev->speed) {
3611 case USB_SPEED_SUPER:
3612 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3613 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3614 residue = total_packet_count % (max_burst + 1);
3615 /* If residue is zero, the last burst contains (max_burst + 1)
3616 * number of packets, but the TLBPC field is zero-based.
3622 if (total_packet_count == 0)
3624 return total_packet_count - 1;
3628 /* This is for isoc transfer */
3629 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3630 struct urb *urb, int slot_id, unsigned int ep_index)
3632 struct xhci_ring *ep_ring;
3633 struct urb_priv *urb_priv;
3635 int num_tds, trbs_per_td;
3636 struct xhci_generic_trb *start_trb;
3639 u32 field, length_field;
3640 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3641 u64 start_addr, addr;
3643 bool more_trbs_coming;
3645 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3647 num_tds = urb->number_of_packets;
3649 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3653 start_addr = (u64) urb->transfer_dma;
3654 start_trb = &ep_ring->enqueue->generic;
3655 start_cycle = ep_ring->cycle_state;
3657 urb_priv = urb->hcpriv;
3658 /* Queue the first TRB, even if it's zero-length */
3659 for (i = 0; i < num_tds; i++) {
3660 unsigned int total_packet_count;
3661 unsigned int burst_count;
3662 unsigned int residue;
3666 addr = start_addr + urb->iso_frame_desc[i].offset;
3667 td_len = urb->iso_frame_desc[i].length;
3668 td_remain_len = td_len;
3669 total_packet_count = DIV_ROUND_UP(td_len,
3671 usb_endpoint_maxp(&urb->ep->desc)));
3672 /* A zero-length transfer still involves at least one packet. */
3673 if (total_packet_count == 0)
3674 total_packet_count++;
3675 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3676 total_packet_count);
3677 residue = xhci_get_last_burst_packet_count(xhci,
3678 urb->dev, urb, total_packet_count);
3680 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3682 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3683 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3690 td = urb_priv->td[i];
3691 for (j = 0; j < trbs_per_td; j++) {
3696 field = TRB_TBC(burst_count) |
3698 /* Queue the isoc TRB */
3699 field |= TRB_TYPE(TRB_ISOC);
3700 /* Assume URB_ISO_ASAP is set */
3703 if (start_cycle == 0)
3706 field |= ep_ring->cycle_state;
3709 /* Queue other normal TRBs */
3710 field |= TRB_TYPE(TRB_NORMAL);
3711 field |= ep_ring->cycle_state;
3714 /* Only set interrupt on short packet for IN EPs */
3715 if (usb_urb_dir_in(urb))
3718 /* Chain all the TRBs together; clear the chain bit in
3719 * the last TRB to indicate it's the last TRB in the
3722 if (j < trbs_per_td - 1) {
3724 more_trbs_coming = true;
3726 td->last_trb = ep_ring->enqueue;
3728 if (xhci->hci_version == 0x100 &&
3731 /* Set BEI bit except for the last td */
3732 if (i < num_tds - 1)
3735 more_trbs_coming = false;
3738 /* Calculate TRB length */
3739 trb_buff_len = TRB_MAX_BUFF_SIZE -
3740 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3741 if (trb_buff_len > td_remain_len)
3742 trb_buff_len = td_remain_len;
3744 /* Set the TRB length, TD size, & interrupter fields. */
3745 if (xhci->hci_version < 0x100) {
3746 remainder = xhci_td_remainder(
3747 td_len - running_total);
3749 remainder = xhci_v1_0_td_remainder(
3750 running_total, trb_buff_len,
3751 total_packet_count, urb,
3752 (trbs_per_td - j - 1));
3754 length_field = TRB_LEN(trb_buff_len) |
3758 queue_trb(xhci, ep_ring, more_trbs_coming,
3759 lower_32_bits(addr),
3760 upper_32_bits(addr),
3763 running_total += trb_buff_len;
3765 addr += trb_buff_len;
3766 td_remain_len -= trb_buff_len;
3769 /* Check TD length */
3770 if (running_total != td_len) {
3771 xhci_err(xhci, "ISOC TD length unmatch\n");
3777 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3778 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3779 usb_amd_quirk_pll_disable();
3781 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3783 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3784 start_cycle, start_trb);
3787 /* Clean up a partially enqueued isoc transfer. */
3789 for (i--; i >= 0; i--)
3790 list_del_init(&urb_priv->td[i]->td_list);
3792 /* Use the first TD as a temporary variable to turn the TDs we've queued
3793 * into No-ops with a software-owned cycle bit. That way the hardware
3794 * won't accidentally start executing bogus TDs when we partially
3795 * overwrite them. td->first_trb and td->start_seg are already set.
3797 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3798 /* Every TRB except the first & last will have its cycle bit flipped. */
3799 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3801 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3802 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3803 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3804 ep_ring->cycle_state = start_cycle;
3805 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3806 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3811 * Check transfer ring to guarantee there is enough room for the urb.
3812 * Update ISO URB start_frame and interval.
3813 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3814 * update the urb->start_frame by now.
3815 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3817 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3818 struct urb *urb, int slot_id, unsigned int ep_index)
3820 struct xhci_virt_device *xdev;
3821 struct xhci_ring *ep_ring;
3822 struct xhci_ep_ctx *ep_ctx;
3826 int num_tds, num_trbs, i;
3829 xdev = xhci->devs[slot_id];
3830 ep_ring = xdev->eps[ep_index].ring;
3831 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3834 num_tds = urb->number_of_packets;
3835 for (i = 0; i < num_tds; i++)
3836 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3838 /* Check the ring to guarantee there is enough room for the whole urb.
3839 * Do not insert any td of the urb to the ring if the check failed.
3841 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3842 num_trbs, mem_flags);
3846 start_frame = readl(&xhci->run_regs->microframe_index);
3847 start_frame &= 0x3fff;
3849 urb->start_frame = start_frame;
3850 if (urb->dev->speed == USB_SPEED_LOW ||
3851 urb->dev->speed == USB_SPEED_FULL)
3852 urb->start_frame >>= 3;
3854 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3855 ep_interval = urb->interval;
3856 /* Convert to microframes */
3857 if (urb->dev->speed == USB_SPEED_LOW ||
3858 urb->dev->speed == USB_SPEED_FULL)
3860 /* FIXME change this to a warning and a suggestion to use the new API
3861 * to set the polling interval (once the API is added).
3863 if (xhci_interval != ep_interval) {
3864 dev_dbg_ratelimited(&urb->dev->dev,
3865 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3866 ep_interval, ep_interval == 1 ? "" : "s",
3867 xhci_interval, xhci_interval == 1 ? "" : "s");
3868 urb->interval = xhci_interval;
3869 /* Convert back to frames for LS/FS devices */
3870 if (urb->dev->speed == USB_SPEED_LOW ||
3871 urb->dev->speed == USB_SPEED_FULL)
3874 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3876 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3879 /**** Command Ring Operations ****/
3881 /* Generic function for queueing a command TRB on the command ring.
3882 * Check to make sure there's room on the command ring for one command TRB.
3883 * Also check that there's room reserved for commands that must not fail.
3884 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3885 * then only check for the number of reserved spots.
3886 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3887 * because the command event handler may want to resubmit a failed command.
3889 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3890 u32 field1, u32 field2,
3891 u32 field3, u32 field4, bool command_must_succeed)
3893 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3895 if (xhci->xhc_state & XHCI_STATE_DYING)
3898 if (!command_must_succeed)
3901 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3902 reserved_trbs, GFP_ATOMIC);
3904 xhci_err(xhci, "ERR: No room for command on command ring\n");
3905 if (command_must_succeed)
3906 xhci_err(xhci, "ERR: Reserved TRB counting for "
3907 "unfailable commands failed.\n");
3911 cmd->command_trb = xhci->cmd_ring->enqueue;
3912 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
3914 /* if there are no other commands queued we start the timeout timer */
3915 if (xhci->cmd_list.next == &cmd->cmd_list &&
3916 !timer_pending(&xhci->cmd_timer)) {
3917 xhci->current_cmd = cmd;
3918 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
3921 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3922 field4 | xhci->cmd_ring->cycle_state);
3926 /* Queue a slot enable or disable request on the command ring */
3927 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
3928 u32 trb_type, u32 slot_id)
3930 return queue_command(xhci, cmd, 0, 0, 0,
3931 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3934 /* Queue an address device command TRB */
3935 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3936 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
3938 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3939 upper_32_bits(in_ctx_ptr), 0,
3940 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
3941 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
3944 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3945 u32 field1, u32 field2, u32 field3, u32 field4)
3947 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
3950 /* Queue a reset device command TRB */
3951 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3954 return queue_command(xhci, cmd, 0, 0, 0,
3955 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3959 /* Queue a configure endpoint command TRB */
3960 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
3961 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
3962 u32 slot_id, bool command_must_succeed)
3964 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3965 upper_32_bits(in_ctx_ptr), 0,
3966 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3967 command_must_succeed);
3970 /* Queue an evaluate context command TRB */
3971 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
3972 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
3974 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3975 upper_32_bits(in_ctx_ptr), 0,
3976 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3977 command_must_succeed);
3981 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3982 * activity on an endpoint that is about to be suspended.
3984 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
3985 int slot_id, unsigned int ep_index, int suspend)
3987 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3988 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3989 u32 type = TRB_TYPE(TRB_STOP_RING);
3990 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3992 return queue_command(xhci, cmd, 0, 0, 0,
3993 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3996 /* Set Transfer Ring Dequeue Pointer command.
3997 * This should not be used for endpoints that have streams enabled.
3999 static int queue_set_tr_deq(struct xhci_hcd *xhci, struct xhci_command *cmd,
4001 unsigned int ep_index, unsigned int stream_id,
4002 struct xhci_segment *deq_seg,
4003 union xhci_trb *deq_ptr, u32 cycle_state)
4006 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4007 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4008 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
4010 u32 type = TRB_TYPE(TRB_SET_DEQ);
4011 struct xhci_virt_ep *ep;
4013 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
4015 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4016 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4020 ep = &xhci->devs[slot_id]->eps[ep_index];
4021 if ((ep->ep_state & SET_DEQ_PENDING)) {
4022 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4023 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4026 ep->queued_deq_seg = deq_seg;
4027 ep->queued_deq_ptr = deq_ptr;
4029 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4030 return queue_command(xhci, cmd,
4031 lower_32_bits(addr) | trb_sct | cycle_state,
4032 upper_32_bits(addr), trb_stream_id,
4033 trb_slot_id | trb_ep_index | type, false);
4036 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4037 int slot_id, unsigned int ep_index)
4039 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4040 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4041 u32 type = TRB_TYPE(TRB_RESET_EP);
4043 return queue_command(xhci, cmd, 0, 0, 0,
4044 trb_slot_id | trb_ep_index | type, false);