drivers/usb/host/xhci-pci.c

   1 /*
   2  * xHCI host controller driver PCI Bus Glue.
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/pci.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26
  27 #include "xhci.h"
  28 #include "xhci-trace.h"
  29
  30 /* Device for a quirk */
  31 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  32 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  35
  36 #define PCI_VENDOR_ID_ETRON             0x1b6f
  37 #define PCI_DEVICE_ID_ASROCK_P67        0x7023
  38
  39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  40 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  41 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  42 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  43 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  44 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  45 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  46 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  47 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  48 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  49
  50 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
  51 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
  52 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
  53 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
  54
  55 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  56
  57 static const char hcd_name[] = "xhci_hcd";
  58
  59 /* called after powerup, by probe or system-pm "wakeup" */
  60 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  61 {
  62         /*
  63          * TODO: Implement finding debug ports later.
  64          * TODO: see if there are any quirks that need to be added to handle
  65          * new extended capabilities.
  66          */
  67
  68         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  69         if (!pci_set_mwi(pdev))
  70                 xhci_dbg(xhci, "MWI active\n");
  71
  72         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  73         return 0;
  74 }
  75
  76 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  77 {
  78         struct pci_dev          *pdev = to_pci_dev(dev);
  79
  80         /* Look for vendor-specific quirks */
  81         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
  82                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
  83                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
  84                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  85                                 pdev->revision == 0x0) {
  86                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
  87                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  88                                 "QUIRK: Fresco Logic xHC needs configure"
  89                                 " endpoint cmd after reset endpoint");
  90                 }
  91                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
  92                                 pdev->revision == 0x4) {
  93                         xhci->quirks |= XHCI_SLOW_SUSPEND;
  94                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  95                                 "QUIRK: Fresco Logic xHC revision %u"
  96                                 "must be suspended extra slowly",
  97                                 pdev->revision);
  98                 }
  99                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 100                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 101                 /* Fresco Logic confirms: all revisions of this chip do not
 102                  * support MSI, even though some of them claim to in their PCI
 103                  * capabilities.
 104                  */
 105                 xhci->quirks |= XHCI_BROKEN_MSI;
 106                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 107                                 "QUIRK: Fresco Logic revision %u "
 108                                 "has broken MSI implementation",
 109                                 pdev->revision);
 110                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 111         }
 112
 113         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 114                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 115                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 116
 117         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 118                 xhci->quirks |= XHCI_NEC_HOST;
 119
 120         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 121                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 122
 123         /* AMD PLL quirk */
 124         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
 125                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 126
 127         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 128                 (pdev->device == 0x15e0 ||
 129                  pdev->device == 0x15e1 ||
 130                  pdev->device == 0x43bb))
 131                 xhci->quirks |= XHCI_SUSPEND_DELAY;
 132
 133         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 134             (pdev->device == 0x15e0 || pdev->device == 0x15e1))
 135                 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
 136
 137         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 138                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 139
 140         if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
 141                 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
 142                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
 143                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
 144                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
 145                 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
 146
 147         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 148                 xhci->quirks |= XHCI_LPM_SUPPORT;
 149                 xhci->quirks |= XHCI_INTEL_HOST;
 150                 xhci->quirks |= XHCI_AVOID_BEI;
 151         }
 152         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 153                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 154                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 155                 xhci->limit_active_eps = 64;
 156                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 157                 /*
 158                  * PPT desktop boards DH77EB and DH77DF will power back on after
 159                  * a few seconds of being shutdown.  The fix for this is to
 160                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 161                  * DMI information to find those particular boards (since each
 162                  * vendor will change the board name), so we have to key off all
 163                  * PPT chipsets.
 164                  */
 165                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 166         }
 167         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 168                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 169                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 170                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 171                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 172         }
 173         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 174                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 175                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 176                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 177                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 178                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 179                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 180                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) {
 181                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 182         }
 183         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 184             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 185              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 186              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 187              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 188              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 189                 xhci->quirks |= XHCI_MISSING_CAS;
 190
 191         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 192                         pdev->device == PCI_DEVICE_ID_ASROCK_P67) {
 193                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 194                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 195                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 196         }
 197         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 198                         pdev->device == 0x0014)
 199                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 200         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 201                         pdev->device == 0x0015)
 202                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 203         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 204                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 205
 206         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 207         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 208                         pdev->device == 0x3432)
 209                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 210
 211         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 212                         pdev->device == 0x1042)
 213                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 214         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 215                         pdev->device == 0x1142)
 216                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 217
 218         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 219                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 220                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 221
 222         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 223                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 224                                 "QUIRK: Resetting on resume");
 225 }
 226
 227 /*
 228  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 229  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 230  */
 231 static void xhci_pme_quirk(struct xhci_hcd *xhci)
 232 {
 233         u32 val;
 234         void __iomem *reg;
 235
 236         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 237         val = readl(reg);
 238         writel(val | BIT(28), reg);
 239         readl(reg);
 240 }
 241
 242 /* called during probe() after chip reset completes */
 243 static int xhci_pci_setup(struct usb_hcd *hcd)
 244 {
 245         struct xhci_hcd         *xhci;
 246         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 247         int                     retval;
 248
 249         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 250         if (retval)
 251                 return retval;
 252
 253         xhci = hcd_to_xhci(hcd);
 254         if (!usb_hcd_is_primary_hcd(hcd))
 255                 return 0;
 256
 257         pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 258         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 259
 260         /* Find any debug ports */
 261         retval = xhci_pci_reinit(xhci, pdev);
 262         if (!retval)
 263                 return retval;
 264
 265         kfree(xhci);
 266         return retval;
 267 }
 268
 269 /*
 270  * We need to register our own PCI probe function (instead of the USB core's
 271  * function) in order to create a second roothub under xHCI.
 272  */
 273 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 274 {
 275         int retval;
 276         struct xhci_hcd *xhci;
 277         struct hc_driver *driver;
 278         struct usb_hcd *hcd;
 279
 280         driver = (struct hc_driver *)id->driver_data;
 281
 282         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 283         pm_runtime_get_noresume(&dev->dev);
 284
 285         /* Register the USB 2.0 roothub.
 286          * FIXME: USB core must know to register the USB 2.0 roothub first.
 287          * This is sort of silly, because we could just set the HCD driver flags
 288          * to say USB 2.0, but I'm not sure what the implications would be in
 289          * the other parts of the HCD code.
 290          */
 291         retval = usb_hcd_pci_probe(dev, id);
 292
 293         if (retval)
 294                 goto put_runtime_pm;
 295
 296         /* USB 2.0 roothub is stored in the PCI device now. */
 297         hcd = dev_get_drvdata(&dev->dev);
 298         xhci = hcd_to_xhci(hcd);
 299         xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
 300                                 pci_name(dev), hcd);
 301         if (!xhci->shared_hcd) {
 302                 retval = -ENOMEM;
 303                 goto dealloc_usb2_hcd;
 304         }
 305
 306         /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
 307          * is called by usb_add_hcd().
 308          */
 309         *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
 310
 311         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 312                         IRQF_SHARED);
 313         if (retval)
 314                 goto put_usb3_hcd;
 315         /* Roothub already marked as USB 3.0 speed */
 316
 317         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 318                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 319                 xhci->shared_hcd->can_do_streams = 1;
 320
 321         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 322         pm_runtime_put_noidle(&dev->dev);
 323
 324         return 0;
 325
 326 put_usb3_hcd:
 327         usb_put_hcd(xhci->shared_hcd);
 328 dealloc_usb2_hcd:
 329         usb_hcd_pci_remove(dev);
 330 put_runtime_pm:
 331         pm_runtime_put_noidle(&dev->dev);
 332         return retval;
 333 }
 334
 335 static void xhci_pci_remove(struct pci_dev *dev)
 336 {
 337         struct xhci_hcd *xhci;
 338
 339         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 340         if (xhci->shared_hcd) {
 341                 usb_remove_hcd(xhci->shared_hcd);
 342                 usb_put_hcd(xhci->shared_hcd);
 343         }
 344
 345         /* Workaround for spurious wakeups at shutdown with HSW */
 346         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 347                 pci_set_power_state(dev, PCI_D3hot);
 348
 349         usb_hcd_pci_remove(dev);
 350
 351         kfree(xhci);
 352 }
 353
 354 #ifdef CONFIG_PM
 355 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 356 {
 357         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 358         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 359
 360         /*
 361          * Systems with the TI redriver that loses port status change events
 362          * need to have the registers polled during D3, so avoid D3cold.
 363          */
 364         if (xhci_compliance_mode_recovery_timer_quirk_check())
 365                 pdev->no_d3cold = true;
 366
 367         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 368                 xhci_pme_quirk(xhci);
 369
 370         return xhci_suspend(xhci, do_wakeup);
 371 }
 372
 373 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 374 {
 375         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 376         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 377         int                     retval = 0;
 378
 379         /* The BIOS on systems with the Intel Panther Point chipset may or may
 380          * not support xHCI natively.  That means that during system resume, it
 381          * may switch the ports back to EHCI so that users can use their
 382          * keyboard to select a kernel from GRUB after resume from hibernate.
 383          *
 384          * The BIOS is supposed to remember whether the OS had xHCI ports
 385          * enabled before resume, and switch the ports back to xHCI when the
 386          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 387          * writers.
 388          *
 389          * Unconditionally switch the ports back to xHCI after a system resume.
 390          * It should not matter whether the EHCI or xHCI controller is
 391          * resumed first. It's enough to do the switchover in xHCI because
 392          * USB core won't notice anything as the hub driver doesn't start
 393          * running again until after all the devices (including both EHCI and
 394          * xHCI host controllers) have been resumed.
 395          */
 396
 397         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 398                 usb_enable_intel_xhci_ports(pdev);
 399
 400         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 401                 xhci_pme_quirk(xhci);
 402
 403         retval = xhci_resume(xhci, hibernated);
 404         return retval;
 405 }
 406 #endif /* CONFIG_PM */
 407
 408 static const struct hc_driver xhci_pci_hc_driver = {
 409         .description =          hcd_name,
 410         .product_desc =         "xHCI Host Controller",
 411         .hcd_priv_size =        sizeof(struct xhci_hcd *),
 412
 413         /*
 414          * generic hardware linkage
 415          */
 416         .irq =                  xhci_irq,
 417         .flags =                HCD_MEMORY | HCD_USB3 | HCD_SHARED,
 418
 419         /*
 420          * basic lifecycle operations
 421          */
 422         .reset =                xhci_pci_setup,
 423         .start =                xhci_run,
 424 #ifdef CONFIG_PM
 425         .pci_suspend =          xhci_pci_suspend,
 426         .pci_resume =           xhci_pci_resume,
 427 #endif
 428         .stop =                 xhci_stop,
 429         .shutdown =             xhci_shutdown,
 430
 431         /*
 432          * managing i/o requests and associated device resources
 433          */
 434         .urb_enqueue =          xhci_urb_enqueue,
 435         .urb_dequeue =          xhci_urb_dequeue,
 436         .alloc_dev =            xhci_alloc_dev,
 437         .free_dev =             xhci_free_dev,
 438         .alloc_streams =        xhci_alloc_streams,
 439         .free_streams =         xhci_free_streams,
 440         .add_endpoint =         xhci_add_endpoint,
 441         .drop_endpoint =        xhci_drop_endpoint,
 442         .endpoint_reset =       xhci_endpoint_reset,
 443         .check_bandwidth =      xhci_check_bandwidth,
 444         .reset_bandwidth =      xhci_reset_bandwidth,
 445         .address_device =       xhci_address_device,
 446         .enable_device =        xhci_enable_device,
 447         .update_hub_device =    xhci_update_hub_device,
 448         .reset_device =         xhci_discover_or_reset_device,
 449
 450         /*
 451          * scheduling support
 452          */
 453         .get_frame_number =     xhci_get_frame,
 454
 455         /* Root hub support */
 456         .hub_control =          xhci_hub_control,
 457         .hub_status_data =      xhci_hub_status_data,
 458         .bus_suspend =          xhci_bus_suspend,
 459         .bus_resume =           xhci_bus_resume,
 460         /*
 461          * call back when device connected and addressed
 462          */
 463         .update_device =        xhci_update_device,
 464         .set_usb2_hw_lpm =      xhci_set_usb2_hardware_lpm,
 465         .enable_usb3_lpm_timeout =      xhci_enable_usb3_lpm_timeout,
 466         .disable_usb3_lpm_timeout =     xhci_disable_usb3_lpm_timeout,
 467         .find_raw_port_number = xhci_find_raw_port_number,
 468 };
 469
 470 /*-------------------------------------------------------------------------*/
 471
 472 /* PCI driver selection metadata; PCI hotplugging uses this */
 473 static const struct pci_device_id pci_ids[] = { {
 474         /* handle any USB 3.0 xHCI controller */
 475         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 476         .driver_data =  (unsigned long) &xhci_pci_hc_driver,
 477         },
 478         { /* end: all zeroes */ }
 479 };
 480 MODULE_DEVICE_TABLE(pci, pci_ids);
 481
 482 /* pci driver glue; this is a "new style" PCI driver module */
 483 static struct pci_driver xhci_pci_driver = {
 484         .name =         (char *) hcd_name,
 485         .id_table =     pci_ids,
 486
 487         .probe =        xhci_pci_probe,
 488         .remove =       xhci_pci_remove,
 489         /* suspend and resume implemented later */
 490
 491         .shutdown =     usb_hcd_pci_shutdown,
 492 #ifdef CONFIG_PM
 493         .driver = {
 494                 .pm = &usb_hcd_pci_pm_ops
 495         },
 496 #endif
 497 };
 498
 499 int __init xhci_register_pci(void)
 500 {
 501         return pci_register_driver(&xhci_pci_driver);
 502 }
 503
 504 void xhci_unregister_pci(void)
 505 {
 506         pci_unregister_driver(&xhci_pci_driver);
 507 }