1 // SPDX-License-Identifier: GPL-2.0+
3 * USB HOST XHCI Controller stack
5 * Based on xHCI host controller driver in linux-kernel
8 * Copyright (C) 2008 Intel Corp.
11 * Copyright (C) 2013 Samsung Electronics Co.Ltd
12 * Authors: Vivek Gautam <gautam.vivek@samsung.com>
13 * Vikas Sajjan <vikas.sajjan@samsung.com>
20 #include <asm/byteorder.h>
23 #include <asm/cache.h>
24 #include <linux/bug.h>
25 #include <linux/errno.h>
29 #define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
31 * flushes the address passed till the length
33 * @param addr pointer to memory region to be flushed
34 * @param len the length of the cache line to be flushed
37 void xhci_flush_cache(uintptr_t addr, u32 len)
39 BUG_ON((void *)addr == NULL || len == 0);
41 flush_dcache_range(addr & ~(CACHELINE_SIZE - 1),
42 ALIGN(addr + len, CACHELINE_SIZE));
46 * invalidates the address passed till the length
48 * @param addr pointer to memory region to be invalidates
49 * @param len the length of the cache line to be invalidated
52 void xhci_inval_cache(uintptr_t addr, u32 len)
54 BUG_ON((void *)addr == NULL || len == 0);
56 invalidate_dcache_range(addr & ~(CACHELINE_SIZE - 1),
57 ALIGN(addr + len, CACHELINE_SIZE));
62 * frees the "segment" pointer passed
64 * @param ptr pointer to "segement" to be freed
67 static void xhci_segment_free(struct xhci_segment *seg)
76 * frees the "ring" pointer passed
78 * @param ptr pointer to "ring" to be freed
81 static void xhci_ring_free(struct xhci_ring *ring)
83 struct xhci_segment *seg;
84 struct xhci_segment *first_seg;
88 first_seg = ring->first_seg;
89 seg = first_seg->next;
90 while (seg != first_seg) {
91 struct xhci_segment *next = seg->next;
92 xhci_segment_free(seg);
95 xhci_segment_free(first_seg);
101 * Free the scratchpad buffer array and scratchpad buffers
103 * @ctrl host controller data structure
106 static void xhci_scratchpad_free(struct xhci_ctrl *ctrl)
108 if (!ctrl->scratchpad)
111 ctrl->dcbaa->dev_context_ptrs[0] = 0;
113 free((void *)(uintptr_t)ctrl->scratchpad->sp_array[0]);
114 free(ctrl->scratchpad->sp_array);
115 free(ctrl->scratchpad);
116 ctrl->scratchpad = NULL;
120 * frees the "xhci_container_ctx" pointer passed
122 * @param ptr pointer to "xhci_container_ctx" to be freed
125 static void xhci_free_container_ctx(struct xhci_container_ctx *ctx)
132 * frees the virtual devices for "xhci_ctrl" pointer passed
134 * @param ptr pointer to "xhci_ctrl" whose virtual devices are to be freed
137 static void xhci_free_virt_devices(struct xhci_ctrl *ctrl)
141 struct xhci_virt_device *virt_dev;
144 * refactored here to loop through all virt_dev
145 * Slot ID 0 is reserved
147 for (slot_id = 0; slot_id < MAX_HC_SLOTS; slot_id++) {
148 virt_dev = ctrl->devs[slot_id];
152 ctrl->dcbaa->dev_context_ptrs[slot_id] = 0;
154 for (i = 0; i < 31; ++i)
155 if (virt_dev->eps[i].ring)
156 xhci_ring_free(virt_dev->eps[i].ring);
158 if (virt_dev->in_ctx)
159 xhci_free_container_ctx(virt_dev->in_ctx);
160 if (virt_dev->out_ctx)
161 xhci_free_container_ctx(virt_dev->out_ctx);
164 /* make sure we are pointing to NULL */
165 ctrl->devs[slot_id] = NULL;
170 * frees all the memory allocated
172 * @param ptr pointer to "xhci_ctrl" to be cleaned up
175 void xhci_cleanup(struct xhci_ctrl *ctrl)
177 xhci_ring_free(ctrl->event_ring);
178 xhci_ring_free(ctrl->cmd_ring);
179 xhci_scratchpad_free(ctrl);
180 xhci_free_virt_devices(ctrl);
181 free(ctrl->erst.entries);
183 memset(ctrl, '\0', sizeof(struct xhci_ctrl));
187 * Malloc the aligned memory
189 * @param size size of memory to be allocated
190 * @return allocates the memory and returns the aligned pointer
192 static void *xhci_malloc(unsigned int size)
195 size_t cacheline_size = max(XHCI_ALIGNMENT, CACHELINE_SIZE);
197 ptr = memalign(cacheline_size, ALIGN(size, cacheline_size));
199 memset(ptr, '\0', size);
201 xhci_flush_cache((uintptr_t)ptr, size);
207 * Make the prev segment point to the next segment.
208 * Change the last TRB in the prev segment to be a Link TRB which points to the
209 * address of the next segment. The caller needs to set any Link TRB
210 * related flags, such as End TRB, Toggle Cycle, and no snoop.
212 * @param prev pointer to the previous segment
213 * @param next pointer to the next segment
214 * @param link_trbs flag to indicate whether to link the trbs or NOT
217 static void xhci_link_segments(struct xhci_segment *prev,
218 struct xhci_segment *next, bool link_trbs)
227 val_64 = (uintptr_t)next->trbs;
228 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = val_64;
231 * Set the last TRB in the segment to
232 * have a TRB type ID of Link TRB
234 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
235 val &= ~TRB_TYPE_BITMASK;
236 val |= (TRB_LINK << TRB_TYPE_SHIFT);
238 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
243 * Initialises the Ring's enqueue,dequeue,enq_seg pointers
245 * @param ring pointer to the RING to be intialised
248 static void xhci_initialize_ring_info(struct xhci_ring *ring)
251 * The ring is empty, so the enqueue pointer == dequeue pointer
253 ring->enqueue = ring->first_seg->trbs;
254 ring->enq_seg = ring->first_seg;
255 ring->dequeue = ring->enqueue;
256 ring->deq_seg = ring->first_seg;
259 * The ring is initialized to 0. The producer must write 1 to the
260 * cycle bit to handover ownership of the TRB, so PCS = 1.
261 * The consumer must compare CCS to the cycle bit to
262 * check ownership, so CCS = 1.
264 ring->cycle_state = 1;
268 * Allocates a generic ring segment from the ring pool, sets the dma address,
269 * initializes the segment to zero, and sets the private next pointer to NULL.
271 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
274 * @return pointer to the newly allocated SEGMENT
276 static struct xhci_segment *xhci_segment_alloc(void)
278 struct xhci_segment *seg;
280 seg = (struct xhci_segment *)malloc(sizeof(struct xhci_segment));
283 seg->trbs = (union xhci_trb *)xhci_malloc(SEGMENT_SIZE);
291 * Create a new ring with zero or more segments.
292 * TODO: current code only uses one-time-allocated single-segment rings
293 * of 1KB anyway, so we might as well get rid of all the segment and
294 * linking code (and maybe increase the size a bit, e.g. 4KB).
297 * Link each segment together into a ring.
298 * Set the end flag and the cycle toggle bit on the last segment.
299 * See section 4.9.2 and figures 15 and 16 of XHCI spec rev1.0.
301 * @param num_segs number of segments in the ring
302 * @param link_trbs flag to indicate whether to link the trbs or NOT
303 * @return pointer to the newly created RING
305 struct xhci_ring *xhci_ring_alloc(unsigned int num_segs, bool link_trbs)
307 struct xhci_ring *ring;
308 struct xhci_segment *prev;
310 ring = (struct xhci_ring *)malloc(sizeof(struct xhci_ring));
316 ring->first_seg = xhci_segment_alloc();
317 BUG_ON(!ring->first_seg);
321 prev = ring->first_seg;
322 while (num_segs > 0) {
323 struct xhci_segment *next;
325 next = xhci_segment_alloc();
328 xhci_link_segments(prev, next, link_trbs);
333 xhci_link_segments(prev, ring->first_seg, link_trbs);
335 /* See section 4.9.2.1 and 6.4.4.1 */
336 prev->trbs[TRBS_PER_SEGMENT-1].link.control |=
337 cpu_to_le32(LINK_TOGGLE);
339 xhci_initialize_ring_info(ring);
345 * Set up the scratchpad buffer array and scratchpad buffers
347 * @ctrl host controller data structure
348 * @return -ENOMEM if buffer allocation fails, 0 on success
350 static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl)
352 struct xhci_hccr *hccr = ctrl->hccr;
353 struct xhci_hcor *hcor = ctrl->hcor;
354 struct xhci_scratchpad *scratchpad;
360 num_sp = HCS_MAX_SCRATCHPAD(xhci_readl(&hccr->cr_hcsparams2));
364 scratchpad = malloc(sizeof(*scratchpad));
367 ctrl->scratchpad = scratchpad;
369 scratchpad->sp_array = xhci_malloc(num_sp * sizeof(u64));
370 if (!scratchpad->sp_array)
372 ctrl->dcbaa->dev_context_ptrs[0] =
373 cpu_to_le64((uintptr_t)scratchpad->sp_array);
375 xhci_flush_cache((uintptr_t)&ctrl->dcbaa->dev_context_ptrs[0],
376 sizeof(ctrl->dcbaa->dev_context_ptrs[0]));
378 page_size = xhci_readl(&hcor->or_pagesize) & 0xffff;
379 for (i = 0; i < 16; i++) {
380 if ((0x1 & page_size) != 0)
382 page_size = page_size >> 1;
386 page_size = 1 << (i + 12);
387 buf = memalign(page_size, num_sp * page_size);
390 memset(buf, '\0', num_sp * page_size);
391 xhci_flush_cache((uintptr_t)buf, num_sp * page_size);
393 for (i = 0; i < num_sp; i++) {
394 uintptr_t ptr = (uintptr_t)buf + i * page_size;
395 scratchpad->sp_array[i] = cpu_to_le64(ptr);
401 free(scratchpad->sp_array);
405 ctrl->scratchpad = NULL;
412 * Allocates the Container context
414 * @param ctrl Host controller data structure
415 * @param type type of XHCI Container Context
416 * @return NULL if failed else pointer to the context on success
418 static struct xhci_container_ctx
419 *xhci_alloc_container_ctx(struct xhci_ctrl *ctrl, int type)
421 struct xhci_container_ctx *ctx;
423 ctx = (struct xhci_container_ctx *)
424 malloc(sizeof(struct xhci_container_ctx));
427 BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
429 ctx->size = (MAX_EP_CTX_NUM + 1) *
430 CTX_SIZE(readl(&ctrl->hccr->cr_hccparams));
431 if (type == XHCI_CTX_TYPE_INPUT)
432 ctx->size += CTX_SIZE(readl(&ctrl->hccr->cr_hccparams));
434 ctx->bytes = (u8 *)xhci_malloc(ctx->size);
440 * Allocating virtual device
442 * @param udev pointer to USB deivce structure
443 * @return 0 on success else -1 on failure
445 int xhci_alloc_virt_device(struct xhci_ctrl *ctrl, unsigned int slot_id)
448 struct xhci_virt_device *virt_dev;
450 /* Slot ID 0 is reserved */
451 if (ctrl->devs[slot_id]) {
452 printf("Virt dev for slot[%d] already allocated\n", slot_id);
456 ctrl->devs[slot_id] = (struct xhci_virt_device *)
457 malloc(sizeof(struct xhci_virt_device));
459 if (!ctrl->devs[slot_id]) {
460 puts("Failed to allocate virtual device\n");
464 memset(ctrl->devs[slot_id], 0, sizeof(struct xhci_virt_device));
465 virt_dev = ctrl->devs[slot_id];
467 /* Allocate the (output) device context that will be used in the HC. */
468 virt_dev->out_ctx = xhci_alloc_container_ctx(ctrl,
469 XHCI_CTX_TYPE_DEVICE);
470 if (!virt_dev->out_ctx) {
471 puts("Failed to allocate out context for virt dev\n");
475 /* Allocate the (input) device context for address device command */
476 virt_dev->in_ctx = xhci_alloc_container_ctx(ctrl,
477 XHCI_CTX_TYPE_INPUT);
478 if (!virt_dev->in_ctx) {
479 puts("Failed to allocate in context for virt dev\n");
483 /* Allocate endpoint 0 ring */
484 virt_dev->eps[0].ring = xhci_ring_alloc(1, true);
486 byte_64 = (uintptr_t)(virt_dev->out_ctx->bytes);
488 /* Point to output device context in dcbaa. */
489 ctrl->dcbaa->dev_context_ptrs[slot_id] = byte_64;
491 xhci_flush_cache((uintptr_t)&ctrl->dcbaa->dev_context_ptrs[slot_id],
497 * Allocates the necessary data structures
498 * for XHCI host controller
500 * @param ctrl Host controller data structure
501 * @param hccr pointer to HOST Controller Control Registers
502 * @param hcor pointer to HOST Controller Operational Registers
503 * @return 0 if successful else -1 on failure
505 int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr *hccr,
506 struct xhci_hcor *hcor)
513 struct xhci_segment *seg;
515 /* DCBAA initialization */
516 ctrl->dcbaa = (struct xhci_device_context_array *)
517 xhci_malloc(sizeof(struct xhci_device_context_array));
518 if (ctrl->dcbaa == NULL) {
519 puts("unable to allocate DCBA\n");
523 val_64 = (uintptr_t)ctrl->dcbaa;
524 /* Set the pointer in DCBAA register */
525 xhci_writeq(&hcor->or_dcbaap, val_64);
527 /* Command ring control pointer register initialization */
528 ctrl->cmd_ring = xhci_ring_alloc(1, true);
530 /* Set the address in the Command Ring Control register */
531 trb_64 = (uintptr_t)ctrl->cmd_ring->first_seg->trbs;
532 val_64 = xhci_readq(&hcor->or_crcr);
533 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
534 (trb_64 & (u64) ~CMD_RING_RSVD_BITS) |
535 ctrl->cmd_ring->cycle_state;
536 xhci_writeq(&hcor->or_crcr, val_64);
538 /* write the address of db register */
539 val = xhci_readl(&hccr->cr_dboff);
541 ctrl->dba = (struct xhci_doorbell_array *)((char *)hccr + val);
543 /* write the address of runtime register */
544 val = xhci_readl(&hccr->cr_rtsoff);
546 ctrl->run_regs = (struct xhci_run_regs *)((char *)hccr + val);
548 /* writting the address of ir_set structure */
549 ctrl->ir_set = &ctrl->run_regs->ir_set[0];
551 /* Event ring does not maintain link TRB */
552 ctrl->event_ring = xhci_ring_alloc(ERST_NUM_SEGS, false);
553 ctrl->erst.entries = (struct xhci_erst_entry *)
554 xhci_malloc(sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS);
556 ctrl->erst.num_entries = ERST_NUM_SEGS;
558 for (val = 0, seg = ctrl->event_ring->first_seg;
562 trb_64 = (uintptr_t)seg->trbs;
563 struct xhci_erst_entry *entry = &ctrl->erst.entries[val];
564 xhci_writeq(&entry->seg_addr, trb_64);
565 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
569 xhci_flush_cache((uintptr_t)ctrl->erst.entries,
570 ERST_NUM_SEGS * sizeof(struct xhci_erst_entry));
572 deq = (unsigned long)ctrl->event_ring->dequeue;
574 /* Update HC event ring dequeue pointer */
575 xhci_writeq(&ctrl->ir_set->erst_dequeue,
576 (u64)deq & (u64)~ERST_PTR_MASK);
578 /* set ERST count with the number of entries in the segment table */
579 val = xhci_readl(&ctrl->ir_set->erst_size);
580 val &= ERST_SIZE_MASK;
581 val |= ERST_NUM_SEGS;
582 xhci_writel(&ctrl->ir_set->erst_size, val);
584 /* this is the event ring segment table pointer */
585 val_64 = xhci_readq(&ctrl->ir_set->erst_base);
586 val_64 &= ERST_PTR_MASK;
587 val_64 |= ((uintptr_t)(ctrl->erst.entries) & ~ERST_PTR_MASK);
589 xhci_writeq(&ctrl->ir_set->erst_base, val_64);
591 /* set up the scratchpad buffer array and scratchpad buffers */
592 xhci_scratchpad_alloc(ctrl);
594 /* initializing the virtual devices to NULL */
595 for (i = 0; i < MAX_HC_SLOTS; ++i)
596 ctrl->devs[i] = NULL;
599 * Just Zero'ing this register completely,
600 * or some spurious Device Notification Events
601 * might screw things here.
603 xhci_writel(&hcor->or_dnctrl, 0x0);
609 * Give the input control context for the passed container context
611 * @param ctx pointer to the context
612 * @return pointer to the Input control context data
614 struct xhci_input_control_ctx
615 *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx)
617 BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
618 return (struct xhci_input_control_ctx *)ctx->bytes;
622 * Give the slot context for the passed container context
624 * @param ctrl Host controller data structure
625 * @param ctx pointer to the context
626 * @return pointer to the slot control context data
628 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_ctrl *ctrl,
629 struct xhci_container_ctx *ctx)
631 if (ctx->type == XHCI_CTX_TYPE_DEVICE)
632 return (struct xhci_slot_ctx *)ctx->bytes;
634 return (struct xhci_slot_ctx *)
635 (ctx->bytes + CTX_SIZE(readl(&ctrl->hccr->cr_hccparams)));
639 * Gets the EP context from based on the ep_index
641 * @param ctrl Host controller data structure
642 * @param ctx context container
643 * @param ep_index index of the endpoint
644 * @return pointer to the End point context
646 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_ctrl *ctrl,
647 struct xhci_container_ctx *ctx,
648 unsigned int ep_index)
650 /* increment ep index by offset of start of ep ctx array */
652 if (ctx->type == XHCI_CTX_TYPE_INPUT)
655 return (struct xhci_ep_ctx *)
657 (ep_index * CTX_SIZE(readl(&ctrl->hccr->cr_hccparams))));
661 * Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
662 * Useful when you want to change one particular aspect of the endpoint
663 * and then issue a configure endpoint command.
665 * @param ctrl Host controller data structure
666 * @param in_ctx contains the input context
667 * @param out_ctx contains the input context
668 * @param ep_index index of the end point
671 void xhci_endpoint_copy(struct xhci_ctrl *ctrl,
672 struct xhci_container_ctx *in_ctx,
673 struct xhci_container_ctx *out_ctx,
674 unsigned int ep_index)
676 struct xhci_ep_ctx *out_ep_ctx;
677 struct xhci_ep_ctx *in_ep_ctx;
679 out_ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index);
680 in_ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
682 in_ep_ctx->ep_info = out_ep_ctx->ep_info;
683 in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
684 in_ep_ctx->deq = out_ep_ctx->deq;
685 in_ep_ctx->tx_info = out_ep_ctx->tx_info;
689 * Copy output xhci_slot_ctx to the input xhci_slot_ctx.
690 * Useful when you want to change one particular aspect of the endpoint
691 * and then issue a configure endpoint command.
692 * Only the context entries field matters, but
693 * we'll copy the whole thing anyway.
695 * @param ctrl Host controller data structure
696 * @param in_ctx contains the inpout context
697 * @param out_ctx contains the inpout context
700 void xhci_slot_copy(struct xhci_ctrl *ctrl, struct xhci_container_ctx *in_ctx,
701 struct xhci_container_ctx *out_ctx)
703 struct xhci_slot_ctx *in_slot_ctx;
704 struct xhci_slot_ctx *out_slot_ctx;
706 in_slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
707 out_slot_ctx = xhci_get_slot_ctx(ctrl, out_ctx);
709 in_slot_ctx->dev_info = out_slot_ctx->dev_info;
710 in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
711 in_slot_ctx->tt_info = out_slot_ctx->tt_info;
712 in_slot_ctx->dev_state = out_slot_ctx->dev_state;
716 * Setup an xHCI virtual device for a Set Address command
718 * @param udev pointer to the Device Data Structure
719 * @return returns negative value on failure else 0 on success
721 void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl,
722 struct usb_device *udev, int hop_portnr)
724 struct xhci_virt_device *virt_dev;
725 struct xhci_ep_ctx *ep0_ctx;
726 struct xhci_slot_ctx *slot_ctx;
729 int slot_id = udev->slot_id;
730 int speed = udev->speed;
732 #if CONFIG_IS_ENABLED(DM_USB)
733 struct usb_device *dev = udev;
734 struct usb_hub_device *hub;
737 virt_dev = ctrl->devs[slot_id];
741 /* Extract the EP0 and Slot Ctrl */
742 ep0_ctx = xhci_get_ep_ctx(ctrl, virt_dev->in_ctx, 0);
743 slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->in_ctx);
745 /* Only the control endpoint is valid - one endpoint context */
746 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
748 #if CONFIG_IS_ENABLED(DM_USB)
749 /* Calculate the route string for this device */
750 port_num = dev->portnr;
751 while (!usb_hub_is_root_hub(dev->dev)) {
752 hub = dev_get_uclass_priv(dev->dev);
754 * Each hub in the topology is expected to have no more than
755 * 15 ports in order for the route string of a device to be
756 * unique. SuperSpeed hubs are restricted to only having 15
757 * ports, but FS/LS/HS hubs are not. The xHCI specification
758 * says that if the port number the device is greater than 15,
759 * that portion of the route string shall be set to 15.
763 route |= port_num << (hub->hub_depth * 4);
764 dev = dev_get_parent_priv(dev->dev);
765 port_num = dev->portnr;
766 dev = dev_get_parent_priv(dev->dev->parent);
769 debug("route string %x\n", route);
771 slot_ctx->dev_info |= route;
774 case USB_SPEED_SUPER:
775 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
778 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
781 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
784 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
787 /* Speed was set earlier, this shouldn't happen. */
791 #if CONFIG_IS_ENABLED(DM_USB)
792 /* Set up TT fields to support FS/LS devices */
793 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) {
794 struct udevice *parent = udev->dev;
798 port_num = dev->portnr;
799 dev = dev_get_parent_priv(parent);
800 if (usb_hub_is_root_hub(dev->dev))
802 parent = dev->dev->parent;
803 } while (dev->speed != USB_SPEED_HIGH);
805 if (!usb_hub_is_root_hub(dev->dev)) {
806 hub = dev_get_uclass_priv(dev->dev);
808 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
809 slot_ctx->tt_info |= cpu_to_le32(TT_PORT(port_num));
810 slot_ctx->tt_info |= cpu_to_le32(TT_SLOT(dev->slot_id));
815 port_num = hop_portnr;
816 debug("port_num = %d\n", port_num);
818 slot_ctx->dev_info2 |=
819 cpu_to_le32(((port_num & ROOT_HUB_PORT_MASK) <<
820 ROOT_HUB_PORT_SHIFT));
822 /* Step 4 - ring already allocated */
824 ep0_ctx->ep_info2 = cpu_to_le32(CTRL_EP << EP_TYPE_SHIFT);
825 debug("SPEED = %d\n", speed);
828 case USB_SPEED_SUPER:
829 ep0_ctx->ep_info2 |= cpu_to_le32(((512 & MAX_PACKET_MASK) <<
831 debug("Setting Packet size = 512bytes\n");
834 /* USB core guesses at a 64-byte max packet first for FS devices */
836 ep0_ctx->ep_info2 |= cpu_to_le32(((64 & MAX_PACKET_MASK) <<
838 debug("Setting Packet size = 64bytes\n");
841 ep0_ctx->ep_info2 |= cpu_to_le32(((8 & MAX_PACKET_MASK) <<
843 debug("Setting Packet size = 8bytes\n");
850 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
852 cpu_to_le32(((0 & MAX_BURST_MASK) << MAX_BURST_SHIFT) |
853 ((3 & ERROR_COUNT_MASK) << ERROR_COUNT_SHIFT));
855 trb_64 = (uintptr_t)virt_dev->eps[0].ring->first_seg->trbs;
856 ep0_ctx->deq = cpu_to_le64(trb_64 | virt_dev->eps[0].ring->cycle_state);
860 * software shall set 'Average TRB Length' to 8 for control endpoints.
862 ep0_ctx->tx_info = cpu_to_le32(EP_AVG_TRB_LENGTH(8));
864 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
866 xhci_flush_cache((uintptr_t)ep0_ctx, sizeof(struct xhci_ep_ctx));
867 xhci_flush_cache((uintptr_t)slot_ctx, sizeof(struct xhci_slot_ctx));