1 // SPDX-License-Identifier: GPL-2.0+
3 * USB HOST XHCI Controller stack
5 * Based on xHCI host controller driver in linux-kernel
8 * Copyright (C) 2008 Intel Corp.
11 * Copyright (C) 2013 Samsung Electronics Co.Ltd
12 * Authors: Vivek Gautam <gautam.vivek@samsung.com>
13 * Vikas Sajjan <vikas.sajjan@samsung.com>
18 #include <asm/byteorder.h>
21 #include <asm/cache.h>
22 #include <linux/errno.h>
26 #define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
28 * flushes the address passed till the length
30 * @param addr pointer to memory region to be flushed
31 * @param len the length of the cache line to be flushed
34 void xhci_flush_cache(uintptr_t addr, u32 len)
36 BUG_ON((void *)addr == NULL || len == 0);
38 flush_dcache_range(addr & ~(CACHELINE_SIZE - 1),
39 ALIGN(addr + len, CACHELINE_SIZE));
43 * invalidates the address passed till the length
45 * @param addr pointer to memory region to be invalidates
46 * @param len the length of the cache line to be invalidated
49 void xhci_inval_cache(uintptr_t addr, u32 len)
51 BUG_ON((void *)addr == NULL || len == 0);
53 invalidate_dcache_range(addr & ~(CACHELINE_SIZE - 1),
54 ALIGN(addr + len, CACHELINE_SIZE));
59 * frees the "segment" pointer passed
61 * @param ptr pointer to "segement" to be freed
64 static void xhci_segment_free(struct xhci_segment *seg)
73 * frees the "ring" pointer passed
75 * @param ptr pointer to "ring" to be freed
78 static void xhci_ring_free(struct xhci_ring *ring)
80 struct xhci_segment *seg;
81 struct xhci_segment *first_seg;
85 first_seg = ring->first_seg;
86 seg = first_seg->next;
87 while (seg != first_seg) {
88 struct xhci_segment *next = seg->next;
89 xhci_segment_free(seg);
92 xhci_segment_free(first_seg);
98 * Free the scratchpad buffer array and scratchpad buffers
100 * @ctrl host controller data structure
103 static void xhci_scratchpad_free(struct xhci_ctrl *ctrl)
105 if (!ctrl->scratchpad)
108 ctrl->dcbaa->dev_context_ptrs[0] = 0;
110 free((void *)(uintptr_t)ctrl->scratchpad->sp_array[0]);
111 free(ctrl->scratchpad->sp_array);
112 free(ctrl->scratchpad);
113 ctrl->scratchpad = NULL;
117 * frees the "xhci_container_ctx" pointer passed
119 * @param ptr pointer to "xhci_container_ctx" to be freed
122 static void xhci_free_container_ctx(struct xhci_container_ctx *ctx)
129 * frees the virtual devices for "xhci_ctrl" pointer passed
131 * @param ptr pointer to "xhci_ctrl" whose virtual devices are to be freed
134 static void xhci_free_virt_devices(struct xhci_ctrl *ctrl)
138 struct xhci_virt_device *virt_dev;
141 * refactored here to loop through all virt_dev
142 * Slot ID 0 is reserved
144 for (slot_id = 0; slot_id < MAX_HC_SLOTS; slot_id++) {
145 virt_dev = ctrl->devs[slot_id];
149 ctrl->dcbaa->dev_context_ptrs[slot_id] = 0;
151 for (i = 0; i < 31; ++i)
152 if (virt_dev->eps[i].ring)
153 xhci_ring_free(virt_dev->eps[i].ring);
155 if (virt_dev->in_ctx)
156 xhci_free_container_ctx(virt_dev->in_ctx);
157 if (virt_dev->out_ctx)
158 xhci_free_container_ctx(virt_dev->out_ctx);
161 /* make sure we are pointing to NULL */
162 ctrl->devs[slot_id] = NULL;
167 * frees all the memory allocated
169 * @param ptr pointer to "xhci_ctrl" to be cleaned up
172 void xhci_cleanup(struct xhci_ctrl *ctrl)
174 xhci_ring_free(ctrl->event_ring);
175 xhci_ring_free(ctrl->cmd_ring);
176 xhci_scratchpad_free(ctrl);
177 xhci_free_virt_devices(ctrl);
178 free(ctrl->erst.entries);
180 memset(ctrl, '\0', sizeof(struct xhci_ctrl));
184 * Malloc the aligned memory
186 * @param size size of memory to be allocated
187 * @return allocates the memory and returns the aligned pointer
189 static void *xhci_malloc(unsigned int size)
192 size_t cacheline_size = max(XHCI_ALIGNMENT, CACHELINE_SIZE);
194 ptr = memalign(cacheline_size, ALIGN(size, cacheline_size));
196 memset(ptr, '\0', size);
198 xhci_flush_cache((uintptr_t)ptr, size);
204 * Make the prev segment point to the next segment.
205 * Change the last TRB in the prev segment to be a Link TRB which points to the
206 * address of the next segment. The caller needs to set any Link TRB
207 * related flags, such as End TRB, Toggle Cycle, and no snoop.
209 * @param prev pointer to the previous segment
210 * @param next pointer to the next segment
211 * @param link_trbs flag to indicate whether to link the trbs or NOT
214 static void xhci_link_segments(struct xhci_segment *prev,
215 struct xhci_segment *next, bool link_trbs)
224 val_64 = (uintptr_t)next->trbs;
225 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = val_64;
228 * Set the last TRB in the segment to
229 * have a TRB type ID of Link TRB
231 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
232 val &= ~TRB_TYPE_BITMASK;
233 val |= (TRB_LINK << TRB_TYPE_SHIFT);
235 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
240 * Initialises the Ring's enqueue,dequeue,enq_seg pointers
242 * @param ring pointer to the RING to be intialised
245 static void xhci_initialize_ring_info(struct xhci_ring *ring)
248 * The ring is empty, so the enqueue pointer == dequeue pointer
250 ring->enqueue = ring->first_seg->trbs;
251 ring->enq_seg = ring->first_seg;
252 ring->dequeue = ring->enqueue;
253 ring->deq_seg = ring->first_seg;
256 * The ring is initialized to 0. The producer must write 1 to the
257 * cycle bit to handover ownership of the TRB, so PCS = 1.
258 * The consumer must compare CCS to the cycle bit to
259 * check ownership, so CCS = 1.
261 ring->cycle_state = 1;
265 * Allocates a generic ring segment from the ring pool, sets the dma address,
266 * initializes the segment to zero, and sets the private next pointer to NULL.
268 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
271 * @return pointer to the newly allocated SEGMENT
273 static struct xhci_segment *xhci_segment_alloc(void)
275 struct xhci_segment *seg;
277 seg = (struct xhci_segment *)malloc(sizeof(struct xhci_segment));
280 seg->trbs = (union xhci_trb *)xhci_malloc(SEGMENT_SIZE);
288 * Create a new ring with zero or more segments.
289 * TODO: current code only uses one-time-allocated single-segment rings
290 * of 1KB anyway, so we might as well get rid of all the segment and
291 * linking code (and maybe increase the size a bit, e.g. 4KB).
294 * Link each segment together into a ring.
295 * Set the end flag and the cycle toggle bit on the last segment.
296 * See section 4.9.2 and figures 15 and 16 of XHCI spec rev1.0.
298 * @param num_segs number of segments in the ring
299 * @param link_trbs flag to indicate whether to link the trbs or NOT
300 * @return pointer to the newly created RING
302 struct xhci_ring *xhci_ring_alloc(unsigned int num_segs, bool link_trbs)
304 struct xhci_ring *ring;
305 struct xhci_segment *prev;
307 ring = (struct xhci_ring *)malloc(sizeof(struct xhci_ring));
313 ring->first_seg = xhci_segment_alloc();
314 BUG_ON(!ring->first_seg);
318 prev = ring->first_seg;
319 while (num_segs > 0) {
320 struct xhci_segment *next;
322 next = xhci_segment_alloc();
325 xhci_link_segments(prev, next, link_trbs);
330 xhci_link_segments(prev, ring->first_seg, link_trbs);
332 /* See section 4.9.2.1 and 6.4.4.1 */
333 prev->trbs[TRBS_PER_SEGMENT-1].link.control |=
334 cpu_to_le32(LINK_TOGGLE);
336 xhci_initialize_ring_info(ring);
342 * Set up the scratchpad buffer array and scratchpad buffers
344 * @ctrl host controller data structure
345 * @return -ENOMEM if buffer allocation fails, 0 on success
347 static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl)
349 struct xhci_hccr *hccr = ctrl->hccr;
350 struct xhci_hcor *hcor = ctrl->hcor;
351 struct xhci_scratchpad *scratchpad;
357 num_sp = HCS_MAX_SCRATCHPAD(xhci_readl(&hccr->cr_hcsparams2));
361 scratchpad = malloc(sizeof(*scratchpad));
364 ctrl->scratchpad = scratchpad;
366 scratchpad->sp_array = xhci_malloc(num_sp * sizeof(u64));
367 if (!scratchpad->sp_array)
369 ctrl->dcbaa->dev_context_ptrs[0] =
370 cpu_to_le64((uintptr_t)scratchpad->sp_array);
372 page_size = xhci_readl(&hcor->or_pagesize) & 0xffff;
373 for (i = 0; i < 16; i++) {
374 if ((0x1 & page_size) != 0)
376 page_size = page_size >> 1;
380 page_size = 1 << (i + 12);
381 buf = memalign(page_size, num_sp * page_size);
384 memset(buf, '\0', num_sp * page_size);
385 xhci_flush_cache((uintptr_t)buf, num_sp * page_size);
387 for (i = 0; i < num_sp; i++) {
388 uintptr_t ptr = (uintptr_t)buf + i * page_size;
389 scratchpad->sp_array[i] = cpu_to_le64(ptr);
395 free(scratchpad->sp_array);
399 ctrl->scratchpad = NULL;
406 * Allocates the Container context
408 * @param ctrl Host controller data structure
409 * @param type type of XHCI Container Context
410 * @return NULL if failed else pointer to the context on success
412 static struct xhci_container_ctx
413 *xhci_alloc_container_ctx(struct xhci_ctrl *ctrl, int type)
415 struct xhci_container_ctx *ctx;
417 ctx = (struct xhci_container_ctx *)
418 malloc(sizeof(struct xhci_container_ctx));
421 BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
423 ctx->size = (MAX_EP_CTX_NUM + 1) *
424 CTX_SIZE(readl(&ctrl->hccr->cr_hccparams));
425 if (type == XHCI_CTX_TYPE_INPUT)
426 ctx->size += CTX_SIZE(readl(&ctrl->hccr->cr_hccparams));
428 ctx->bytes = (u8 *)xhci_malloc(ctx->size);
434 * Allocating virtual device
436 * @param udev pointer to USB deivce structure
437 * @return 0 on success else -1 on failure
439 int xhci_alloc_virt_device(struct xhci_ctrl *ctrl, unsigned int slot_id)
442 struct xhci_virt_device *virt_dev;
444 /* Slot ID 0 is reserved */
445 if (ctrl->devs[slot_id]) {
446 printf("Virt dev for slot[%d] already allocated\n", slot_id);
450 ctrl->devs[slot_id] = (struct xhci_virt_device *)
451 malloc(sizeof(struct xhci_virt_device));
453 if (!ctrl->devs[slot_id]) {
454 puts("Failed to allocate virtual device\n");
458 memset(ctrl->devs[slot_id], 0, sizeof(struct xhci_virt_device));
459 virt_dev = ctrl->devs[slot_id];
461 /* Allocate the (output) device context that will be used in the HC. */
462 virt_dev->out_ctx = xhci_alloc_container_ctx(ctrl,
463 XHCI_CTX_TYPE_DEVICE);
464 if (!virt_dev->out_ctx) {
465 puts("Failed to allocate out context for virt dev\n");
469 /* Allocate the (input) device context for address device command */
470 virt_dev->in_ctx = xhci_alloc_container_ctx(ctrl,
471 XHCI_CTX_TYPE_INPUT);
472 if (!virt_dev->in_ctx) {
473 puts("Failed to allocate in context for virt dev\n");
477 /* Allocate endpoint 0 ring */
478 virt_dev->eps[0].ring = xhci_ring_alloc(1, true);
480 byte_64 = (uintptr_t)(virt_dev->out_ctx->bytes);
482 /* Point to output device context in dcbaa. */
483 ctrl->dcbaa->dev_context_ptrs[slot_id] = byte_64;
485 xhci_flush_cache((uintptr_t)&ctrl->dcbaa->dev_context_ptrs[slot_id],
491 * Allocates the necessary data structures
492 * for XHCI host controller
494 * @param ctrl Host controller data structure
495 * @param hccr pointer to HOST Controller Control Registers
496 * @param hcor pointer to HOST Controller Operational Registers
497 * @return 0 if successful else -1 on failure
499 int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr *hccr,
500 struct xhci_hcor *hcor)
507 struct xhci_segment *seg;
509 /* DCBAA initialization */
510 ctrl->dcbaa = (struct xhci_device_context_array *)
511 xhci_malloc(sizeof(struct xhci_device_context_array));
512 if (ctrl->dcbaa == NULL) {
513 puts("unable to allocate DCBA\n");
517 val_64 = (uintptr_t)ctrl->dcbaa;
518 /* Set the pointer in DCBAA register */
519 xhci_writeq(&hcor->or_dcbaap, val_64);
521 /* Command ring control pointer register initialization */
522 ctrl->cmd_ring = xhci_ring_alloc(1, true);
524 /* Set the address in the Command Ring Control register */
525 trb_64 = (uintptr_t)ctrl->cmd_ring->first_seg->trbs;
526 val_64 = xhci_readq(&hcor->or_crcr);
527 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
528 (trb_64 & (u64) ~CMD_RING_RSVD_BITS) |
529 ctrl->cmd_ring->cycle_state;
530 xhci_writeq(&hcor->or_crcr, val_64);
532 /* write the address of db register */
533 val = xhci_readl(&hccr->cr_dboff);
535 ctrl->dba = (struct xhci_doorbell_array *)((char *)hccr + val);
537 /* write the address of runtime register */
538 val = xhci_readl(&hccr->cr_rtsoff);
540 ctrl->run_regs = (struct xhci_run_regs *)((char *)hccr + val);
542 /* writting the address of ir_set structure */
543 ctrl->ir_set = &ctrl->run_regs->ir_set[0];
545 /* Event ring does not maintain link TRB */
546 ctrl->event_ring = xhci_ring_alloc(ERST_NUM_SEGS, false);
547 ctrl->erst.entries = (struct xhci_erst_entry *)
548 xhci_malloc(sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS);
550 ctrl->erst.num_entries = ERST_NUM_SEGS;
552 for (val = 0, seg = ctrl->event_ring->first_seg;
556 trb_64 = (uintptr_t)seg->trbs;
557 struct xhci_erst_entry *entry = &ctrl->erst.entries[val];
558 xhci_writeq(&entry->seg_addr, trb_64);
559 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
563 xhci_flush_cache((uintptr_t)ctrl->erst.entries,
564 ERST_NUM_SEGS * sizeof(struct xhci_erst_entry));
566 deq = (unsigned long)ctrl->event_ring->dequeue;
568 /* Update HC event ring dequeue pointer */
569 xhci_writeq(&ctrl->ir_set->erst_dequeue,
570 (u64)deq & (u64)~ERST_PTR_MASK);
572 /* set ERST count with the number of entries in the segment table */
573 val = xhci_readl(&ctrl->ir_set->erst_size);
574 val &= ERST_SIZE_MASK;
575 val |= ERST_NUM_SEGS;
576 xhci_writel(&ctrl->ir_set->erst_size, val);
578 /* this is the event ring segment table pointer */
579 val_64 = xhci_readq(&ctrl->ir_set->erst_base);
580 val_64 &= ERST_PTR_MASK;
581 val_64 |= ((uintptr_t)(ctrl->erst.entries) & ~ERST_PTR_MASK);
583 xhci_writeq(&ctrl->ir_set->erst_base, val_64);
585 /* set up the scratchpad buffer array and scratchpad buffers */
586 xhci_scratchpad_alloc(ctrl);
588 /* initializing the virtual devices to NULL */
589 for (i = 0; i < MAX_HC_SLOTS; ++i)
590 ctrl->devs[i] = NULL;
593 * Just Zero'ing this register completely,
594 * or some spurious Device Notification Events
595 * might screw things here.
597 xhci_writel(&hcor->or_dnctrl, 0x0);
603 * Give the input control context for the passed container context
605 * @param ctx pointer to the context
606 * @return pointer to the Input control context data
608 struct xhci_input_control_ctx
609 *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx)
611 BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
612 return (struct xhci_input_control_ctx *)ctx->bytes;
616 * Give the slot context for the passed container context
618 * @param ctrl Host controller data structure
619 * @param ctx pointer to the context
620 * @return pointer to the slot control context data
622 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_ctrl *ctrl,
623 struct xhci_container_ctx *ctx)
625 if (ctx->type == XHCI_CTX_TYPE_DEVICE)
626 return (struct xhci_slot_ctx *)ctx->bytes;
628 return (struct xhci_slot_ctx *)
629 (ctx->bytes + CTX_SIZE(readl(&ctrl->hccr->cr_hccparams)));
633 * Gets the EP context from based on the ep_index
635 * @param ctrl Host controller data structure
636 * @param ctx context container
637 * @param ep_index index of the endpoint
638 * @return pointer to the End point context
640 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_ctrl *ctrl,
641 struct xhci_container_ctx *ctx,
642 unsigned int ep_index)
644 /* increment ep index by offset of start of ep ctx array */
646 if (ctx->type == XHCI_CTX_TYPE_INPUT)
649 return (struct xhci_ep_ctx *)
651 (ep_index * CTX_SIZE(readl(&ctrl->hccr->cr_hccparams))));
655 * Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
656 * Useful when you want to change one particular aspect of the endpoint
657 * and then issue a configure endpoint command.
659 * @param ctrl Host controller data structure
660 * @param in_ctx contains the input context
661 * @param out_ctx contains the input context
662 * @param ep_index index of the end point
665 void xhci_endpoint_copy(struct xhci_ctrl *ctrl,
666 struct xhci_container_ctx *in_ctx,
667 struct xhci_container_ctx *out_ctx,
668 unsigned int ep_index)
670 struct xhci_ep_ctx *out_ep_ctx;
671 struct xhci_ep_ctx *in_ep_ctx;
673 out_ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index);
674 in_ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
676 in_ep_ctx->ep_info = out_ep_ctx->ep_info;
677 in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
678 in_ep_ctx->deq = out_ep_ctx->deq;
679 in_ep_ctx->tx_info = out_ep_ctx->tx_info;
683 * Copy output xhci_slot_ctx to the input xhci_slot_ctx.
684 * Useful when you want to change one particular aspect of the endpoint
685 * and then issue a configure endpoint command.
686 * Only the context entries field matters, but
687 * we'll copy the whole thing anyway.
689 * @param ctrl Host controller data structure
690 * @param in_ctx contains the inpout context
691 * @param out_ctx contains the inpout context
694 void xhci_slot_copy(struct xhci_ctrl *ctrl, struct xhci_container_ctx *in_ctx,
695 struct xhci_container_ctx *out_ctx)
697 struct xhci_slot_ctx *in_slot_ctx;
698 struct xhci_slot_ctx *out_slot_ctx;
700 in_slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
701 out_slot_ctx = xhci_get_slot_ctx(ctrl, out_ctx);
703 in_slot_ctx->dev_info = out_slot_ctx->dev_info;
704 in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
705 in_slot_ctx->tt_info = out_slot_ctx->tt_info;
706 in_slot_ctx->dev_state = out_slot_ctx->dev_state;
710 * Setup an xHCI virtual device for a Set Address command
712 * @param udev pointer to the Device Data Structure
713 * @return returns negative value on failure else 0 on success
715 void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl,
716 struct usb_device *udev, int hop_portnr)
718 struct xhci_virt_device *virt_dev;
719 struct xhci_ep_ctx *ep0_ctx;
720 struct xhci_slot_ctx *slot_ctx;
723 int slot_id = udev->slot_id;
724 int speed = udev->speed;
726 #if CONFIG_IS_ENABLED(DM_USB)
727 struct usb_device *dev = udev;
728 struct usb_hub_device *hub;
731 virt_dev = ctrl->devs[slot_id];
735 /* Extract the EP0 and Slot Ctrl */
736 ep0_ctx = xhci_get_ep_ctx(ctrl, virt_dev->in_ctx, 0);
737 slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->in_ctx);
739 /* Only the control endpoint is valid - one endpoint context */
740 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
742 #if CONFIG_IS_ENABLED(DM_USB)
743 /* Calculate the route string for this device */
744 port_num = dev->portnr;
745 while (!usb_hub_is_root_hub(dev->dev)) {
746 hub = dev_get_uclass_priv(dev->dev);
748 * Each hub in the topology is expected to have no more than
749 * 15 ports in order for the route string of a device to be
750 * unique. SuperSpeed hubs are restricted to only having 15
751 * ports, but FS/LS/HS hubs are not. The xHCI specification
752 * says that if the port number the device is greater than 15,
753 * that portion of the route string shall be set to 15.
757 route |= port_num << (hub->hub_depth * 4);
758 dev = dev_get_parent_priv(dev->dev);
759 port_num = dev->portnr;
760 dev = dev_get_parent_priv(dev->dev->parent);
763 debug("route string %x\n", route);
765 slot_ctx->dev_info |= route;
768 case USB_SPEED_SUPER:
769 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
772 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
775 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
778 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
781 /* Speed was set earlier, this shouldn't happen. */
785 #if CONFIG_IS_ENABLED(DM_USB)
786 /* Set up TT fields to support FS/LS devices */
787 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) {
788 struct udevice *parent = udev->dev;
792 port_num = dev->portnr;
793 dev = dev_get_parent_priv(parent);
794 if (usb_hub_is_root_hub(dev->dev))
796 parent = dev->dev->parent;
797 } while (dev->speed != USB_SPEED_HIGH);
799 if (!usb_hub_is_root_hub(dev->dev)) {
800 hub = dev_get_uclass_priv(dev->dev);
802 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
803 slot_ctx->tt_info |= cpu_to_le32(TT_PORT(port_num));
804 slot_ctx->tt_info |= cpu_to_le32(TT_SLOT(dev->slot_id));
809 port_num = hop_portnr;
810 debug("port_num = %d\n", port_num);
812 slot_ctx->dev_info2 |=
813 cpu_to_le32(((port_num & ROOT_HUB_PORT_MASK) <<
814 ROOT_HUB_PORT_SHIFT));
816 /* Step 4 - ring already allocated */
818 ep0_ctx->ep_info2 = cpu_to_le32(CTRL_EP << EP_TYPE_SHIFT);
819 debug("SPEED = %d\n", speed);
822 case USB_SPEED_SUPER:
823 ep0_ctx->ep_info2 |= cpu_to_le32(((512 & MAX_PACKET_MASK) <<
825 debug("Setting Packet size = 512bytes\n");
828 /* USB core guesses at a 64-byte max packet first for FS devices */
830 ep0_ctx->ep_info2 |= cpu_to_le32(((64 & MAX_PACKET_MASK) <<
832 debug("Setting Packet size = 64bytes\n");
835 ep0_ctx->ep_info2 |= cpu_to_le32(((8 & MAX_PACKET_MASK) <<
837 debug("Setting Packet size = 8bytes\n");
844 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
846 cpu_to_le32(((0 & MAX_BURST_MASK) << MAX_BURST_SHIFT) |
847 ((3 & ERROR_COUNT_MASK) << ERROR_COUNT_SHIFT));
849 trb_64 = (uintptr_t)virt_dev->eps[0].ring->first_seg->trbs;
850 ep0_ctx->deq = cpu_to_le64(trb_64 | virt_dev->eps[0].ring->cycle_state);
854 * software shall set 'Average TRB Length' to 8 for control endpoints.
856 ep0_ctx->tx_info = cpu_to_le32(EP_AVG_TRB_LENGTH(8));
858 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
860 xhci_flush_cache((uintptr_t)ep0_ctx, sizeof(struct xhci_ep_ctx));
861 xhci_flush_cache((uintptr_t)slot_ctx, sizeof(struct xhci_slot_ctx));