2 * Copyright 2015,2016 Freescale Semiconductor, Inc.
4 * FSL USB HOST xHCI Controller
6 * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/errno.h>
14 #include <linux/compat.h>
15 #include <linux/usb/xhci-fsl.h>
16 #include <linux/usb/dwc3.h>
18 #include <fsl_errata.h>
22 /* Declare global data pointer */
23 DECLARE_GLOBAL_DATA_PTR;
26 static struct fsl_xhci fsl_xhci;
27 unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR;
29 struct xhci_fsl_priv {
30 struct xhci_ctrl xhci;
36 __weak int __board_usb_init(int index, enum usb_init_type init)
41 static int erratum_a008751(void)
43 #if defined(CONFIG_TARGET_LS2080AQDS) || defined(CONFIG_TARGET_LS2080ARDB)
44 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
45 writel(SCFG_USB3PRM1CR_INIT, scfg + SCFG_USB3PRM1CR / 4);
51 static void fsl_apply_xhci_errata(void)
54 if (has_erratum_a008751()) {
55 ret = erratum_a008751();
57 puts("Failed to apply erratum a008751\n");
61 static void fsl_xhci_set_beat_burst_length(struct dwc3 *dwc3_reg)
63 clrsetbits_le32(&dwc3_reg->g_sbuscfg0, USB3_ENABLE_BEAT_BURST_MASK,
64 USB3_ENABLE_BEAT_BURST);
65 setbits_le32(&dwc3_reg->g_sbuscfg1, USB3_SET_BEAT_BURST_LIMIT);
68 static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
72 ret = dwc3_core_init(fsl_xhci->dwc3_reg);
74 debug("%s:failed to initialize core\n", __func__);
78 /* We are hard-coding DWC3 core to Host Mode */
79 dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
81 /* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */
82 dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT);
84 /* Change beat burst and outstanding pipelined transfers requests */
85 fsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg);
90 static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
93 * Currently fsl socs do not support PHY shutdown from
94 * sw. But this support may be added in future socs.
100 static int xhci_fsl_probe(struct udevice *dev)
102 struct xhci_fsl_priv *priv = dev_get_priv(dev);
103 struct xhci_hccr *hccr;
104 struct xhci_hcor *hcor;
109 * Get the base address for XHCI controller from the device node
111 priv->hcd_base = dev_get_addr(dev);
112 if (priv->hcd_base == FDT_ADDR_T_NONE) {
113 debug("Can't get the XHCI register base address\n");
116 priv->ctx.hcd = (struct xhci_hccr *)priv->hcd_base;
117 priv->ctx.dwc3_reg = (struct dwc3 *)((char *)(priv->hcd_base) +
120 fsl_apply_xhci_errata();
122 ret = fsl_xhci_core_init(&priv->ctx);
124 puts("Failed to initialize xhci\n");
128 hccr = (struct xhci_hccr *)(priv->ctx.hcd);
129 hcor = (struct xhci_hcor *)((uintptr_t) hccr
130 + HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
132 debug("xhci-fsl: init hccr %lx and hcor %lx hc_length %lx\n",
133 (uintptr_t)hccr, (uintptr_t)hcor,
134 (uintptr_t)HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
136 return xhci_register(dev, hccr, hcor);
139 static int xhci_fsl_remove(struct udevice *dev)
141 struct xhci_fsl_priv *priv = dev_get_priv(dev);
143 fsl_xhci_core_exit(&priv->ctx);
145 return xhci_deregister(dev);
148 static const struct udevice_id xhci_usb_ids[] = {
149 { .compatible = "fsl,layerscape-dwc3", },
153 U_BOOT_DRIVER(xhci_fsl) = {
156 .of_match = xhci_usb_ids,
157 .probe = xhci_fsl_probe,
158 .remove = xhci_fsl_remove,
159 .ops = &xhci_usb_ops,
160 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
161 .priv_auto_alloc_size = sizeof(struct xhci_fsl_priv),
162 .flags = DM_FLAG_ALLOC_PRIV_DMA,
165 int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
167 struct fsl_xhci *ctx = &fsl_xhci;
170 ctx->hcd = (struct xhci_hccr *)ctr_addr[index];
171 ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
173 ret = board_usb_init(index, USB_INIT_HOST);
175 puts("Failed to initialize board for USB\n");
179 fsl_apply_xhci_errata();
181 ret = fsl_xhci_core_init(ctx);
183 puts("Failed to initialize xhci\n");
187 *hccr = (struct xhci_hccr *)ctx->hcd;
188 *hcor = (struct xhci_hcor *)((uintptr_t) *hccr
189 + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
191 debug("fsl-xhci: init hccr %lx and hcor %lx hc_length %lx\n",
192 (uintptr_t)*hccr, (uintptr_t)*hcor,
193 (uintptr_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
198 void xhci_hcd_stop(int index)
200 struct fsl_xhci *ctx = &fsl_xhci;
202 fsl_xhci_core_exit(ctx);