1 // SPDX-License-Identifier: GPL-2.0+
4 * eInfochips Ltd. <www.einfochips.com>
5 * Written-by: Ajay Bhargav <contact@8051projects.net>
8 * Marvell Semiconductor <www.marvell.com>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/armada100.h>
16 #include <asm/arch/utmi-armada100.h>
18 static int utmi_phy_init(void)
20 struct armd1usb_phy_reg *phy_regs =
21 (struct armd1usb_phy_reg *)UTMI_PHY_BASE;
24 setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP);
26 setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP);
28 clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK);
29 setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER);
31 setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL);
35 while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
41 setbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
43 clrbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
46 setbits_le32(&phy_regs->utmi_tx, RCAL_START);
48 clrbits_le32(&phy_regs->utmi_tx, RCAL_START);
51 while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
60 * Initialize USB host controller's UTMI Physical interface
64 struct armd1mpmu_registers *mpmu_regs =
65 (struct armd1mpmu_registers *)ARMD1_MPMU_BASE;
67 struct armd1apmu_registers *apmu_regs =
68 (struct armd1apmu_registers *)ARMD1_APMU_BASE;
70 /* Turn on 26Mhz ref clock for UTMI PLL */
71 setbits_le32(&mpmu_regs->acgr, APB2_26M_EN | AP_26M);
74 writel(USB_SPH_AXICLK_EN, &apmu_regs->usbcrc);
75 writel(USB_SPH_AXICLK_EN | USB_SPH_AXI_RST, &apmu_regs->usbcrc);
77 /* Initialize UTMI transceiver */
78 return utmi_phy_init();