1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2007-2008, Juniper Networks, Inc.
4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
13 /* Section 2.2.3 - N_PORTS */
14 #define MAX_HC_PORTS 15
21 #define HC_LENGTH(p) (((p) >> 0) & 0x00ff)
22 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
23 uint32_t cr_hcsparams;
24 #define HCS_PPC(p) ((p) & (1 << 4))
25 #define HCS_INDICATOR(p) ((p) & (1 << 16)) /* Port indicators */
26 #define HCS_N_PORTS(p) (((p) >> 0) & 0xf)
27 uint32_t cr_hccparams;
28 uint8_t cr_hcsp_portrt[8];
29 } __attribute__ ((packed, aligned(4)));
33 #define CMD_PARK (1 << 11) /* enable "park" */
34 #define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */
35 #define CMD_LRESET (1 << 7) /* partial reset */
36 #define CMD_IAAD (1 << 6) /* "doorbell" interrupt */
37 #define CMD_ASE (1 << 5) /* async schedule enable */
38 #define CMD_PSE (1 << 4) /* periodic schedule enable */
39 #define CMD_RESET (1 << 1) /* reset HC not bus */
40 #define CMD_RUN (1 << 0) /* start/stop HC */
42 #define STS_ASS (1 << 15)
43 #define STS_PSS (1 << 14)
44 #define STS_HALT (1 << 12)
46 #define INTR_UE (1 << 0) /* USB interrupt enable */
47 #define INTR_UEE (1 << 1) /* USB error interrupt enable */
48 #define INTR_PCE (1 << 2) /* Port change detect enable */
49 #define INTR_SEE (1 << 4) /* system error enable */
50 #define INTR_AAE (1 << 5) /* Interrupt on async adavance enable */
52 uint32_t or_ctrldssegment;
53 uint32_t or_periodiclistbase;
54 uint32_t or_asynclistaddr;
55 uint32_t _reserved_0_;
56 uint32_t or_burstsize;
57 uint32_t or_txfilltuning;
58 #define TXFIFO_THRESH_MASK (0x3f << 16)
59 #define TXFIFO_THRESH(p) ((p & 0x3f) << 16)
60 uint32_t _reserved_1_[6];
61 uint32_t or_configflag;
62 #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
63 uint32_t or_portsc[MAX_HC_PORTS];
64 #define PORTSC_PSPD(x) (((x) >> 26) & 0x3)
65 #define PORTSC_PSPD_FS 0x0
66 #define PORTSC_PSPD_LS 0x1
67 #define PORTSC_PSPD_HS 0x2
69 } __attribute__ ((packed, aligned(4)));
71 #define USBMODE 0x68 /* USB Device mode */
72 #define USBMODE_SDIS (1 << 3) /* Stream disable */
73 #define USBMODE_BE (1 << 2) /* BE/LE endiannes select */
74 #define USBMODE_CM_HC (3 << 0) /* host controller mode */
75 #define USBMODE_CM_IDLE (0 << 0) /* idle state */
77 /* Interface descriptor */
78 struct usb_linux_interface_descriptor {
79 unsigned char bLength;
80 unsigned char bDescriptorType;
81 unsigned char bInterfaceNumber;
82 unsigned char bAlternateSetting;
83 unsigned char bNumEndpoints;
84 unsigned char bInterfaceClass;
85 unsigned char bInterfaceSubClass;
86 unsigned char bInterfaceProtocol;
87 unsigned char iInterface;
88 } __attribute__ ((packed));
90 /* Configuration descriptor information.. */
91 struct usb_linux_config_descriptor {
92 unsigned char bLength;
93 unsigned char bDescriptorType;
94 unsigned short wTotalLength;
95 unsigned char bNumInterfaces;
96 unsigned char bConfigurationValue;
97 unsigned char iConfiguration;
98 unsigned char bmAttributes;
99 unsigned char MaxPower;
100 } __attribute__ ((packed));
102 #if defined CONFIG_EHCI_DESC_BIG_ENDIAN
103 #define ehci_readl(x) be32_to_cpu(__raw_readl(x))
104 #define ehci_writel(a, b) __raw_writel(cpu_to_be32(b), a)
106 #define ehci_readl(x) readl(x)
107 #define ehci_writel(a, b) writel(b, a)
110 #if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
111 #define hc32_to_cpu(x) be32_to_cpu((x))
112 #define cpu_to_hc32(x) cpu_to_be32((x))
114 #define hc32_to_cpu(x) le32_to_cpu((x))
115 #define cpu_to_hc32(x) cpu_to_le32((x))
118 #define EHCI_PS_WKOC_E (1 << 22) /* RW wake on over current */
119 #define EHCI_PS_WKDSCNNT_E (1 << 21) /* RW wake on disconnect */
120 #define EHCI_PS_WKCNNT_E (1 << 20) /* RW wake on connect */
121 #define EHCI_PS_PO (1 << 13) /* RW port owner */
122 #define EHCI_PS_PP (1 << 12) /* RW,RO port power */
123 #define EHCI_PS_LS (3 << 10) /* RO line status */
124 #define EHCI_PS_PR (1 << 8) /* RW port reset */
125 #define EHCI_PS_SUSP (1 << 7) /* RW suspend */
126 #define EHCI_PS_FPR (1 << 6) /* RW force port resume */
127 #define EHCI_PS_OCC (1 << 5) /* RWC over current change */
128 #define EHCI_PS_OCA (1 << 4) /* RO over current active */
129 #define EHCI_PS_PEC (1 << 3) /* RWC port enable change */
130 #define EHCI_PS_PE (1 << 2) /* RW port enable */
131 #define EHCI_PS_CSC (1 << 1) /* RWC connect status change */
132 #define EHCI_PS_CS (1 << 0) /* RO connect status */
133 #define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
135 #define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == (1 << 10))
138 * Schedule Interface Space.
140 * IMPORTANT: Software must ensure that no interface data structure
141 * reachable by the EHCI host controller spans a 4K page boundary!
143 * Periodic transfers (i.e. isochronous and interrupt transfers) are
147 /* Queue Element Transfer Descriptor (qTD). */
149 /* this part defined by EHCI spec */
150 uint32_t qt_next; /* see EHCI 3.5.1 */
151 #define QT_NEXT_TERMINATE 1
152 uint32_t qt_altnext; /* see EHCI 3.5.2 */
153 uint32_t qt_token; /* see EHCI 3.5.3 */
154 #define QT_TOKEN_DT(x) (((x) & 0x1) << 31) /* Data Toggle */
155 #define QT_TOKEN_GET_DT(x) (((x) >> 31) & 0x1)
156 #define QT_TOKEN_TOTALBYTES(x) (((x) & 0x7fff) << 16) /* Total Bytes to Transfer */
157 #define QT_TOKEN_GET_TOTALBYTES(x) (((x) >> 16) & 0x7fff)
158 #define QT_TOKEN_IOC(x) (((x) & 0x1) << 15) /* Interrupt On Complete */
159 #define QT_TOKEN_CPAGE(x) (((x) & 0x7) << 12) /* Current Page */
160 #define QT_TOKEN_CERR(x) (((x) & 0x3) << 10) /* Error Counter */
161 #define QT_TOKEN_PID(x) (((x) & 0x3) << 8) /* PID Code */
162 #define QT_TOKEN_PID_OUT 0x0
163 #define QT_TOKEN_PID_IN 0x1
164 #define QT_TOKEN_PID_SETUP 0x2
165 #define QT_TOKEN_STATUS(x) (((x) & 0xff) << 0) /* Status */
166 #define QT_TOKEN_GET_STATUS(x) (((x) >> 0) & 0xff)
167 #define QT_TOKEN_STATUS_ACTIVE 0x80
168 #define QT_TOKEN_STATUS_HALTED 0x40
169 #define QT_TOKEN_STATUS_DATBUFERR 0x20
170 #define QT_TOKEN_STATUS_BABBLEDET 0x10
171 #define QT_TOKEN_STATUS_XACTERR 0x08
172 #define QT_TOKEN_STATUS_MISSEDUFRAME 0x04
173 #define QT_TOKEN_STATUS_SPLITXSTATE 0x02
174 #define QT_TOKEN_STATUS_PERR 0x01
175 #define QT_BUFFER_CNT 5
176 uint32_t qt_buffer[QT_BUFFER_CNT]; /* see EHCI 3.5.4 */
177 uint32_t qt_buffer_hi[QT_BUFFER_CNT]; /* Appendix B */
178 /* pad struct for 32 byte alignment */
182 #define EHCI_PAGE_SIZE 4096
184 /* Queue Head (QH). */
187 #define QH_LINK_TERMINATE 1
188 #define QH_LINK_TYPE_ITD 0
189 #define QH_LINK_TYPE_QH 2
190 #define QH_LINK_TYPE_SITD 4
191 #define QH_LINK_TYPE_FSTN 6
193 #define QH_ENDPT1_RL(x) (((x) & 0xf) << 28) /* NAK Count Reload */
194 #define QH_ENDPT1_C(x) (((x) & 0x1) << 27) /* Control Endpoint Flag */
195 #define QH_ENDPT1_MAXPKTLEN(x) (((x) & 0x7ff) << 16) /* Maximum Packet Length */
196 #define QH_ENDPT1_H(x) (((x) & 0x1) << 15) /* Head of Reclamation List Flag */
197 #define QH_ENDPT1_DTC(x) (((x) & 0x1) << 14) /* Data Toggle Control */
198 #define QH_ENDPT1_DTC_IGNORE_QTD_TD 0x0
199 #define QH_ENDPT1_DTC_DT_FROM_QTD 0x1
200 #define QH_ENDPT1_EPS(x) (((x) & 0x3) << 12) /* Endpoint Speed */
201 #define QH_ENDPT1_EPS_FS 0x0
202 #define QH_ENDPT1_EPS_LS 0x1
203 #define QH_ENDPT1_EPS_HS 0x2
204 #define QH_ENDPT1_ENDPT(x) (((x) & 0xf) << 8) /* Endpoint Number */
205 #define QH_ENDPT1_I(x) (((x) & 0x1) << 7) /* Inactivate on Next Transaction */
206 #define QH_ENDPT1_DEVADDR(x) (((x) & 0x7f) << 0) /* Device Address */
208 #define QH_ENDPT2_MULT(x) (((x) & 0x3) << 30) /* High-Bandwidth Pipe Multiplier */
209 #define QH_ENDPT2_PORTNUM(x) (((x) & 0x7f) << 23) /* Port Number */
210 #define QH_ENDPT2_HUBADDR(x) (((x) & 0x7f) << 16) /* Hub Address */
211 #define QH_ENDPT2_UFCMASK(x) (((x) & 0xff) << 8) /* Split Completion Mask */
212 #define QH_ENDPT2_UFSMASK(x) (((x) & 0xff) << 0) /* Interrupt Schedule Mask */
214 struct qTD qh_overlay;
216 * Add dummy fill value to make the size of this struct
217 * aligned to 32 bytes
225 /* Tweak flags for EHCI, used to control operation */
227 /* don't use or_configflag in init */
228 EHCI_TWEAK_NO_INIT_CF = 1 << 0,
234 void (*set_usb_mode)(struct ehci_ctrl *ctrl);
235 int (*get_port_speed)(struct ehci_ctrl *ctrl, uint32_t reg);
236 void (*powerup_fixup)(struct ehci_ctrl *ctrl, uint32_t *status_reg,
238 uint32_t *(*get_portsc_register)(struct ehci_ctrl *ctrl, int port);
239 int (*init_after_reset)(struct ehci_ctrl *ctrl);
243 enum usb_init_type init;
244 struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
245 struct ehci_hcor *hcor;
248 struct QH qh_list __aligned(USB_DMA_MINALIGN);
249 struct QH periodic_queue __aligned(USB_DMA_MINALIGN);
250 uint32_t *periodic_list;
251 int periodic_schedules;
254 void *priv; /* client's private data */
258 * ehci_set_controller_info() - Set up private data for the controller
260 * This function can be called in ehci_hcd_init() to tell the EHCI layer
261 * about the controller's private data pointer. Then in the above functions
262 * this can be accessed given the struct ehci_ctrl pointer. Also special
263 * EHCI operation methods can be provided if required
265 * @index: Controller number to set
266 * @priv: Controller pointer
267 * @ops: Controller operations, or NULL to use default
269 void ehci_set_controller_priv(int index, void *priv,
270 const struct ehci_ops *ops);
273 * ehci_get_controller_priv() - Get controller private data
275 * @index Controller number to get
276 * @return controller pointer for this index
278 void *ehci_get_controller_priv(int index);
280 /* Low level init functions */
281 int ehci_hcd_init(int index, enum usb_init_type init,
282 struct ehci_hccr **hccr, struct ehci_hcor **hcor);
283 int ehci_hcd_stop(int index);
285 int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
286 struct ehci_hcor *hcor, const struct ehci_ops *ops,
287 uint tweaks, enum usb_init_type init);
288 int ehci_deregister(struct udevice *dev);
289 extern struct dm_usb_ops ehci_usb_ops;
291 #endif /* USB_EHCI_H */