1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2011 Ilya Yanok, Emcraft Systems
4 * (C) Copyright 2004-2008
5 * Texas Instruments, <www.ti.com>
7 * Derived from Beagle Board code by
8 * Sunil Kumar <sunilsaini05@gmail.com>
9 * Shashi Ranjan <shashiranjanmca05@gmail.com>
16 #include <linux/delay.h>
21 #include <asm/arch/ehci.h>
22 #include <asm/ehci-omap.h>
26 static struct omap_uhh *const uhh = (struct omap_uhh *)OMAP_UHH_BASE;
27 static struct omap_usbtll *const usbtll = (struct omap_usbtll *)OMAP_USBTLL_BASE;
28 static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE;
30 static int omap_uhh_reset(void)
35 rev = readl(&uhh->rev);
38 writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc);
42 /* Wait for soft RESET to complete */
43 while (!(readl(&uhh->syss) & 0x1)) {
45 printf("%s: RESET timeout\n", __func__);
52 /* Set No-Idle, No-Standby */
53 writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
56 default: /* Rev. 2 onwards */
58 udelay(2); /* Need to wait before accessing SYSCONFIG back */
60 /* Wait for soft RESET to complete */
61 while ((readl(&uhh->sysc) & 0x1)) {
63 printf("%s: RESET timeout\n", __func__);
70 writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
77 static int omap_ehci_tll_reset(void)
79 unsigned long init = get_timer(0);
81 /* perform TLL soft reset, and wait until reset is complete */
82 writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc);
84 /* Wait for TLL reset to complete */
85 while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE))
86 if (get_timer(init) > CONFIG_SYS_HZ) {
87 debug("OMAP EHCI error: timeout resetting TLL\n");
94 static void omap_usbhs_hsic_init(int port)
98 /* Enable channels now */
99 reg = readl(&usbtll->channel_conf + port);
101 setbits_le32(®, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI
102 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
103 | OMAP_TLL_CHANNEL_CONF_DRVVBUS
104 | OMAP_TLL_CHANNEL_CONF_CHRGVBUS
105 | OMAP_TLL_CHANNEL_CONF_CHANEN));
107 writel(reg, &usbtll->channel_conf + port);
110 #ifdef CONFIG_USB_ULPI
111 static void omap_ehci_soft_phy_reset(int port)
113 struct ulpi_viewport ulpi_vp;
115 ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi;
116 ulpi_vp.port_num = port;
118 ulpi_reset(&ulpi_vp);
121 static void omap_ehci_soft_phy_reset(int port)
127 #if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
128 defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) || \
129 defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO)
130 /* controls PHY(s) reset signal(s) */
131 static inline void omap_ehci_phy_reset(int on, int delay)
135 * Hold the PHY in RESET for enough time till
136 * PHY is settled and ready
140 #ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
141 gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset");
142 gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on);
144 #ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
145 gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
146 gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
148 #ifdef CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
149 gpio_request(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, "USB PHY3 reset");
150 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, !on);
153 /* Hold the PHY in RESET for enough time till DIR is high */
159 #define omap_ehci_phy_reset(on, delay) do {} while (0)
162 /* Reset is needed otherwise the kernel-driver will throw an error. */
163 int omap_ehci_hcd_stop(void)
165 debug("Resetting OMAP EHCI\n");
166 omap_ehci_phy_reset(1, 0);
168 if (omap_uhh_reset() < 0)
171 if (omap_ehci_tll_reset() < 0)
178 * Initialize the OMAP EHCI controller and PHY.
179 * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
180 * See there for additional Copyrights.
182 int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata,
183 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
186 unsigned int i, reg = 0, rev = 0;
188 debug("Initializing OMAP EHCI\n");
190 ret = board_usb_init(index, USB_INIT_HOST);
194 /* Put the PHY in RESET */
195 omap_ehci_phy_reset(1, 10);
197 ret = omap_uhh_reset();
201 ret = omap_ehci_tll_reset();
205 writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
206 OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
207 OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc);
209 /* Put UHH in NoIdle/NoStandby mode */
210 writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
212 /* setup ULPI bypass and burst configurations */
213 clrsetbits_le32(®, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN,
214 (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN |
215 OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN |
216 OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN));
218 rev = readl(&uhh->rev);
219 if (rev == OMAP_USBHS_REV1) {
220 if (is_ehci_phy_mode(usbhs_pdata->port_mode[0]))
221 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
223 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
225 if (is_ehci_phy_mode(usbhs_pdata->port_mode[1]))
226 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
228 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
230 if (is_ehci_phy_mode(usbhs_pdata->port_mode[2]))
231 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
233 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
234 } else if (rev == OMAP_USBHS_REV2) {
236 clrsetbits_le32(®, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR),
237 OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
239 /* Clear port mode fields for PHY mode */
241 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
242 setbits_le32(®, OMAP_P1_MODE_HSIC);
244 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
245 setbits_le32(®, OMAP_P2_MODE_HSIC);
247 } else if (rev == OMAP_USBHS_REV2_1) {
249 clrsetbits_le32(®,
250 (OMAP_P1_MODE_CLEAR |
253 OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
255 /* Clear port mode fields for PHY mode */
257 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
258 setbits_le32(®, OMAP_P1_MODE_HSIC);
260 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
261 setbits_le32(®, OMAP_P2_MODE_HSIC);
263 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2]))
264 setbits_le32(®, OMAP_P3_MODE_HSIC);
267 debug("OMAP UHH_REVISION 0x%x\n", rev);
268 writel(reg, &uhh->hostconfig);
270 for (i = 0; i < OMAP_HS_USB_PORTS; i++)
271 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i]))
272 omap_usbhs_hsic_init(i);
274 omap_ehci_phy_reset(0, 10);
277 * An undocumented "feature" in the OMAP3 EHCI controller,
278 * causes suspended ports to be taken out of suspend when
279 * the USBCMD.Run/Stop bit is cleared (for example when
280 * we do ehci_bus_suspend).
281 * This breaks suspend-resume if the root-hub is allowed
282 * to suspend. Writing 1 to this undocumented register bit
283 * disables this feature and restores normal behavior.
285 writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04);
287 for (i = 0; i < OMAP_HS_USB_PORTS; i++)
288 if (is_ehci_phy_mode(usbhs_pdata->port_mode[i]))
289 omap_ehci_soft_phy_reset(i);
291 *hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE);
292 *hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10);
294 debug("OMAP EHCI init done\n");