2 * (C) Copyright 2011 Ilya Yanok, Emcraft Systems
3 * (C) Copyright 2004-2008
4 * Texas Instruments, <www.ti.com>
6 * Derived from Beagle Board code by
7 * Sunil Kumar <sunilsaini05@gmail.com>
8 * Shashi Ranjan <shashiranjanmca05@gmail.com>
11 * SPDX-License-Identifier: GPL-2.0+
20 #include <asm/arch/ehci.h>
21 #include <asm/ehci-omap.h>
25 static struct omap_uhh *const uhh = (struct omap_uhh *)OMAP_UHH_BASE;
26 static struct omap_usbtll *const usbtll = (struct omap_usbtll *)OMAP_USBTLL_BASE;
27 static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE;
29 static int omap_uhh_reset(void)
32 * Soft resetting the UHH module causes instability issues on
33 * all OMAPs so we just avoid it.
36 * i571: USB host EHCI may stall when entering smart-standby mode
37 * i660: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
39 * On OMAP4/5, soft-resetting the UHH module will put it into
40 * Smart-Idle mode and lead to a deadlock.
42 * On OMAP3, this doesn't seem to be the case but still instabilities
43 * are observed on beagle (3530 ES1.0) if soft-reset is used.
44 * e.g. NFS root failures with Linux kernel.
49 static int omap_ehci_tll_reset(void)
51 unsigned long init = get_timer(0);
53 /* perform TLL soft reset, and wait until reset is complete */
54 writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc);
56 /* Wait for TLL reset to complete */
57 while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE))
58 if (get_timer(init) > CONFIG_SYS_HZ) {
59 debug("OMAP EHCI error: timeout resetting TLL\n");
66 static void omap_usbhs_hsic_init(int port)
70 /* Enable channels now */
71 reg = readl(&usbtll->channel_conf + port);
73 setbits_le32(®, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI
74 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
75 | OMAP_TLL_CHANNEL_CONF_DRVVBUS
76 | OMAP_TLL_CHANNEL_CONF_CHRGVBUS
77 | OMAP_TLL_CHANNEL_CONF_CHANEN));
79 writel(reg, &usbtll->channel_conf + port);
82 static void omap_ehci_soft_phy_reset(int port)
84 struct ulpi_viewport ulpi_vp;
86 ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi;
87 ulpi_vp.port_num = port;
92 inline int __board_usb_init(void)
96 int board_usb_init(void) __attribute__((weak, alias("__board_usb_init")));
98 #if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
99 defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO)
100 /* controls PHY(s) reset signal(s) */
101 static inline void omap_ehci_phy_reset(int on, int delay)
105 * Hold the PHY in RESET for enough time till
106 * PHY is settled and ready
110 #ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
111 gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset");
112 gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on);
114 #ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
115 gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
116 gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
119 /* Hold the PHY in RESET for enough time till DIR is high */
125 #define omap_ehci_phy_reset(on, delay) do {} while (0)
128 /* Reset is needed otherwise the kernel-driver will throw an error. */
129 int omap_ehci_hcd_stop(void)
131 debug("Resetting OMAP EHCI\n");
132 omap_ehci_phy_reset(1, 0);
134 if (omap_uhh_reset() < 0)
137 if (omap_ehci_tll_reset() < 0)
144 * Initialize the OMAP EHCI controller and PHY.
145 * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
146 * See there for additional Copyrights.
148 int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata,
149 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
152 unsigned int i, reg = 0, rev = 0;
154 debug("Initializing OMAP EHCI\n");
156 ret = board_usb_init();
160 /* Put the PHY in RESET */
161 omap_ehci_phy_reset(1, 10);
163 ret = omap_uhh_reset();
167 ret = omap_ehci_tll_reset();
171 writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
172 OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
173 OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc);
175 /* Put UHH in NoIdle/NoStandby mode */
176 writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
178 /* setup ULPI bypass and burst configurations */
179 clrsetbits_le32(®, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN,
180 (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN |
181 OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN |
182 OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN));
184 rev = readl(&uhh->rev);
185 if (rev == OMAP_USBHS_REV1) {
186 if (is_ehci_phy_mode(usbhs_pdata->port_mode[0]))
187 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
189 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
191 if (is_ehci_phy_mode(usbhs_pdata->port_mode[1]))
192 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
194 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
196 if (is_ehci_phy_mode(usbhs_pdata->port_mode[2]))
197 clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
199 setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
200 } else if (rev == OMAP_USBHS_REV2) {
201 clrsetbits_le32(®, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR),
202 OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
204 /* Clear port mode fields for PHY mode*/
206 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
207 setbits_le32(®, OMAP_P1_MODE_HSIC);
209 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
210 setbits_le32(®, OMAP_P2_MODE_HSIC);
212 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2]))
213 setbits_le32(®, OMAP_P3_MODE_HSIC);
216 debug("OMAP UHH_REVISION 0x%x\n", rev);
217 writel(reg, &uhh->hostconfig);
219 for (i = 0; i < OMAP_HS_USB_PORTS; i++)
220 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i]))
221 omap_usbhs_hsic_init(i);
223 omap_ehci_phy_reset(0, 10);
226 * An undocumented "feature" in the OMAP3 EHCI controller,
227 * causes suspended ports to be taken out of suspend when
228 * the USBCMD.Run/Stop bit is cleared (for example when
229 * we do ehci_bus_suspend).
230 * This breaks suspend-resume if the root-hub is allowed
231 * to suspend. Writing 1 to this undocumented register bit
232 * disables this feature and restores normal behavior.
234 writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04);
236 for (i = 0; i < OMAP_HS_USB_PORTS; i++)
237 if (is_ehci_phy_mode(usbhs_pdata->port_mode[i]))
238 omap_ehci_soft_phy_reset(i);
240 *hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE);
241 *hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10);
243 debug("OMAP EHCI init done\n");