2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <asm/arch/imx-regs.h>
24 #include <usb/ehci-fsl.h>
28 #include "ehci-core.h"
30 #define USBCTRL_OTGBASE_OFFSET 0x600
33 #define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6)
34 #define MX25_USB_CTRL_HSTD_BIT (1<<5)
35 #define MX25_USB_CTRL_USBTE_BIT (1<<4)
36 #define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3)
40 #define MX31_OTG_SIC_SHIFT 29
41 #define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
42 #define MX31_OTG_PM_BIT (1 << 24)
44 #define MX31_H2_SIC_SHIFT 21
45 #define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
46 #define MX31_H2_PM_BIT (1 << 16)
47 #define MX31_H2_DT_BIT (1 << 5)
49 #define MX31_H1_SIC_SHIFT 13
50 #define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
51 #define MX31_H1_PM_BIT (1 << 8)
52 #define MX31_H1_DT_BIT (1 << 4)
55 static int mxc_set_usbcontrol(int port, unsigned int flags)
60 v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT |
61 MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT;
65 v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
68 case 0: /* OTG port */
69 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
70 v |= (flags & MXC_EHCI_INTERFACE_MASK)
71 << MX31_OTG_SIC_SHIFT;
72 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
77 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT |
79 v |= (flags & MXC_EHCI_INTERFACE_MASK)
81 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
84 if (!(flags & MXC_EHCI_TTL_ENABLED))
89 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT |
91 v |= (flags & MXC_EHCI_INTERFACE_MASK)
93 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
96 if (!(flags & MXC_EHCI_TTL_ENABLED))
105 writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
109 int ehci_hcd_init(void)
111 struct usb_ehci *ehci;
113 struct clock_control_regs *sc_regs =
114 (struct clock_control_regs *)CCM_BASE;
116 __raw_readl(&sc_regs->ccmr);
117 __raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ;
122 ehci = (struct usb_ehci *)(IMX_USB_BASE +
123 (0x200 * CONFIG_MXC_USB_PORT));
124 hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
125 hcor = (struct ehci_hcor *)((uint32_t) hccr +
126 HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
127 setbits_le32(&ehci->usbmode, CM_HOST);
129 setbits_le32(&ehci->control, USB_EN);
131 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
133 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
141 * Destroy the appropriate control structures corresponding
142 * the the EHCI host controller.
144 int ehci_hcd_stop(void)