drivers/usb/host/ehci-mx6.c

   1 /*
   2  * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
   3  * Copyright (C) 2010 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  13  * for more details.
  14  */
  15
  16 #include <common.h>
  17 #include <usb.h>
  18 #include <errno.h>
  19 #include <linux/compiler.h>
  20 #include <usb/ehci-fsl.h>
  21 #include <asm/io.h>
  22 #include <asm/arch/imx-regs.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/mx6x_pins.h>
  25 #include <asm/arch/iomux-v3.h>
  26
  27 #include "ehci.h"
  28 #include "ehci-core.h"
  29
  30 #define USB_OTGREGS_OFFSET      0x000
  31 #define USB_H1REGS_OFFSET       0x200
  32 #define USB_H2REGS_OFFSET       0x400
  33 #define USB_H3REGS_OFFSET       0x600
  34 #define USB_OTHERREGS_OFFSET    0x800
  35
  36 #define USB_H1_CTRL_OFFSET      0x04
  37
  38 #define USBPHY_CTRL                             0x00000030
  39 #define USBPHY_CTRL_SET                         0x00000034
  40 #define USBPHY_CTRL_CLR                         0x00000038
  41 #define USBPHY_CTRL_TOG                         0x0000003c
  42
  43 #define USBPHY_PWD                              0x00000000
  44 #define USBPHY_CTRL_SFTRST                      0x80000000
  45 #define USBPHY_CTRL_CLKGATE                     0x40000000
  46 #define USBPHY_CTRL_ENUTMILEVEL3                0x00008000
  47 #define USBPHY_CTRL_ENUTMILEVEL2                0x00004000
  48
  49 #define ANADIG_USB2_CHRG_DETECT                 0x00000210
  50 #define ANADIG_USB2_CHRG_DETECT_EN_B            0x00100000
  51 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B      0x00080000
  52
  53 #define ANADIG_USB2_PLL_480_CTRL                0x00000020
  54 #define ANADIG_USB2_PLL_480_CTRL_SET            0x00000024
  55 #define ANADIG_USB2_PLL_480_CTRL_CLR            0x00000028
  56 #define ANADIG_USB2_PLL_480_CTRL_BYPASS         0x00010000
  57 #define ANADIG_USB2_PLL_480_CTRL_ENABLE         0x00002000
  58 #define ANADIG_USB2_PLL_480_CTRL_POWER          0x00001000
  59 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS    0x00000040
  60
  61
  62 #define UCTRL_OVER_CUR_POL      (1 << 8) /* OTG Polarity of Overcurrent */
  63 #define UCTRL_OVER_CUR_DIS      (1 << 7) /* Disable OTG Overcurrent Detection */
  64
  65 /* USBCMD */
  66 #define UH1_USBCMD_OFFSET       0x140
  67 #define UCMD_RUN_STOP           (1 << 0) /* controller run/stop */
  68 #define UCMD_RESET              (1 << 1) /* controller reset */
  69
  70 static void usbh1_internal_phy_clock_gate(int on)
  71 {
  72         void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
  73
  74         phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
  75         __raw_writel(USBPHY_CTRL_CLKGATE, phy_reg);
  76 }
  77
  78 static void usbh1_power_config(void)
  79 {
  80         void __iomem *anatop_base = (void __iomem *)ANATOP_BASE_ADDR;
  81
  82         /*
  83          * Some phy and power's special controls for host1
  84          * 1. The external charger detector needs to be disabled
  85          * or the signal at DP will be poor
  86          * 2. The PLL's power and output to usb for host 1
  87          * is totally controlled by IC, so the Software only needs
  88          * to enable them at initializtion.
  89          */
  90         __raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B |
  91                      ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
  92                      anatop_base + ANADIG_USB2_CHRG_DETECT);
  93
  94         __raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
  95                      anatop_base + ANADIG_USB2_PLL_480_CTRL_CLR);
  96
  97         __raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
  98                      ANADIG_USB2_PLL_480_CTRL_POWER |
  99                      ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
 100                      anatop_base + ANADIG_USB2_PLL_480_CTRL_SET);
 101 }
 102
 103 static int usbh1_phy_enable(void)
 104 {
 105         void __iomem *phy_reg = (void __iomem *)USB_PHY1_BASE_ADDR;
 106         void __iomem *phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
 107         void __iomem *usb_cmd = (void __iomem *)(USBOH3_USB_BASE_ADDR +
 108                                                  USB_H1REGS_OFFSET +
 109                                                  UH1_USBCMD_OFFSET);
 110         u32 val;
 111
 112         /* Stop then Reset */
 113         val = __raw_readl(usb_cmd);
 114         val &= ~UCMD_RUN_STOP;
 115         __raw_writel(val, usb_cmd);
 116         while (__raw_readl(usb_cmd) & UCMD_RUN_STOP)
 117                 ;
 118
 119         val = __raw_readl(usb_cmd);
 120         val |= UCMD_RESET;
 121         __raw_writel(val, usb_cmd);
 122         while (__raw_readl(usb_cmd) & UCMD_RESET)
 123                 ;
 124
 125         /* Reset USBPHY module */
 126         val = __raw_readl(phy_ctrl);
 127         val |= USBPHY_CTRL_SFTRST;
 128         __raw_writel(val, phy_ctrl);
 129         udelay(10);
 130
 131         /* Remove CLKGATE and SFTRST */
 132         val = __raw_readl(phy_ctrl);
 133         val &= ~(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
 134         __raw_writel(val, phy_ctrl);
 135         udelay(10);
 136
 137         /* Power up the PHY */
 138         __raw_writel(0, phy_reg + USBPHY_PWD);
 139         /* enable FS/LS device */
 140         val = __raw_readl(phy_reg + USBPHY_CTRL);
 141         val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
 142         __raw_writel(val, phy_reg + USBPHY_CTRL);
 143
 144         return 0;
 145 }
 146
 147 static void usbh1_oc_config(void)
 148 {
 149         void __iomem *usb_base = (void __iomem *)USBOH3_USB_BASE_ADDR;
 150         void __iomem *usbother_base = usb_base + USB_OTHERREGS_OFFSET;
 151         u32 val;
 152
 153         val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
 154 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
 155         /* mx6qarm2 seems to required a different setting*/
 156         val &= ~UCTRL_OVER_CUR_POL;
 157 #else
 158         val |= UCTRL_OVER_CUR_POL;
 159 #endif
 160         __raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
 161
 162         val = __raw_readl(usbother_base + USB_H1_CTRL_OFFSET);
 163         val |= UCTRL_OVER_CUR_DIS;
 164         __raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
 165 }
 166
 167 int ehci_hcd_init(void)
 168 {
 169         struct usb_ehci *ehci;
 170
 171         enable_usboh3_clk(1);
 172         mdelay(1);
 173
 174         /* Do board specific initialization */
 175         board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
 176
 177 #if CONFIG_MXC_USB_PORT == 1
 178         /* USB Host 1 */
 179         usbh1_power_config();
 180         usbh1_oc_config();
 181         usbh1_internal_phy_clock_gate(1);
 182         usbh1_phy_enable();
 183 #else
 184 #error "MXC USB port not yet supported"
 185 #endif
 186
 187         ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
 188                 (0x200 * CONFIG_MXC_USB_PORT));
 189         hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
 190         hcor = (struct ehci_hcor *)((uint32_t)hccr +
 191                         HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
 192         setbits_le32(&ehci->usbmode, CM_HOST);
 193
 194         __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
 195         setbits_le32(&ehci->portsc, USB_EN);
 196
 197         mdelay(10);
 198
 199         return 0;
 200 }
 201
 202 int ehci_hcd_stop(void)
 203 {
 204         return 0;
 205 }