2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/compiler.h>
13 #include <usb/ehci-ci.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/imx-common/iomux-v3.h>
22 #define USB_OTGREGS_OFFSET 0x000
23 #define USB_H1REGS_OFFSET 0x200
24 #define USB_H2REGS_OFFSET 0x400
25 #define USB_H3REGS_OFFSET 0x600
26 #define USB_OTHERREGS_OFFSET 0x800
28 #define USB_H1_CTRL_OFFSET 0x04
30 #define USBPHY_CTRL 0x00000030
31 #define USBPHY_CTRL_SET 0x00000034
32 #define USBPHY_CTRL_CLR 0x00000038
33 #define USBPHY_CTRL_TOG 0x0000003c
35 #define USBPHY_PWD 0x00000000
36 #define USBPHY_CTRL_SFTRST 0x80000000
37 #define USBPHY_CTRL_CLKGATE 0x40000000
38 #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
39 #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
40 #define USBPHY_CTRL_OTG_ID 0x08000000
42 #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
43 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
45 #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
46 #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
47 #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
48 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
50 #define USBNC_OFFSET 0x200
51 #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
52 #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
53 #define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
54 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
55 #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
58 #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
59 #define UCMD_RESET (1 << 1) /* controller reset */
61 #if defined(CONFIG_MX6)
62 static const unsigned phy_bases[] = {
67 static void usb_internal_phy_clock_gate(int index, int on)
69 void __iomem *phy_reg;
71 if (index >= ARRAY_SIZE(phy_bases))
74 phy_reg = (void __iomem *)phy_bases[index];
75 phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
76 writel(USBPHY_CTRL_CLKGATE, phy_reg);
79 static void usb_power_config(int index)
81 struct anatop_regs __iomem *anatop =
82 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
83 void __iomem *chrg_detect;
84 void __iomem *pll_480_ctrl_clr;
85 void __iomem *pll_480_ctrl_set;
89 chrg_detect = &anatop->usb1_chrg_detect;
90 pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
91 pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
94 chrg_detect = &anatop->usb2_chrg_detect;
95 pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
96 pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
102 * Some phy and power's special controls
103 * 1. The external charger detector needs to be disabled
104 * or the signal at DP will be poor
105 * 2. The PLL's power and output to usb
106 * is totally controlled by IC, so the Software only needs
107 * to enable them at initializtion.
109 writel(ANADIG_USB2_CHRG_DETECT_EN_B |
110 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
113 writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
116 writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
117 ANADIG_USB2_PLL_480_CTRL_POWER |
118 ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
122 /* Return 0 : host node, <>0 : device mode */
123 static int usb_phy_enable(int index, struct usb_ehci *ehci)
125 void __iomem *phy_reg;
126 void __iomem *phy_ctrl;
127 void __iomem *usb_cmd;
130 if (index >= ARRAY_SIZE(phy_bases))
133 phy_reg = (void __iomem *)phy_bases[index];
134 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
135 usb_cmd = (void __iomem *)&ehci->usbcmd;
137 /* Stop then Reset */
138 clrbits_le32(usb_cmd, UCMD_RUN_STOP);
139 ret = wait_for_bit(__func__, usb_cmd, UCMD_RUN_STOP, false, 10000,
144 setbits_le32(usb_cmd, UCMD_RESET);
145 ret = wait_for_bit(__func__, usb_cmd, UCMD_RESET, false, 10000, false);
149 /* Reset USBPHY module */
150 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
153 /* Remove CLKGATE and SFTRST */
154 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
157 /* Power up the PHY */
158 writel(0, phy_reg + USBPHY_PWD);
159 /* enable FS/LS device */
160 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
161 USBPHY_CTRL_ENUTMILEVEL3);
166 int usb_phy_mode(int port)
168 void __iomem *phy_reg;
169 void __iomem *phy_ctrl;
172 phy_reg = (void __iomem *)phy_bases[port];
173 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
175 val = readl(phy_ctrl);
177 if (val & USBPHY_CTRL_OTG_ID)
178 return USB_INIT_DEVICE;
180 return USB_INIT_HOST;
183 /* Base address for this IP block is 0x02184800 */
185 u32 ctrl[4]; /* otg/host1-3 */
191 #elif defined(CONFIG_MX7)
206 static void usb_power_config(int index)
208 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
209 (0x10000 * index) + USBNC_OFFSET);
210 void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
211 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
214 * Clear the ACAENB to enable usb_otg_id detection,
215 * otherwise it is the ACA detection enabled.
217 clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
219 /* Set power polarity to high active */
220 #ifdef CONFIG_MXC_USB_OTG_HACTIVE
221 setbits_le32(ctrl, UCTRL_PWR_POL);
223 clrbits_le32(ctrl, UCTRL_PWR_POL);
227 int usb_phy_mode(int port)
229 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
230 (0x10000 * port) + USBNC_OFFSET);
231 void __iomem *status = (void __iomem *)(&usbnc->phy_status);
236 if (val & USBNC_PHYSTATUS_ID_DIG)
237 return USB_INIT_DEVICE;
239 return USB_INIT_HOST;
243 static void usb_oc_config(int index)
245 #if defined(CONFIG_MX6)
246 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
247 USB_OTHERREGS_OFFSET);
248 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
249 #elif defined(CONFIG_MX7)
250 struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
251 (0x10000 * index) + USBNC_OFFSET);
252 void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
255 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
256 /* mx6qarm2 seems to required a different setting*/
257 clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
259 setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
262 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
266 * board_usb_phy_mode - override usb phy mode
267 * @port: usb host/otg port
269 * Target board specific, override usb_phy_mode.
270 * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
271 * left disconnected in this case usb_phy_mode will not be able to identify
272 * the phy mode that usb port is used.
273 * Machine file overrides board_usb_phy_mode.
275 * Return: USB_INIT_DEVICE or USB_INIT_HOST
277 int __weak board_usb_phy_mode(int port)
279 return usb_phy_mode(port);
283 * board_ehci_hcd_init - set usb vbus voltage
284 * @port: usb otg port
286 * Target board specific, setup iomux pad to setup supply vbus voltage
287 * for usb otg port. Machine board file overrides board_ehci_hcd_init
291 int __weak board_ehci_hcd_init(int port)
297 * board_ehci_power - enables/disables usb vbus voltage
298 * @port: usb otg port
299 * @on: on/off vbus voltage
301 * Enables/disables supply vbus voltage for usb otg port.
302 * Machine board file overrides board_ehci_power
306 int __weak board_ehci_power(int port, int on)
311 int ehci_mx6_common_init(struct usb_ehci *ehci, int index)
315 enable_usboh3_clk(1);
318 /* Do board specific initialization */
319 ret = board_ehci_hcd_init(index);
323 usb_power_config(index);
324 usb_oc_config(index);
326 #if defined(CONFIG_MX6)
327 usb_internal_phy_clock_gate(index, 1);
328 usb_phy_enable(index, ehci);
334 #ifndef CONFIG_DM_USB
335 int ehci_hcd_init(int index, enum usb_init_type init,
336 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
338 enum usb_init_type type;
339 #if defined(CONFIG_MX6)
340 u32 controller_spacing = 0x200;
341 #elif defined(CONFIG_MX7)
342 u32 controller_spacing = 0x10000;
344 struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
345 (controller_spacing * index));
351 ret = ehci_mx6_common_init(ehci, index);
355 type = board_usb_phy_mode(index);
358 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
359 *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
360 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
363 if ((type == init) || (type == USB_INIT_DEVICE))
364 board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
367 if (type == USB_INIT_DEVICE)
370 setbits_le32(&ehci->usbmode, CM_HOST);
371 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
372 setbits_le32(&ehci->portsc, USB_EN);
379 int ehci_hcd_stop(int index)
384 struct ehci_mx6_priv_data {
385 struct ehci_ctrl ctrl;
386 struct usb_ehci *ehci;
387 enum usb_init_type init_type;
391 static int mx6_init_after_reset(struct ehci_ctrl *dev)
393 struct ehci_mx6_priv_data *priv = dev->priv;
394 enum usb_init_type type = priv->init_type;
395 struct usb_ehci *ehci = priv->ehci;
398 ret = ehci_mx6_common_init(priv->ehci, priv->portnr);
402 board_ehci_power(priv->portnr, (type == USB_INIT_DEVICE) ? 0 : 1);
404 if (type == USB_INIT_DEVICE)
407 setbits_le32(&ehci->usbmode, CM_HOST);
408 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
409 setbits_le32(&ehci->portsc, USB_EN);
416 static const struct ehci_ops mx6_ehci_ops = {
417 .init_after_reset = mx6_init_after_reset
420 static int ehci_usb_probe(struct udevice *dev)
422 struct usb_platdata *plat = dev_get_platdata(dev);
423 struct usb_ehci *ehci = (struct usb_ehci *)dev_get_addr(dev);
424 struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
425 struct ehci_hccr *hccr;
426 struct ehci_hcor *hcor;
430 priv->portnr = dev->seq;
431 priv->init_type = plat->init_type;
433 ret = ehci_mx6_common_init(ehci, priv->portnr);
437 board_ehci_power(priv->portnr, (priv->init_type == USB_INIT_DEVICE) ? 0 : 1);
439 if (priv->init_type == USB_INIT_HOST) {
440 setbits_le32(&ehci->usbmode, CM_HOST);
441 writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
442 setbits_le32(&ehci->portsc, USB_EN);
447 hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
448 hcor = (struct ehci_hcor *)((uint32_t)hccr +
449 HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
451 return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
454 static const struct udevice_id mx6_usb_ids[] = {
455 { .compatible = "fsl,imx27-usb" },
459 U_BOOT_DRIVER(usb_mx6) = {
462 .of_match = mx6_usb_ids,
463 .probe = ehci_usb_probe,
464 .remove = ehci_deregister,
465 .ops = &ehci_usb_ops,
466 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
467 .priv_auto_alloc_size = sizeof(struct ehci_mx6_priv_data),
468 .flags = DM_FLAG_ALLOC_PRIV_DMA,