drivers/usb/host/ehci-marvell.c

   1 /*
   2  * (C) Copyright 2009
   3  * Marvell Semiconductor <www.marvell.com>
   4  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <usb.h>
  12 #include "ehci.h"
  13 #include <linux/mbus.h>
  14 #include <asm/arch/cpu.h>
  15
  16 #if defined(CONFIG_KIRKWOOD)
  17 #include <asm/arch/soc.h>
  18 #elif defined(CONFIG_ORION5X)
  19 #include <asm/arch/orion5x.h>
  20 #endif
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #define USB_WINDOW_CTRL(i)      (0x320 + ((i) << 4))
  25 #define USB_WINDOW_BASE(i)      (0x324 + ((i) << 4))
  26 #define USB_TARGET_DRAM         0x0
  27
  28 /*
  29  * USB 2.0 Bridge Address Decoding registers setup
  30  */
  31 #ifdef CONFIG_ARMADA_XP
  32
  33 /*
  34  * Armada XP and Armada 38x have different base addresses for
  35  * the USB 2.0 EHCI host controller. So we need to provide
  36  * a mechnism to support both here.
  37  */
  38 #define MVUSB0_BASE                                     \
  39         (mvebu_soc_family() == MVEBU_SOC_A38X ?         \
  40          MVEBU_USB20_BASE : MVEBU_AXP_USB_BASE)
  41
  42 /*
  43  * Once all the older Marvell SoC's (Orion, Kirkwood) are converted
  44  * to the common mvebu archticture including the mbus setup, this
  45  * will be the only function needed to configure the access windows
  46  */
  47 static void usb_brg_adrdec_setup(void)
  48 {
  49         const struct mbus_dram_target_info *dram;
  50         int i;
  51
  52         dram = mvebu_mbus_dram_info();
  53
  54         for (i = 0; i < 4; i++) {
  55                 writel(0, MVUSB0_BASE + USB_WINDOW_CTRL(i));
  56                 writel(0, MVUSB0_BASE + USB_WINDOW_BASE(i));
  57         }
  58
  59         for (i = 0; i < dram->num_cs; i++) {
  60                 const struct mbus_dram_window *cs = dram->cs + i;
  61
  62                 /* Write size, attributes and target id to control register */
  63                 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
  64                        (dram->mbus_dram_target_id << 4) | 1,
  65                        MVUSB0_BASE + USB_WINDOW_CTRL(i));
  66
  67                 /* Write base address to base register */
  68                 writel(cs->base, MVUSB0_BASE + USB_WINDOW_BASE(i));
  69         }
  70 }
  71 #else
  72 static void usb_brg_adrdec_setup(void)
  73 {
  74         int i;
  75         u32 size, base, attrib;
  76
  77         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  78
  79                 /* Enable DRAM bank */
  80                 switch (i) {
  81                 case 0:
  82                         attrib = MVUSB0_CPU_ATTR_DRAM_CS0;
  83                         break;
  84                 case 1:
  85                         attrib = MVUSB0_CPU_ATTR_DRAM_CS1;
  86                         break;
  87                 case 2:
  88                         attrib = MVUSB0_CPU_ATTR_DRAM_CS2;
  89                         break;
  90                 case 3:
  91                         attrib = MVUSB0_CPU_ATTR_DRAM_CS3;
  92                         break;
  93                 default:
  94                         /* invalide bank, disable access */
  95                         attrib = 0;
  96                         break;
  97                 }
  98
  99                 size = gd->bd->bi_dram[i].size;
 100                 base = gd->bd->bi_dram[i].start;
 101                 if ((size) && (attrib))
 102                         writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
 103                                                    attrib, MVCPU_WIN_ENABLE),
 104                                 MVUSB0_BASE + USB_WINDOW_CTRL(i));
 105                 else
 106                         writel(MVCPU_WIN_DISABLE,
 107                                MVUSB0_BASE + USB_WINDOW_CTRL(i));
 108
 109                 writel(base, MVUSB0_BASE + USB_WINDOW_BASE(i));
 110         }
 111 }
 112 #endif
 113
 114 /*
 115  * Create the appropriate control structures to manage
 116  * a new EHCI host controller.
 117  */
 118 int ehci_hcd_init(int index, enum usb_init_type init,
 119                 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 120 {
 121         usb_brg_adrdec_setup();
 122
 123         *hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);
 124         *hcor = (struct ehci_hcor *)((uint32_t) *hccr
 125                         + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
 126
 127         debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
 128                 (uint32_t)*hccr, (uint32_t)*hcor,
 129                 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
 130
 131         return 0;
 132 }
 133
 134 /*
 135  * Destroy the appropriate control structures corresponding
 136  * the the EHCI host controller.
 137  */
 138 int ehci_hcd_stop(int index)
 139 {
 140         return 0;
 141 }