3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/mbus.h>
14 #include <asm/arch/cpu.h>
16 #if defined(CONFIG_KIRKWOOD)
17 #include <asm/arch/soc.h>
18 #elif defined(CONFIG_ORION5X)
19 #include <asm/arch/orion5x.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 #define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4))
25 #define USB_WINDOW_BASE(i) (0x324 + ((i) << 4))
26 #define USB_TARGET_DRAM 0x0
29 * USB 2.0 Bridge Address Decoding registers setup
31 #ifdef CONFIG_ARMADA_XP
34 * Armada XP and Armada 38x have different base addresses for
35 * the USB 2.0 EHCI host controller. So we need to provide
36 * a mechnism to support both here.
39 (mvebu_soc_family() == MVEBU_SOC_A38X ? \
40 MVEBU_USB20_BASE : MVEBU_AXP_USB_BASE)
41 #define MVUSB_BASE(port) MVUSB0_BASE + ((port) << 12)
44 * Once all the older Marvell SoC's (Orion, Kirkwood) are converted
45 * to the common mvebu archticture including the mbus setup, this
46 * will be the only function needed to configure the access windows
48 static void usb_brg_adrdec_setup(int index)
50 const struct mbus_dram_target_info *dram;
53 dram = mvebu_mbus_dram_info();
55 for (i = 0; i < 4; i++) {
56 writel(0, MVUSB_BASE(index) + USB_WINDOW_CTRL(i));
57 writel(0, MVUSB_BASE(index) + USB_WINDOW_BASE(i));
60 for (i = 0; i < dram->num_cs; i++) {
61 const struct mbus_dram_window *cs = dram->cs + i;
63 /* Write size, attributes and target id to control register */
64 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
65 (dram->mbus_dram_target_id << 4) | 1,
66 MVUSB_BASE(index) + USB_WINDOW_CTRL(i));
68 /* Write base address to base register */
69 writel(cs->base, MVUSB_BASE(index) + USB_WINDOW_BASE(i));
73 #define MVUSB_BASE(port) MVUSB0_BASE
75 static void usb_brg_adrdec_setup(int index)
78 u32 size, base, attrib;
80 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
82 /* Enable DRAM bank */
85 attrib = MVUSB0_CPU_ATTR_DRAM_CS0;
88 attrib = MVUSB0_CPU_ATTR_DRAM_CS1;
91 attrib = MVUSB0_CPU_ATTR_DRAM_CS2;
94 attrib = MVUSB0_CPU_ATTR_DRAM_CS3;
97 /* invalide bank, disable access */
102 size = gd->bd->bi_dram[i].size;
103 base = gd->bd->bi_dram[i].start;
104 if ((size) && (attrib))
105 writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
106 attrib, MVCPU_WIN_ENABLE),
107 MVUSB0_BASE + USB_WINDOW_CTRL(i));
109 writel(MVCPU_WIN_DISABLE,
110 MVUSB0_BASE + USB_WINDOW_CTRL(i));
112 writel(base, MVUSB0_BASE + USB_WINDOW_BASE(i));
118 * Create the appropriate control structures to manage
119 * a new EHCI host controller.
121 int ehci_hcd_init(int index, enum usb_init_type init,
122 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
124 usb_brg_adrdec_setup(index);
126 *hccr = (struct ehci_hccr *)(MVUSB_BASE(index) + 0x100);
127 *hcor = (struct ehci_hcor *)((uint32_t) *hccr
128 + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
130 debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
131 (uint32_t)*hccr, (uint32_t)*hcor,
132 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
138 * Destroy the appropriate control structures corresponding
139 * the the EHCI host controller.
141 int ehci_hcd_stop(int index)