drivers/usb/host/ehci-marvell.c

   1 /*
   2  * (C) Copyright 2009
   3  * Marvell Semiconductor <www.marvell.com>
   4  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <usb.h>
  12 #include "ehci.h"
  13 #include <linux/mbus.h>
  14 #include <asm/arch/cpu.h>
  15
  16 #if defined(CONFIG_KIRKWOOD)
  17 #include <asm/arch/soc.h>
  18 #elif defined(CONFIG_ORION5X)
  19 #include <asm/arch/orion5x.h>
  20 #endif
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #define rdl(off)        readl(MVUSB0_BASE + (off))
  25 #define wrl(off, val)   writel((val), MVUSB0_BASE + (off))
  26
  27 #define USB_WINDOW_CTRL(i)      (0x320 + ((i) << 4))
  28 #define USB_WINDOW_BASE(i)      (0x324 + ((i) << 4))
  29 #define USB_TARGET_DRAM         0x0
  30
  31 /*
  32  * USB 2.0 Bridge Address Decoding registers setup
  33  */
  34 #ifdef CONFIG_ARMADA_XP
  35
  36 #define MVUSB0_BASE             MVEBU_USB20_BASE
  37
  38 /*
  39  * Once all the older Marvell SoC's (Orion, Kirkwood) are converted
  40  * to the common mvebu archticture including the mbus setup, this
  41  * will be the only function needed to configure the access windows
  42  */
  43 static void usb_brg_adrdec_setup(void)
  44 {
  45         const struct mbus_dram_target_info *dram;
  46         int i;
  47
  48         dram = mvebu_mbus_dram_info();
  49
  50         for (i = 0; i < 4; i++) {
  51                 wrl(USB_WINDOW_CTRL(i), 0);
  52                 wrl(USB_WINDOW_BASE(i), 0);
  53         }
  54
  55         for (i = 0; i < dram->num_cs; i++) {
  56                 const struct mbus_dram_window *cs = dram->cs + i;
  57
  58                 /* Write size, attributes and target id to control register */
  59                 wrl(USB_WINDOW_CTRL(i),
  60                     ((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
  61                     (dram->mbus_dram_target_id << 4) | 1);
  62
  63                 /* Write base address to base register */
  64                 wrl(USB_WINDOW_BASE(i), cs->base);
  65         }
  66 }
  67 #else
  68 static void usb_brg_adrdec_setup(void)
  69 {
  70         int i;
  71         u32 size, base, attrib;
  72
  73         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  74
  75                 /* Enable DRAM bank */
  76                 switch (i) {
  77                 case 0:
  78                         attrib = MVUSB0_CPU_ATTR_DRAM_CS0;
  79                         break;
  80                 case 1:
  81                         attrib = MVUSB0_CPU_ATTR_DRAM_CS1;
  82                         break;
  83                 case 2:
  84                         attrib = MVUSB0_CPU_ATTR_DRAM_CS2;
  85                         break;
  86                 case 3:
  87                         attrib = MVUSB0_CPU_ATTR_DRAM_CS3;
  88                         break;
  89                 default:
  90                         /* invalide bank, disable access */
  91                         attrib = 0;
  92                         break;
  93                 }
  94
  95                 size = gd->bd->bi_dram[i].size;
  96                 base = gd->bd->bi_dram[i].start;
  97                 if ((size) && (attrib))
  98                         wrl(USB_WINDOW_CTRL(i),
  99                                 MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
 100                                         attrib, MVCPU_WIN_ENABLE));
 101                 else
 102                         wrl(USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
 103
 104                 wrl(USB_WINDOW_BASE(i), base);
 105         }
 106 }
 107 #endif
 108
 109 /*
 110  * Create the appropriate control structures to manage
 111  * a new EHCI host controller.
 112  */
 113 int ehci_hcd_init(int index, enum usb_init_type init,
 114                 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 115 {
 116         usb_brg_adrdec_setup();
 117
 118         *hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);
 119         *hcor = (struct ehci_hcor *)((uint32_t) *hccr
 120                         + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
 121
 122         debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
 123                 (uint32_t)*hccr, (uint32_t)*hcor,
 124                 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
 125
 126         return 0;
 127 }
 128
 129 /*
 130  * Destroy the appropriate control structures corresponding
 131  * the the EHCI host controller.
 132  */
 133 int ehci_hcd_stop(int index)
 134 {
 135         return 0;
 136 }