2 * Copyright (c) 2007-2008, Juniper Networks, Inc.
3 * Copyright (c) 2008, Excito Elektronik i Skåne AB
4 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2 of
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/byteorder.h>
33 struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
34 volatile struct ehci_hcor *hcor;
36 static uint16_t portreset;
37 static struct QH qh_list __attribute__((aligned(32)));
39 static struct descriptor {
40 struct usb_hub_descriptor hub;
41 struct usb_device_descriptor device;
42 struct usb_linux_config_descriptor config;
43 struct usb_linux_interface_descriptor interface;
44 struct usb_endpoint_descriptor endpoint;
45 } __attribute__ ((packed)) descriptor = {
47 0x8, /* bDescLength */
48 0x29, /* bDescriptorType: hub descriptor */
49 2, /* bNrPorts -- runtime modified */
50 0, /* wHubCharacteristics */
51 10, /* bPwrOn2PwrGood */
52 0, /* bHubCntrCurrent */
53 {}, /* Device removable */
54 {} /* at most 7 ports! XXX */
58 1, /* bDescriptorType: UDESC_DEVICE */
59 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
60 9, /* bDeviceClass: UDCLASS_HUB */
61 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
62 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
63 64, /* bMaxPacketSize: 64 bytes */
64 0x0000, /* idVendor */
65 0x0000, /* idProduct */
66 cpu_to_le16(0x0100), /* bcdDevice */
67 1, /* iManufacturer */
69 0, /* iSerialNumber */
70 1 /* bNumConfigurations: 1 */
74 2, /* bDescriptorType: UDESC_CONFIG */
76 1, /* bNumInterface */
77 1, /* bConfigurationValue */
78 0, /* iConfiguration */
79 0x40, /* bmAttributes: UC_SELF_POWER */
84 4, /* bDescriptorType: UDESC_INTERFACE */
85 0, /* bInterfaceNumber */
86 0, /* bAlternateSetting */
87 1, /* bNumEndpoints */
88 9, /* bInterfaceClass: UICLASS_HUB */
89 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
90 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
95 5, /* bDescriptorType: UDESC_ENDPOINT */
96 0x81, /* bEndpointAddress:
97 * UE_DIR_IN | EHCI_INTR_ENDPT
99 3, /* bmAttributes: UE_INTERRUPT */
100 8, /* wMaxPacketSize */
105 #if defined(CONFIG_EHCI_IS_TDI)
106 #define ehci_is_TDI() (1)
108 #define ehci_is_TDI() (0)
111 #if defined(CONFIG_EHCI_DCACHE)
113 * Routines to handle (flush/invalidate) the dcache for the QH and qTD
114 * structures and data buffers. This is needed on platforms using this
115 * EHCI support with dcache enabled.
117 static void flush_invalidate(u32 addr, int size, int flush)
120 flush_dcache_range(addr, addr + size);
122 invalidate_dcache_range(addr, addr + size);
125 static void cache_qtd(struct qTD *qtd, int flush)
127 u32 *ptr = (u32 *)qtd->qt_buffer[0];
128 int len = (qtd->qt_token & 0x7fff0000) >> 16;
130 flush_invalidate((u32)qtd, sizeof(struct qTD), flush);
132 flush_invalidate((u32)ptr, len, flush);
136 static inline struct QH *qh_addr(struct QH *qh)
138 return (struct QH *)((u32)qh & 0xffffffe0);
141 static void cache_qh(struct QH *qh, int flush)
145 static struct qTD *first_qtd;
148 * Walk the QH list and flush/invalidate all entries
151 flush_invalidate((u32)qh_addr(qh), sizeof(struct QH), flush);
152 if ((u32)qh & QH_LINK_TYPE_QH)
155 qh = (struct QH *)qh->qh_link;
160 * Save first qTD pointer, needed for invalidating pass on this QH
163 first_qtd = qtd = (struct qTD *)(*(u32 *)&qh->qh_overlay &
169 * Walk the qTD list and flush/invalidate all entries
174 cache_qtd(qtd, flush);
175 next = (struct qTD *)((u32)qtd->qt_next & 0xffffffe0);
182 static inline void ehci_flush_dcache(struct QH *qh)
187 static inline void ehci_invalidate_dcache(struct QH *qh)
191 #else /* CONFIG_EHCI_DCACHE */
195 static inline void ehci_flush_dcache(struct QH *qh)
199 static inline void ehci_invalidate_dcache(struct QH *qh)
202 #endif /* CONFIG_EHCI_DCACHE */
204 void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
209 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
210 __attribute__((weak, alias("__ehci_powerup_fixup")));
212 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
216 result = ehci_readl(ptr);
218 if (result == ~(uint32_t)0)
228 static void ehci_free(void *p, size_t sz)
233 static int ehci_reset(void)
240 cmd = ehci_readl(&hcor->or_usbcmd);
241 cmd = (cmd & ~CMD_RUN) | CMD_RESET;
242 ehci_writel(&hcor->or_usbcmd, cmd);
243 ret = handshake((uint32_t *)&hcor->or_usbcmd, CMD_RESET, 0, 250 * 1000);
245 printf("EHCI fail to reset\n");
250 reg_ptr = (uint32_t *)((u8 *)hcor + USBMODE);
251 tmp = ehci_readl(reg_ptr);
252 tmp |= USBMODE_CM_HC;
253 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
256 ehci_writel(reg_ptr, tmp);
259 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
260 cmd = ehci_readl(&hcor->or_txfilltuning);
261 cmd &= ~TXFIFO_THRESH(0x3f);
262 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
263 ehci_writel(&hcor->or_txfilltuning, cmd);
269 static void *ehci_alloc(size_t sz, size_t align)
271 static struct QH qh __attribute__((aligned(32)));
272 static struct qTD td[3] __attribute__((aligned (32)));
277 case sizeof(struct QH):
281 case sizeof(struct qTD):
283 debug("out of TDs\n");
290 debug("unknown allocation size\n");
298 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
300 uint32_t addr, delta, next;
303 addr = (uint32_t) buf;
306 td->qt_buffer[idx] = cpu_to_hc32(addr);
307 td->qt_buffer_hi[idx] = 0;
308 next = (addr + 4096) & ~4095;
318 debug("out of buffer pointers (%u bytes left)\n", sz);
326 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
327 int length, struct devrequest *req)
331 volatile struct qTD *vtd;
334 uint32_t endpt, token, usbsts;
340 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
341 buffer, length, req);
343 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
344 req->request, req->request,
345 req->requesttype, req->requesttype,
346 le16_to_cpu(req->value), le16_to_cpu(req->value),
347 le16_to_cpu(req->index));
349 qh = ehci_alloc(sizeof(struct QH), 32);
351 debug("unable to allocate QH\n");
354 qh->qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
355 c = (usb_pipespeed(pipe) != USB_SPEED_HIGH &&
356 usb_pipeendpoint(pipe) == 0) ? 1 : 0;
359 (usb_maxpacket(dev, pipe) << 16) |
362 (usb_pipespeed(pipe) << 12) |
363 (usb_pipeendpoint(pipe) << 8) |
364 (0 << 7) | (usb_pipedevice(pipe) << 0);
365 qh->qh_endpt1 = cpu_to_hc32(endpt);
367 (dev->portnr << 23) |
368 (dev->parent->devnum << 16) | (0 << 8) | (0 << 0);
369 qh->qh_endpt2 = cpu_to_hc32(endpt);
370 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
373 tdp = &qh->qh_overlay.qt_next;
376 usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
379 td = ehci_alloc(sizeof(struct qTD), 32);
381 debug("unable to allocate SETUP td\n");
384 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
385 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
387 (sizeof(*req) << 16) |
388 (0 << 15) | (0 << 12) | (3 << 10) | (2 << 8) | (0x80 << 0);
389 td->qt_token = cpu_to_hc32(token);
390 if (ehci_td_buffer(td, req, sizeof(*req)) != 0) {
391 debug("unable construct SETUP td\n");
392 ehci_free(td, sizeof(*td));
395 *tdp = cpu_to_hc32((uint32_t) td);
400 if (length > 0 || req == NULL) {
401 td = ehci_alloc(sizeof(struct qTD), 32);
403 debug("unable to allocate DATA td\n");
406 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
407 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
408 token = (toggle << 31) |
410 ((req == NULL ? 1 : 0) << 15) |
413 ((usb_pipein(pipe) ? 1 : 0) << 8) | (0x80 << 0);
414 td->qt_token = cpu_to_hc32(token);
415 if (ehci_td_buffer(td, buffer, length) != 0) {
416 debug("unable construct DATA td\n");
417 ehci_free(td, sizeof(*td));
420 *tdp = cpu_to_hc32((uint32_t) td);
425 td = ehci_alloc(sizeof(struct qTD), 32);
427 debug("unable to allocate ACK td\n");
430 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
431 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
432 token = (toggle << 31) |
437 ((usb_pipein(pipe) ? 0 : 1) << 8) | (0x80 << 0);
438 td->qt_token = cpu_to_hc32(token);
439 *tdp = cpu_to_hc32((uint32_t) td);
443 qh_list.qh_link = cpu_to_hc32((uint32_t) qh | QH_LINK_TYPE_QH);
446 ehci_flush_dcache(&qh_list);
448 usbsts = ehci_readl(&hcor->or_usbsts);
449 ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f));
451 /* Enable async. schedule. */
452 cmd = ehci_readl(&hcor->or_usbcmd);
454 ehci_writel(&hcor->or_usbcmd, cmd);
456 ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, STD_ASS,
459 printf("EHCI fail timeout STD_ASS set\n");
463 /* Wait for TDs to be processed. */
466 timeout = USB_TIMEOUT_MS(pipe);
468 /* Invalidate dcache */
469 ehci_invalidate_dcache(&qh_list);
470 token = hc32_to_cpu(vtd->qt_token);
474 } while (get_timer(ts) < timeout);
476 /* Check that the TD processing happened */
478 printf("EHCI timed out on TD - token=%#x\n", token);
481 /* Disable async schedule. */
482 cmd = ehci_readl(&hcor->or_usbcmd);
484 ehci_writel(&hcor->or_usbcmd, cmd);
486 ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, 0,
489 printf("EHCI fail timeout STD_ASS reset\n");
493 qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
495 token = hc32_to_cpu(qh->qh_overlay.qt_token);
496 if (!(token & 0x80)) {
497 debug("TOKEN=%#x\n", token);
498 switch (token & 0xfc) {
500 toggle = token >> 31;
501 usb_settoggle(dev, usb_pipeendpoint(pipe),
502 usb_pipeout(pipe), toggle);
506 dev->status = USB_ST_STALLED;
510 dev->status = USB_ST_BUF_ERR;
514 dev->status = USB_ST_BABBLE_DET;
517 dev->status = USB_ST_CRC_ERR;
518 if ((token & 0x40) == 0x40)
519 dev->status |= USB_ST_STALLED;
522 dev->act_len = length - ((token >> 16) & 0x7fff);
525 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
526 dev->devnum, ehci_readl(&hcor->or_usbsts),
527 ehci_readl(&hcor->or_portsc[0]),
528 ehci_readl(&hcor->or_portsc[1]));
531 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
534 td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next);
535 while (td != (void *)QT_NEXT_TERMINATE) {
536 qh->qh_overlay.qt_next = td->qt_next;
537 ehci_free(td, sizeof(*td));
538 td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next);
540 ehci_free(qh, sizeof(*qh));
544 static inline int min3(int a, int b, int c)
555 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
556 int length, struct devrequest *req)
563 uint32_t *status_reg;
565 if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
566 printf("The request port(%d) is not configured\n",
567 le16_to_cpu(req->index) - 1);
570 status_reg = (uint32_t *)&hcor->or_portsc[
571 le16_to_cpu(req->index) - 1];
574 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
575 req->request, req->request,
576 req->requesttype, req->requesttype,
577 le16_to_cpu(req->value), le16_to_cpu(req->index));
579 typeReq = req->request | req->requesttype << 8;
582 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
583 switch (le16_to_cpu(req->value) >> 8) {
585 debug("USB_DT_DEVICE request\n");
586 srcptr = &descriptor.device;
590 debug("USB_DT_CONFIG config\n");
591 srcptr = &descriptor.config;
595 debug("USB_DT_STRING config\n");
596 switch (le16_to_cpu(req->value) & 0xff) {
597 case 0: /* Language */
602 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
605 case 2: /* Product */
606 srcptr = "\52\3E\0H\0C\0I\0 "
608 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
612 debug("unknown value DT_STRING %x\n",
613 le16_to_cpu(req->value));
618 debug("unknown value %x\n", le16_to_cpu(req->value));
622 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
623 switch (le16_to_cpu(req->value) >> 8) {
625 debug("USB_DT_HUB config\n");
626 srcptr = &descriptor.hub;
630 debug("unknown value %x\n", le16_to_cpu(req->value));
634 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
635 debug("USB_REQ_SET_ADDRESS\n");
636 rootdev = le16_to_cpu(req->value);
638 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
639 debug("USB_REQ_SET_CONFIGURATION\n");
642 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
643 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
648 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
649 memset(tmpbuf, 0, 4);
650 reg = ehci_readl(status_reg);
651 if (reg & EHCI_PS_CS)
652 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
653 if (reg & EHCI_PS_PE)
654 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
655 if (reg & EHCI_PS_SUSP)
656 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
657 if (reg & EHCI_PS_OCA)
658 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
659 if (reg & EHCI_PS_PR)
660 tmpbuf[0] |= USB_PORT_STAT_RESET;
661 if (reg & EHCI_PS_PP)
662 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
665 switch ((reg >> 26) & 3) {
669 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
673 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
677 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
680 if (reg & EHCI_PS_CSC)
681 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
682 if (reg & EHCI_PS_PEC)
683 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
684 if (reg & EHCI_PS_OCC)
685 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
686 if (portreset & (1 << le16_to_cpu(req->index)))
687 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
692 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
693 reg = ehci_readl(status_reg);
694 reg &= ~EHCI_PS_CLEAR;
695 switch (le16_to_cpu(req->value)) {
696 case USB_PORT_FEAT_ENABLE:
698 ehci_writel(status_reg, reg);
700 case USB_PORT_FEAT_POWER:
701 if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) {
703 ehci_writel(status_reg, reg);
706 case USB_PORT_FEAT_RESET:
707 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
709 EHCI_PS_IS_LOWSPEED(reg)) {
710 /* Low speed device, give up ownership. */
711 debug("port %d low speed --> companion\n",
714 ehci_writel(status_reg, reg);
721 ehci_writel(status_reg, reg);
723 * caller must wait, then call GetPortStatus
724 * usb 2.0 specification say 50 ms resets on
727 ehci_powerup_fixup(status_reg, ®);
729 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
731 * A host controller must terminate the reset
732 * and stabilize the state of the port within
735 ret = handshake(status_reg, EHCI_PS_PR, 0,
739 1 << le16_to_cpu(req->index);
741 printf("port(%d) reset error\n",
742 le16_to_cpu(req->index) - 1);
746 debug("unknown feature %x\n", le16_to_cpu(req->value));
749 /* unblock posted writes */
750 (void) ehci_readl(&hcor->or_usbcmd);
752 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
753 reg = ehci_readl(status_reg);
754 switch (le16_to_cpu(req->value)) {
755 case USB_PORT_FEAT_ENABLE:
758 case USB_PORT_FEAT_C_ENABLE:
759 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE;
761 case USB_PORT_FEAT_POWER:
762 if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams)))
763 reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP);
764 case USB_PORT_FEAT_C_CONNECTION:
765 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC;
767 case USB_PORT_FEAT_OVER_CURRENT:
768 reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC;
770 case USB_PORT_FEAT_C_RESET:
771 portreset &= ~(1 << le16_to_cpu(req->index));
774 debug("unknown feature %x\n", le16_to_cpu(req->value));
777 ehci_writel(status_reg, reg);
778 /* unblock posted write */
779 (void) ehci_readl(&hcor->or_usbcmd);
782 debug("Unknown request\n");
787 len = min3(srclen, le16_to_cpu(req->length), length);
788 if (srcptr != NULL && len > 0)
789 memcpy(buffer, srcptr, len);
798 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
799 req->requesttype, req->request, le16_to_cpu(req->value),
800 le16_to_cpu(req->index), le16_to_cpu(req->length));
803 dev->status = USB_ST_STALLED;
807 int usb_lowlevel_stop(void)
809 return ehci_hcd_stop();
812 int usb_lowlevel_init(void)
817 if (ehci_hcd_init() != 0)
820 /* EHCI spec section 4.1 */
821 if (ehci_reset() != 0)
824 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
825 if (ehci_hcd_init() != 0)
829 /* Set head of reclaim list */
830 memset(&qh_list, 0, sizeof(qh_list));
831 qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
832 qh_list.qh_endpt1 = cpu_to_hc32((1 << 15) | (USB_SPEED_HIGH << 12));
833 qh_list.qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
834 qh_list.qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
835 qh_list.qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
836 qh_list.qh_overlay.qt_token = cpu_to_hc32(0x40);
838 /* Set async. queue head pointer. */
839 ehci_writel(&hcor->or_asynclistaddr, (uint32_t)&qh_list);
841 reg = ehci_readl(&hccr->cr_hcsparams);
842 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
843 printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
844 /* Port Indicators */
845 if (HCS_INDICATOR(reg))
846 descriptor.hub.wHubCharacteristics |= 0x80;
847 /* Port Power Control */
849 descriptor.hub.wHubCharacteristics |= 0x01;
851 /* Start the host controller. */
852 cmd = ehci_readl(&hcor->or_usbcmd);
854 * Philips, Intel, and maybe others need CMD_RUN before the
855 * root hub will detect new devices (why?); NEC doesn't
857 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
859 ehci_writel(&hcor->or_usbcmd, cmd);
861 /* take control over the ports */
862 cmd = ehci_readl(&hcor->or_configflag);
864 ehci_writel(&hcor->or_configflag, cmd);
865 /* unblock posted write */
866 cmd = ehci_readl(&hcor->or_usbcmd);
868 reg = HC_VERSION(ehci_readl(&hccr->cr_capbase));
869 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
877 submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
881 if (usb_pipetype(pipe) != PIPE_BULK) {
882 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
885 return ehci_submit_async(dev, pipe, buffer, length, NULL);
889 submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
890 int length, struct devrequest *setup)
893 if (usb_pipetype(pipe) != PIPE_CONTROL) {
894 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
898 if (usb_pipedevice(pipe) == rootdev) {
900 dev->speed = USB_SPEED_HIGH;
901 return ehci_submit_root(dev, pipe, buffer, length, setup);
903 return ehci_submit_async(dev, pipe, buffer, length, setup);
907 submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
908 int length, int interval)
911 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
912 dev, pipe, buffer, length, interval);
913 return ehci_submit_async(dev, pipe, buffer, length, NULL);