1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2007-2008, Juniper Networks, Inc.
4 * Copyright (c) 2008, Excito Elektronik i Skåne AB
5 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
12 #include <asm/byteorder.h>
13 #include <asm/unaligned.h>
19 #include <linux/compiler.h>
23 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
24 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
28 * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt.
29 * Let's time out after 8 to have a little safety margin on top of that.
31 #define HCHALT_TIMEOUT (8 * 1000)
33 #if !CONFIG_IS_ENABLED(DM_USB)
34 static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
37 #define ALIGN_END_ADDR(type, ptr, size) \
38 ((unsigned long)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
40 static struct descriptor {
41 struct usb_hub_descriptor hub;
42 struct usb_device_descriptor device;
43 struct usb_linux_config_descriptor config;
44 struct usb_linux_interface_descriptor interface;
45 struct usb_endpoint_descriptor endpoint;
46 } __attribute__ ((packed)) descriptor = {
48 0x8, /* bDescLength */
49 0x29, /* bDescriptorType: hub descriptor */
50 2, /* bNrPorts -- runtime modified */
51 0, /* wHubCharacteristics */
52 10, /* bPwrOn2PwrGood */
53 0, /* bHubCntrCurrent */
54 { /* Device removable */
55 } /* at most 7 ports! XXX */
59 1, /* bDescriptorType: UDESC_DEVICE */
60 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
61 9, /* bDeviceClass: UDCLASS_HUB */
62 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
63 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
64 64, /* bMaxPacketSize: 64 bytes */
65 0x0000, /* idVendor */
66 0x0000, /* idProduct */
67 cpu_to_le16(0x0100), /* bcdDevice */
68 1, /* iManufacturer */
70 0, /* iSerialNumber */
71 1 /* bNumConfigurations: 1 */
75 2, /* bDescriptorType: UDESC_CONFIG */
77 1, /* bNumInterface */
78 1, /* bConfigurationValue */
79 0, /* iConfiguration */
80 0x40, /* bmAttributes: UC_SELF_POWER */
85 4, /* bDescriptorType: UDESC_INTERFACE */
86 0, /* bInterfaceNumber */
87 0, /* bAlternateSetting */
88 1, /* bNumEndpoints */
89 9, /* bInterfaceClass: UICLASS_HUB */
90 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
91 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
96 5, /* bDescriptorType: UDESC_ENDPOINT */
97 0x81, /* bEndpointAddress:
98 * UE_DIR_IN | EHCI_INTR_ENDPT
100 3, /* bmAttributes: UE_INTERRUPT */
101 8, /* wMaxPacketSize */
106 #if defined(CONFIG_EHCI_IS_TDI)
107 #define ehci_is_TDI() (1)
109 #define ehci_is_TDI() (0)
112 static struct ehci_ctrl *ehci_get_ctrl(struct usb_device *udev)
114 #if CONFIG_IS_ENABLED(DM_USB)
115 return dev_get_priv(usb_get_bus(udev->dev));
117 return udev->controller;
121 static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
123 return PORTSC_PSPD(reg);
126 static void ehci_set_usbmode(struct ehci_ctrl *ctrl)
131 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE);
132 tmp = ehci_readl(reg_ptr);
133 tmp |= USBMODE_CM_HC;
134 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
139 ehci_writel(reg_ptr, tmp);
142 static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
148 static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port)
150 int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
152 if (port < 0 || port >= max_ports) {
153 /* Printing the message would cause a scan failure! */
154 debug("The request port(%u) exceeds maximum port number\n",
159 return (uint32_t *)&ctrl->hcor->or_portsc[port];
162 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
166 result = ehci_readl(ptr);
168 if (result == ~(uint32_t)0)
178 static int ehci_reset(struct ehci_ctrl *ctrl)
183 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
184 cmd = (cmd & ~CMD_RUN) | CMD_RESET;
185 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
186 ret = handshake((uint32_t *)&ctrl->hcor->or_usbcmd,
187 CMD_RESET, 0, 250 * 1000);
189 printf("EHCI fail to reset\n");
194 ctrl->ops.set_usb_mode(ctrl);
196 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
197 cmd = ehci_readl(&ctrl->hcor->or_txfilltuning);
198 cmd &= ~TXFIFO_THRESH_MASK;
199 cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
200 ehci_writel(&ctrl->hcor->or_txfilltuning, cmd);
206 static int ehci_shutdown(struct ehci_ctrl *ctrl)
210 int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
212 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
213 /* If not run, directly return */
214 if (!(cmd & CMD_RUN))
216 cmd &= ~(CMD_PSE | CMD_ASE);
217 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
218 ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0,
222 for (i = 0; i < max_ports; i++) {
223 reg = ehci_readl(&ctrl->hcor->or_portsc[i]);
225 ehci_writel(&ctrl->hcor->or_portsc[i], reg);
229 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
230 ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT,
235 puts("EHCI failed to shut down host controller.\n");
240 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
242 uint32_t delta, next;
243 unsigned long addr = (unsigned long)buf;
246 if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
247 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
249 flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
252 while (idx < QT_BUFFER_CNT) {
253 td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr));
254 td->qt_buffer_hi[idx] = 0;
255 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
264 if (idx == QT_BUFFER_CNT) {
265 printf("out of buffer pointers (%zu bytes left)\n", sz);
272 static inline u8 ehci_encode_speed(enum usb_device_speed speed)
274 #define QH_HIGH_SPEED 2
275 #define QH_FULL_SPEED 0
276 #define QH_LOW_SPEED 1
277 if (speed == USB_SPEED_HIGH)
278 return QH_HIGH_SPEED;
279 if (speed == USB_SPEED_LOW)
281 return QH_FULL_SPEED;
284 static void ehci_update_endpt2_dev_n_port(struct usb_device *udev,
290 if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL)
293 usb_find_usb2_hub_address_port(udev, &hubaddr, &portnr);
295 qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(portnr) |
296 QH_ENDPT2_HUBADDR(hubaddr));
300 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
301 int length, struct devrequest *req)
303 ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
307 volatile struct qTD *vtd;
310 uint32_t endpt, maxpacket, token, usbsts;
315 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
317 debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
318 buffer, length, req);
320 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
321 req->request, req->request,
322 req->requesttype, req->requesttype,
323 le16_to_cpu(req->value), le16_to_cpu(req->value),
324 le16_to_cpu(req->index));
326 #define PKT_ALIGN 512
328 * The USB transfer is split into qTD transfers. Eeach qTD transfer is
329 * described by a transfer descriptor (the qTD). The qTDs form a linked
330 * list with a queue head (QH).
332 * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
333 * have its beginning in a qTD transfer and its end in the following
334 * one, so the qTD transfer lengths have to be chosen accordingly.
336 * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
337 * single pages. The first data buffer can start at any offset within a
338 * page (not considering the cache-line alignment issues), while the
339 * following buffers must be page-aligned. There is no alignment
340 * constraint on the size of a qTD transfer.
343 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
345 if (length > 0 || req == NULL) {
347 * Determine the qTD transfer size that will be used for the
348 * data payload (not considering the first qTD transfer, which
349 * may be longer or shorter, and the final one, which may be
352 * In order to keep each packet within a qTD transfer, the qTD
353 * transfer size is aligned to PKT_ALIGN, which is a multiple of
354 * wMaxPacketSize (except in some cases for interrupt transfers,
355 * see comment in submit_int_msg()).
357 * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
358 * QT_BUFFER_CNT full pages will be used.
360 int xfr_sz = QT_BUFFER_CNT;
362 * However, if the input buffer is not aligned to PKT_ALIGN, the
363 * qTD transfer size will be one page shorter, and the first qTD
364 * data buffer of each transfer will be page-unaligned.
366 if ((unsigned long)buffer & (PKT_ALIGN - 1))
368 /* Convert the qTD transfer size to bytes. */
369 xfr_sz *= EHCI_PAGE_SIZE;
371 * Approximate by excess the number of qTDs that will be
372 * required for the data payload. The exact formula is way more
373 * complicated and saves at most 2 qTDs, i.e. a total of 128
376 qtd_count += 2 + length / xfr_sz;
379 * Threshold value based on the worst-case total size of the allocated qTDs for
380 * a mass-storage transfer of 65535 blocks of 512 bytes.
382 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
383 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
385 qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
387 printf("unable to allocate TDs\n");
391 memset(qh, 0, sizeof(struct QH));
392 memset(qtd, 0, qtd_count * sizeof(*qtd));
394 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
397 * Setup QH (3.6 in ehci-r10.pdf)
399 * qh_link ................. 03-00 H
400 * qh_endpt1 ............... 07-04 H
401 * qh_endpt2 ............... 0B-08 H
403 * qh_overlay.qt_next ...... 13-10 H
404 * - qh_overlay.qt_altnext
406 qh->qh_link = cpu_to_hc32(virt_to_phys(&ctrl->qh_list) | QH_LINK_TYPE_QH);
407 c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
408 maxpacket = usb_maxpacket(dev, pipe);
409 endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
410 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
411 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
412 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
413 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
415 /* Force FS for fsl HS quirk */
416 if (!ctrl->has_fsl_erratum_a005275)
417 endpt |= QH_ENDPT1_EPS(ehci_encode_speed(dev->speed));
419 endpt |= QH_ENDPT1_EPS(ehci_encode_speed(QH_FULL_SPEED));
421 qh->qh_endpt1 = cpu_to_hc32(endpt);
422 endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
423 qh->qh_endpt2 = cpu_to_hc32(endpt);
424 ehci_update_endpt2_dev_n_port(dev, qh);
425 qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
426 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
428 tdp = &qh->qh_overlay.qt_next;
431 * Setup request qTD (3.5 in ehci-r10.pdf)
433 * qt_next ................ 03-00 H
434 * qt_altnext ............. 07-04 H
435 * qt_token ............... 0B-08 H
437 * [ buffer, buffer_hi ] loaded with "req".
439 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
440 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
441 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
442 QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
443 QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
444 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
445 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
446 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
447 printf("unable to construct SETUP TD\n");
450 /* Update previous qTD! */
451 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
452 tdp = &qtd[qtd_counter++].qt_next;
456 if (length > 0 || req == NULL) {
457 uint8_t *buf_ptr = buffer;
458 int left_length = length;
462 * Determine the size of this qTD transfer. By default,
463 * QT_BUFFER_CNT full pages can be used.
465 int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
467 * However, if the input buffer is not page-aligned, the
468 * portion of the first page before the buffer start
469 * offset within that page is unusable.
471 xfr_bytes -= (unsigned long)buf_ptr & (EHCI_PAGE_SIZE - 1);
473 * In order to keep each packet within a qTD transfer,
474 * align the qTD transfer size to PKT_ALIGN.
476 xfr_bytes &= ~(PKT_ALIGN - 1);
478 * This transfer may be shorter than the available qTD
479 * transfer size that has just been computed.
481 xfr_bytes = min(xfr_bytes, left_length);
484 * Setup request qTD (3.5 in ehci-r10.pdf)
486 * qt_next ................ 03-00 H
487 * qt_altnext ............. 07-04 H
488 * qt_token ............... 0B-08 H
490 * [ buffer, buffer_hi ] loaded with "buffer".
492 qtd[qtd_counter].qt_next =
493 cpu_to_hc32(QT_NEXT_TERMINATE);
494 qtd[qtd_counter].qt_altnext =
495 cpu_to_hc32(QT_NEXT_TERMINATE);
496 token = QT_TOKEN_DT(toggle) |
497 QT_TOKEN_TOTALBYTES(xfr_bytes) |
498 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
500 QT_TOKEN_PID(usb_pipein(pipe) ?
501 QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
502 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
503 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
504 if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
506 printf("unable to construct DATA TD\n");
509 /* Update previous qTD! */
510 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
511 tdp = &qtd[qtd_counter++].qt_next;
513 * Data toggle has to be adjusted since the qTD transfer
514 * size is not always an even multiple of
517 if ((xfr_bytes / maxpacket) & 1)
519 buf_ptr += xfr_bytes;
520 left_length -= xfr_bytes;
521 } while (left_length > 0);
526 * Setup request qTD (3.5 in ehci-r10.pdf)
528 * qt_next ................ 03-00 H
529 * qt_altnext ............. 07-04 H
530 * qt_token ............... 0B-08 H
532 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
533 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
534 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
535 QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
536 QT_TOKEN_PID(usb_pipein(pipe) ?
537 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
538 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
539 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
540 /* Update previous qTD! */
541 *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
542 tdp = &qtd[qtd_counter++].qt_next;
545 ctrl->qh_list.qh_link = cpu_to_hc32(virt_to_phys(qh) | QH_LINK_TYPE_QH);
548 flush_dcache_range((unsigned long)&ctrl->qh_list,
549 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
550 flush_dcache_range((unsigned long)qh, ALIGN_END_ADDR(struct QH, qh, 1));
551 flush_dcache_range((unsigned long)qtd,
552 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
554 /* Set async. queue head pointer. */
555 ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(&ctrl->qh_list));
557 usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
558 ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
560 /* Enable async. schedule. */
561 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
563 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
565 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
568 printf("EHCI fail timeout STS_ASS set\n");
572 /* Wait for TDs to be processed. */
574 vtd = &qtd[qtd_counter - 1];
575 timeout = USB_TIMEOUT_MS(pipe);
577 /* Invalidate dcache */
578 invalidate_dcache_range((unsigned long)&ctrl->qh_list,
579 ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
580 invalidate_dcache_range((unsigned long)qh,
581 ALIGN_END_ADDR(struct QH, qh, 1));
582 invalidate_dcache_range((unsigned long)qtd,
583 ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
585 token = hc32_to_cpu(vtd->qt_token);
586 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
589 } while (get_timer(ts) < timeout);
592 * Invalidate the memory area occupied by buffer
593 * Don't try to fix the buffer alignment, if it isn't properly
594 * aligned it's upper layer's fault so let invalidate_dcache_range()
595 * vow about it. But we have to fix the length as it's actual
596 * transfer length and can be unaligned. This is potentially
597 * dangerous operation, it's responsibility of the calling
598 * code to make sure enough space is reserved.
600 if (buffer != NULL && length > 0)
601 invalidate_dcache_range((unsigned long)buffer,
602 ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN));
604 /* Check that the TD processing happened */
605 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
606 printf("EHCI timed out on TD - token=%#x\n", token);
608 /* Disable async schedule. */
609 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
611 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
613 ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
616 printf("EHCI fail timeout STS_ASS reset\n");
620 token = hc32_to_cpu(qh->qh_overlay.qt_token);
621 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
622 debug("TOKEN=%#x\n", token);
623 switch (QT_TOKEN_GET_STATUS(token) &
624 ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
626 toggle = QT_TOKEN_GET_DT(token);
627 usb_settoggle(dev, usb_pipeendpoint(pipe),
628 usb_pipeout(pipe), toggle);
631 case QT_TOKEN_STATUS_HALTED:
632 dev->status = USB_ST_STALLED;
634 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
635 case QT_TOKEN_STATUS_DATBUFERR:
636 dev->status = USB_ST_BUF_ERR;
638 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
639 case QT_TOKEN_STATUS_BABBLEDET:
640 dev->status = USB_ST_BABBLE_DET;
643 dev->status = USB_ST_CRC_ERR;
644 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
645 dev->status |= USB_ST_STALLED;
648 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
651 #ifndef CONFIG_USB_EHCI_FARADAY
652 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
653 dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
654 ehci_readl(&ctrl->hcor->or_portsc[0]),
655 ehci_readl(&ctrl->hcor->or_portsc[1]));
660 return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
667 static int ehci_submit_root(struct usb_device *dev, unsigned long pipe,
668 void *buffer, int length, struct devrequest *req)
675 uint32_t *status_reg;
676 int port = le16_to_cpu(req->index) & 0xff;
677 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
681 debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
682 req->request, req->request,
683 req->requesttype, req->requesttype,
684 le16_to_cpu(req->value), le16_to_cpu(req->index));
686 typeReq = req->request | req->requesttype << 8;
689 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
690 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
691 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
692 status_reg = ctrl->ops.get_portsc_register(ctrl, port - 1);
702 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
703 switch (le16_to_cpu(req->value) >> 8) {
705 debug("USB_DT_DEVICE request\n");
706 srcptr = &descriptor.device;
707 srclen = descriptor.device.bLength;
710 debug("USB_DT_CONFIG config\n");
711 srcptr = &descriptor.config;
712 srclen = descriptor.config.bLength +
713 descriptor.interface.bLength +
714 descriptor.endpoint.bLength;
717 debug("USB_DT_STRING config\n");
718 switch (le16_to_cpu(req->value) & 0xff) {
719 case 0: /* Language */
724 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
727 case 2: /* Product */
728 srcptr = "\52\3E\0H\0C\0I\0 "
730 "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
734 debug("unknown value DT_STRING %x\n",
735 le16_to_cpu(req->value));
740 debug("unknown value %x\n", le16_to_cpu(req->value));
744 case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
745 switch (le16_to_cpu(req->value) >> 8) {
747 debug("USB_DT_HUB config\n");
748 srcptr = &descriptor.hub;
749 srclen = descriptor.hub.bLength;
752 debug("unknown value %x\n", le16_to_cpu(req->value));
756 case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
757 debug("USB_REQ_SET_ADDRESS\n");
758 ctrl->rootdev = le16_to_cpu(req->value);
760 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
761 debug("USB_REQ_SET_CONFIGURATION\n");
764 case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
765 tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
770 case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
771 memset(tmpbuf, 0, 4);
772 reg = ehci_readl(status_reg);
773 if (reg & EHCI_PS_CS)
774 tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
775 if (reg & EHCI_PS_PE)
776 tmpbuf[0] |= USB_PORT_STAT_ENABLE;
777 if (reg & EHCI_PS_SUSP)
778 tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
779 if (reg & EHCI_PS_OCA)
780 tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
781 if (reg & EHCI_PS_PR)
782 tmpbuf[0] |= USB_PORT_STAT_RESET;
783 if (reg & EHCI_PS_PP)
784 tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
787 switch (ctrl->ops.get_port_speed(ctrl, reg)) {
791 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
795 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
799 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
802 if (reg & EHCI_PS_CSC)
803 tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
804 if (reg & EHCI_PS_PEC)
805 tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
806 if (reg & EHCI_PS_OCC)
807 tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
808 if (ctrl->portreset & (1 << port))
809 tmpbuf[2] |= USB_PORT_STAT_C_RESET;
814 case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
815 reg = ehci_readl(status_reg);
816 reg &= ~EHCI_PS_CLEAR;
817 switch (le16_to_cpu(req->value)) {
818 case USB_PORT_FEAT_ENABLE:
820 ehci_writel(status_reg, reg);
822 case USB_PORT_FEAT_POWER:
823 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
825 ehci_writel(status_reg, reg);
828 case USB_PORT_FEAT_RESET:
829 if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
831 EHCI_PS_IS_LOWSPEED(reg)) {
832 /* Low speed device, give up ownership. */
833 debug("port %d low speed --> companion\n",
836 ehci_writel(status_reg, reg);
841 /* Disable chirp for HS erratum */
842 if (ctrl->has_fsl_erratum_a005275)
843 reg |= PORTSC_FSL_PFSC;
847 ehci_writel(status_reg, reg);
849 * caller must wait, then call GetPortStatus
850 * usb 2.0 specification say 50 ms resets on
853 ctrl->ops.powerup_fixup(ctrl, status_reg, ®);
855 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
857 * A host controller must terminate the reset
858 * and stabilize the state of the port within
861 ret = handshake(status_reg, EHCI_PS_PR, 0,
864 reg = ehci_readl(status_reg);
865 if ((reg & (EHCI_PS_PE | EHCI_PS_CS))
866 == EHCI_PS_CS && !ehci_is_TDI()) {
867 debug("port %d full speed --> companion\n", port - 1);
868 reg &= ~EHCI_PS_CLEAR;
870 ehci_writel(status_reg, reg);
873 ctrl->portreset |= 1 << port;
876 printf("port(%d) reset error\n",
881 case USB_PORT_FEAT_TEST:
884 reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16;
885 ehci_writel(status_reg, reg);
888 debug("unknown feature %x\n", le16_to_cpu(req->value));
891 /* unblock posted writes */
892 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
894 case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
895 reg = ehci_readl(status_reg);
896 reg &= ~EHCI_PS_CLEAR;
897 switch (le16_to_cpu(req->value)) {
898 case USB_PORT_FEAT_ENABLE:
901 case USB_PORT_FEAT_C_ENABLE:
904 case USB_PORT_FEAT_POWER:
905 if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
908 case USB_PORT_FEAT_C_CONNECTION:
911 case USB_PORT_FEAT_OVER_CURRENT:
914 case USB_PORT_FEAT_C_RESET:
915 ctrl->portreset &= ~(1 << port);
918 debug("unknown feature %x\n", le16_to_cpu(req->value));
921 ehci_writel(status_reg, reg);
922 /* unblock posted write */
923 (void) ehci_readl(&ctrl->hcor->or_usbcmd);
926 debug("Unknown request\n");
931 len = min3(srclen, (int)le16_to_cpu(req->length), length);
932 if (srcptr != NULL && len > 0)
933 memcpy(buffer, srcptr, len);
942 debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
943 req->requesttype, req->request, le16_to_cpu(req->value),
944 le16_to_cpu(req->index), le16_to_cpu(req->length));
947 dev->status = USB_ST_STALLED;
951 static const struct ehci_ops default_ehci_ops = {
952 .set_usb_mode = ehci_set_usbmode,
953 .get_port_speed = ehci_get_port_speed,
954 .powerup_fixup = ehci_powerup_fixup,
955 .get_portsc_register = ehci_get_portsc_register,
958 static void ehci_setup_ops(struct ehci_ctrl *ctrl, const struct ehci_ops *ops)
961 ctrl->ops = default_ehci_ops;
964 if (!ctrl->ops.set_usb_mode)
965 ctrl->ops.set_usb_mode = ehci_set_usbmode;
966 if (!ctrl->ops.get_port_speed)
967 ctrl->ops.get_port_speed = ehci_get_port_speed;
968 if (!ctrl->ops.powerup_fixup)
969 ctrl->ops.powerup_fixup = ehci_powerup_fixup;
970 if (!ctrl->ops.get_portsc_register)
971 ctrl->ops.get_portsc_register =
972 ehci_get_portsc_register;
976 #if !CONFIG_IS_ENABLED(DM_USB)
977 void ehci_set_controller_priv(int index, void *priv, const struct ehci_ops *ops)
979 struct ehci_ctrl *ctrl = &ehcic[index];
982 ehci_setup_ops(ctrl, ops);
985 void *ehci_get_controller_priv(int index)
987 return ehcic[index].priv;
991 static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks)
999 /* Set the high address word (aka segment) for 64-bit controller */
1000 if (ehci_readl(&ctrl->hccr->cr_hccparams) & 1)
1001 ehci_writel(&ctrl->hcor->or_ctrldssegment, 0);
1003 qh_list = &ctrl->qh_list;
1005 /* Set head of reclaim list */
1006 memset(qh_list, 0, sizeof(*qh_list));
1007 qh_list->qh_link = cpu_to_hc32(virt_to_phys(qh_list) | QH_LINK_TYPE_QH);
1008 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
1009 QH_ENDPT1_EPS(USB_SPEED_HIGH));
1010 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1011 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1012 qh_list->qh_overlay.qt_token =
1013 cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
1015 flush_dcache_range((unsigned long)qh_list,
1016 ALIGN_END_ADDR(struct QH, qh_list, 1));
1018 /* Set async. queue head pointer. */
1019 ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(qh_list));
1022 * Set up periodic list
1023 * Step 1: Parent QH for all periodic transfers.
1025 ctrl->periodic_schedules = 0;
1026 periodic = &ctrl->periodic_queue;
1027 memset(periodic, 0, sizeof(*periodic));
1028 periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1029 periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1030 periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1032 flush_dcache_range((unsigned long)periodic,
1033 ALIGN_END_ADDR(struct QH, periodic, 1));
1036 * Step 2: Setup frame-list: Every microframe, USB tries the same list.
1037 * In particular, device specifications on polling frequency
1038 * are disregarded. Keyboards seem to send NAK/NYet reliably
1039 * when polled with an empty buffer.
1041 * Split Transactions will be spread across microframes using
1042 * S-mask and C-mask.
1044 if (ctrl->periodic_list == NULL)
1045 ctrl->periodic_list = memalign(4096, 1024 * 4);
1047 if (!ctrl->periodic_list)
1049 for (i = 0; i < 1024; i++) {
1050 ctrl->periodic_list[i] = cpu_to_hc32((unsigned long)periodic
1054 flush_dcache_range((unsigned long)ctrl->periodic_list,
1055 ALIGN_END_ADDR(uint32_t, ctrl->periodic_list,
1058 /* Set periodic list base address */
1059 ehci_writel(&ctrl->hcor->or_periodiclistbase,
1060 (unsigned long)ctrl->periodic_list);
1062 reg = ehci_readl(&ctrl->hccr->cr_hcsparams);
1063 descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
1064 debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
1065 /* Port Indicators */
1066 if (HCS_INDICATOR(reg))
1067 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1068 | 0x80, &descriptor.hub.wHubCharacteristics);
1069 /* Port Power Control */
1071 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
1072 | 0x01, &descriptor.hub.wHubCharacteristics);
1074 /* Start the host controller. */
1075 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1077 * Philips, Intel, and maybe others need CMD_RUN before the
1078 * root hub will detect new devices (why?); NEC doesn't
1080 cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
1082 ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
1084 if (!(tweaks & EHCI_TWEAK_NO_INIT_CF)) {
1085 /* take control over the ports */
1086 cmd = ehci_readl(&ctrl->hcor->or_configflag);
1088 ehci_writel(&ctrl->hcor->or_configflag, cmd);
1091 /* unblock posted write */
1092 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
1094 reg = HC_VERSION(ehci_readl(&ctrl->hccr->cr_capbase));
1095 printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
1100 #if !CONFIG_IS_ENABLED(DM_USB)
1101 int usb_lowlevel_stop(int index)
1103 ehci_shutdown(&ehcic[index]);
1104 return ehci_hcd_stop(index);
1107 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1109 struct ehci_ctrl *ctrl = &ehcic[index];
1114 * Set ops to default_ehci_ops, ehci_hcd_init should call
1115 * ehci_set_controller_priv to change any of these function pointers.
1117 ctrl->ops = default_ehci_ops;
1119 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1122 if (!ctrl->hccr || !ctrl->hcor)
1124 if (init == USB_INIT_DEVICE)
1127 /* EHCI spec section 4.1 */
1128 if (ehci_reset(ctrl))
1131 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
1132 rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
1136 #ifdef CONFIG_USB_EHCI_FARADAY
1137 tweaks |= EHCI_TWEAK_NO_INIT_CF;
1139 rc = ehci_common_init(ctrl, tweaks);
1145 *controller = &ehcic[index];
1150 static int _ehci_submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1151 void *buffer, int length)
1154 if (usb_pipetype(pipe) != PIPE_BULK) {
1155 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
1158 return ehci_submit_async(dev, pipe, buffer, length, NULL);
1161 static int _ehci_submit_control_msg(struct usb_device *dev, unsigned long pipe,
1162 void *buffer, int length,
1163 struct devrequest *setup)
1165 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1167 if (usb_pipetype(pipe) != PIPE_CONTROL) {
1168 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
1172 if (usb_pipedevice(pipe) == ctrl->rootdev) {
1174 dev->speed = USB_SPEED_HIGH;
1175 return ehci_submit_root(dev, pipe, buffer, length, setup);
1177 return ehci_submit_async(dev, pipe, buffer, length, setup);
1189 #define NEXT_QH(qh) (struct QH *)((unsigned long)hc32_to_cpu((qh)->qh_link) & ~0x1f)
1192 enable_periodic(struct ehci_ctrl *ctrl)
1195 struct ehci_hcor *hcor = ctrl->hcor;
1198 cmd = ehci_readl(&hcor->or_usbcmd);
1200 ehci_writel(&hcor->or_usbcmd, cmd);
1202 ret = handshake((uint32_t *)&hcor->or_usbsts,
1203 STS_PSS, STS_PSS, 100 * 1000);
1205 printf("EHCI failed: timeout when enabling periodic list\n");
1213 disable_periodic(struct ehci_ctrl *ctrl)
1216 struct ehci_hcor *hcor = ctrl->hcor;
1219 cmd = ehci_readl(&hcor->or_usbcmd);
1221 ehci_writel(&hcor->or_usbcmd, cmd);
1223 ret = handshake((uint32_t *)&hcor->or_usbsts,
1224 STS_PSS, 0, 100 * 1000);
1226 printf("EHCI failed: timeout when disabling periodic list\n");
1232 static struct int_queue *_ehci_create_int_queue(struct usb_device *dev,
1233 unsigned long pipe, int queuesize, int elementsize,
1234 void *buffer, int interval)
1236 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1237 struct int_queue *result = NULL;
1241 * Interrupt transfers requiring several transactions are not supported
1242 * because bInterval is ignored.
1244 * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
1245 * <= PKT_ALIGN if several qTDs are required, while the USB
1246 * specification does not constrain this for interrupt transfers. That
1247 * means that ehci_submit_async() would support interrupt transfers
1248 * requiring several transactions only as long as the transfer size does
1249 * not require more than a single qTD.
1251 if (elementsize > usb_maxpacket(dev, pipe)) {
1252 printf("%s: xfers requiring several transactions are not supported.\n",
1257 debug("Enter create_int_queue\n");
1258 if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
1259 debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
1263 /* limit to 4 full pages worth of data -
1264 * we can safely fit them in a single TD,
1265 * no matter the alignment
1267 if (elementsize >= 16384) {
1268 debug("too large elements for interrupt transfers\n");
1272 result = malloc(sizeof(*result));
1274 debug("ehci intr queue: out of memory\n");
1277 result->elementsize = elementsize;
1278 result->pipe = pipe;
1279 result->first = memalign(USB_DMA_MINALIGN,
1280 sizeof(struct QH) * queuesize);
1281 if (!result->first) {
1282 debug("ehci intr queue: out of memory\n");
1285 result->current = result->first;
1286 result->last = result->first + queuesize - 1;
1287 result->tds = memalign(USB_DMA_MINALIGN,
1288 sizeof(struct qTD) * queuesize);
1290 debug("ehci intr queue: out of memory\n");
1293 memset(result->first, 0, sizeof(struct QH) * queuesize);
1294 memset(result->tds, 0, sizeof(struct qTD) * queuesize);
1296 toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
1298 for (i = 0; i < queuesize; i++) {
1299 struct QH *qh = result->first + i;
1300 struct qTD *td = result->tds + i;
1301 void **buf = &qh->buffer;
1303 qh->qh_link = cpu_to_hc32((unsigned long)(qh+1) | QH_LINK_TYPE_QH);
1304 if (i == queuesize - 1)
1305 qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
1307 qh->qh_overlay.qt_next = cpu_to_hc32((unsigned long)td);
1308 qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1310 cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */
1311 (usb_maxpacket(dev, pipe) << 16) | /* MPS */
1313 QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
1314 (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
1315 (usb_pipedevice(pipe) << 0));
1316 qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */
1317 (1 << 0)); /* S-mask: microframe 0 */
1318 if (dev->speed == USB_SPEED_LOW ||
1319 dev->speed == USB_SPEED_FULL) {
1320 /* C-mask: microframes 2-4 */
1321 qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8));
1323 ehci_update_endpt2_dev_n_port(dev, qh);
1325 td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
1326 td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
1327 debug("communication direction is '%s'\n",
1328 usb_pipein(pipe) ? "in" : "out");
1329 td->qt_token = cpu_to_hc32(
1330 QT_TOKEN_DT(toggle) |
1331 (elementsize << 16) |
1332 ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
1335 cpu_to_hc32((unsigned long)buffer + i * elementsize);
1337 cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff);
1339 cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff);
1341 cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff);
1343 cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff);
1345 *buf = buffer + i * elementsize;
1349 flush_dcache_range((unsigned long)buffer,
1350 ALIGN_END_ADDR(char, buffer,
1351 queuesize * elementsize));
1352 flush_dcache_range((unsigned long)result->first,
1353 ALIGN_END_ADDR(struct QH, result->first,
1355 flush_dcache_range((unsigned long)result->tds,
1356 ALIGN_END_ADDR(struct qTD, result->tds,
1359 if (ctrl->periodic_schedules > 0) {
1360 if (disable_periodic(ctrl) < 0) {
1361 debug("FATAL: periodic should never fail, but did");
1366 /* hook up to periodic list */
1367 struct QH *list = &ctrl->periodic_queue;
1368 result->last->qh_link = list->qh_link;
1369 list->qh_link = cpu_to_hc32((unsigned long)result->first | QH_LINK_TYPE_QH);
1371 flush_dcache_range((unsigned long)result->last,
1372 ALIGN_END_ADDR(struct QH, result->last, 1));
1373 flush_dcache_range((unsigned long)list,
1374 ALIGN_END_ADDR(struct QH, list, 1));
1376 if (enable_periodic(ctrl) < 0) {
1377 debug("FATAL: periodic should never fail, but did");
1380 ctrl->periodic_schedules++;
1382 debug("Exit create_int_queue\n");
1389 free(result->first);
1396 static void *_ehci_poll_int_queue(struct usb_device *dev,
1397 struct int_queue *queue)
1399 struct QH *cur = queue->current;
1401 uint32_t token, toggle;
1402 unsigned long pipe = queue->pipe;
1404 /* depleted queue */
1406 debug("Exit poll_int_queue with completed queue\n");
1410 cur_td = &queue->tds[queue->current - queue->first];
1411 invalidate_dcache_range((unsigned long)cur_td,
1412 ALIGN_END_ADDR(struct qTD, cur_td, 1));
1413 token = hc32_to_cpu(cur_td->qt_token);
1414 if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) {
1415 debug("Exit poll_int_queue with no completed intr transfer. token is %x\n", token);
1419 toggle = QT_TOKEN_GET_DT(token);
1420 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle);
1422 if (!(cur->qh_link & QH_LINK_TERMINATE))
1425 queue->current = NULL;
1427 invalidate_dcache_range((unsigned long)cur->buffer,
1428 ALIGN_END_ADDR(char, cur->buffer,
1429 queue->elementsize));
1431 debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n",
1432 token, cur, queue->first);
1436 /* Do not free buffers associated with QHs, they're owned by someone else */
1437 static int _ehci_destroy_int_queue(struct usb_device *dev,
1438 struct int_queue *queue)
1440 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
1442 unsigned long timeout;
1444 if (disable_periodic(ctrl) < 0) {
1445 debug("FATAL: periodic should never fail, but did");
1448 ctrl->periodic_schedules--;
1450 struct QH *cur = &ctrl->periodic_queue;
1451 timeout = get_timer(0) + 500; /* abort after 500ms */
1452 while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) {
1453 debug("considering %p, with qh_link %x\n", cur, cur->qh_link);
1454 if (NEXT_QH(cur) == queue->first) {
1455 debug("found candidate. removing from chain\n");
1456 cur->qh_link = queue->last->qh_link;
1457 flush_dcache_range((unsigned long)cur,
1458 ALIGN_END_ADDR(struct QH, cur, 1));
1463 if (get_timer(0) > timeout) {
1464 printf("Timeout destroying interrupt endpoint queue\n");
1470 if (ctrl->periodic_schedules > 0) {
1471 result = enable_periodic(ctrl);
1473 debug("FATAL: periodic should never fail, but did");
1484 static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe,
1485 void *buffer, int length, int interval)
1488 struct int_queue *queue;
1489 unsigned long timeout;
1490 int result = 0, ret;
1492 debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
1493 dev, pipe, buffer, length, interval);
1495 queue = _ehci_create_int_queue(dev, pipe, 1, length, buffer, interval);
1499 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1500 while ((backbuffer = _ehci_poll_int_queue(dev, queue)) == NULL)
1501 if (get_timer(0) > timeout) {
1502 printf("Timeout poll on interrupt endpoint\n");
1503 result = -ETIMEDOUT;
1507 if (backbuffer != buffer) {
1508 debug("got wrong buffer back (%p instead of %p)\n",
1509 backbuffer, buffer);
1513 ret = _ehci_destroy_int_queue(dev, queue);
1517 /* everything worked out fine */
1521 #if !CONFIG_IS_ENABLED(DM_USB)
1522 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
1523 void *buffer, int length)
1525 return _ehci_submit_bulk_msg(dev, pipe, buffer, length);
1528 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1529 int length, struct devrequest *setup)
1531 return _ehci_submit_control_msg(dev, pipe, buffer, length, setup);
1534 int submit_int_msg(struct usb_device *dev, unsigned long pipe,
1535 void *buffer, int length, int interval)
1537 return _ehci_submit_int_msg(dev, pipe, buffer, length, interval);
1540 struct int_queue *create_int_queue(struct usb_device *dev,
1541 unsigned long pipe, int queuesize, int elementsize,
1542 void *buffer, int interval)
1544 return _ehci_create_int_queue(dev, pipe, queuesize, elementsize,
1548 void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
1550 return _ehci_poll_int_queue(dev, queue);
1553 int destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
1555 return _ehci_destroy_int_queue(dev, queue);
1559 #if CONFIG_IS_ENABLED(DM_USB)
1560 static int ehci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1561 unsigned long pipe, void *buffer, int length,
1562 struct devrequest *setup)
1564 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1565 dev->name, udev, udev->dev->name, udev->portnr);
1567 return _ehci_submit_control_msg(udev, pipe, buffer, length, setup);
1570 static int ehci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1571 unsigned long pipe, void *buffer, int length)
1573 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1574 return _ehci_submit_bulk_msg(udev, pipe, buffer, length);
1577 static int ehci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1578 unsigned long pipe, void *buffer, int length,
1581 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1582 return _ehci_submit_int_msg(udev, pipe, buffer, length, interval);
1585 static struct int_queue *ehci_create_int_queue(struct udevice *dev,
1586 struct usb_device *udev, unsigned long pipe, int queuesize,
1587 int elementsize, void *buffer, int interval)
1589 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1590 return _ehci_create_int_queue(udev, pipe, queuesize, elementsize,
1594 static void *ehci_poll_int_queue(struct udevice *dev, struct usb_device *udev,
1595 struct int_queue *queue)
1597 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1598 return _ehci_poll_int_queue(udev, queue);
1601 static int ehci_destroy_int_queue(struct udevice *dev, struct usb_device *udev,
1602 struct int_queue *queue)
1604 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1605 return _ehci_destroy_int_queue(udev, queue);
1608 static int ehci_get_max_xfer_size(struct udevice *dev, size_t *size)
1611 * EHCD can handle any transfer length as long as there is enough
1612 * free heap space left, hence set the theoretical max number here.
1619 int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
1620 struct ehci_hcor *hcor, const struct ehci_ops *ops,
1621 uint tweaks, enum usb_init_type init)
1623 struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
1624 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1627 debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__,
1628 dev->name, ctrl, hccr, hcor, init);
1630 if (!ctrl || !hccr || !hcor)
1633 priv->desc_before_addr = true;
1635 ehci_setup_ops(ctrl, ops);
1641 if (ctrl->init == USB_INIT_DEVICE)
1644 ret = ehci_reset(ctrl);
1648 if (ctrl->ops.init_after_reset) {
1649 ret = ctrl->ops.init_after_reset(ctrl);
1654 ret = ehci_common_init(ctrl, tweaks);
1661 debug("%s: failed, ret=%d\n", __func__, ret);
1665 int ehci_deregister(struct udevice *dev)
1667 struct ehci_ctrl *ctrl = dev_get_priv(dev);
1669 if (ctrl->init == USB_INIT_DEVICE)
1672 ehci_shutdown(ctrl);
1677 struct dm_usb_ops ehci_usb_ops = {
1678 .control = ehci_submit_control_msg,
1679 .bulk = ehci_submit_bulk_msg,
1680 .interrupt = ehci_submit_int_msg,
1681 .create_int_queue = ehci_create_int_queue,
1682 .poll_int_queue = ehci_poll_int_queue,
1683 .destroy_int_queue = ehci_destroy_int_queue,
1684 .get_max_xfer_size = ehci_get_max_xfer_size,
1690 int ehci_setup_phy(struct udevice *dev, struct phy *phy, int index)
1697 ret = generic_phy_get_by_index(dev, index, phy);
1699 if (ret != -ENOENT) {
1700 dev_err(dev, "failed to get usb phy\n");
1704 ret = generic_phy_init(phy);
1706 dev_err(dev, "failed to init usb phy\n");
1710 ret = generic_phy_power_on(phy);
1712 dev_err(dev, "failed to power on usb phy\n");
1713 return generic_phy_exit(phy);
1720 int ehci_shutdown_phy(struct udevice *dev, struct phy *phy)
1727 if (generic_phy_valid(phy)) {
1728 ret = generic_phy_power_off(phy);
1730 dev_err(dev, "failed to power off usb phy\n");
1734 ret = generic_phy_exit(phy);
1736 dev_err(dev, "failed to power off usb phy\n");
1744 int ehci_setup_phy(struct udevice *dev, struct phy *phy, int index)
1749 int ehci_shutdown_phy(struct udevice *dev, struct phy *phy)