1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2009, 2011, 2016 Freescale Semiconductor, Inc.
5 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
7 * Author: Tor Krill tor@excito.com
14 #include <usb/ehci-ci.h>
17 #include <fdt_support.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
25 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
28 #if CONFIG_IS_ENABLED(DM_USB)
29 struct ehci_fsl_priv {
30 struct ehci_ctrl ehci;
36 static void set_txfifothresh(struct usb_ehci *, u32);
37 #if CONFIG_IS_ENABLED(DM_USB)
38 static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
39 struct ehci_hccr *hccr, struct ehci_hcor *hcor);
41 static int ehci_fsl_init(int index, struct usb_ehci *ehci,
42 struct ehci_hccr *hccr, struct ehci_hcor *hcor);
45 /* Check USB PHY clock valid */
46 static int usb_phy_clk_valid(struct usb_ehci *ehci)
48 if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
49 in_be32(&ehci->prictrl))) {
50 printf("USB PHY clock invalid!\n");
57 #if CONFIG_IS_ENABLED(DM_USB)
58 static int ehci_fsl_ofdata_to_platdata(struct udevice *dev)
60 struct ehci_fsl_priv *priv = dev_get_priv(dev);
63 prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy_type",
66 priv->phy_type = (char *)prop;
67 debug("phy_type %s\n", priv->phy_type);
73 static int ehci_fsl_init_after_reset(struct ehci_ctrl *ctrl)
75 struct usb_ehci *ehci = NULL;
76 struct ehci_fsl_priv *priv = container_of(ctrl, struct ehci_fsl_priv,
79 ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
81 ehci = (struct usb_ehci *)priv->hcd_base;
84 if (ehci_fsl_init(priv, ehci, priv->ehci.hccr, priv->ehci.hcor) < 0)
90 static const struct ehci_ops fsl_ehci_ops = {
91 .init_after_reset = ehci_fsl_init_after_reset,
94 static int ehci_fsl_probe(struct udevice *dev)
96 struct ehci_fsl_priv *priv = dev_get_priv(dev);
97 struct usb_ehci *ehci = NULL;
98 struct ehci_hccr *hccr;
99 struct ehci_hcor *hcor;
100 struct ehci_ctrl *ehci_ctrl = &priv->ehci;
103 * Get the base address for EHCI controller from the device node
105 priv->hcd_base = devfdt_get_addr(dev);
106 if (priv->hcd_base == FDT_ADDR_T_NONE) {
107 debug("Can't get the EHCI register base address\n");
111 ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
113 ehci = (struct usb_ehci *)priv->hcd_base;
115 hccr = (struct ehci_hccr *)(&ehci->caplength);
116 hcor = (struct ehci_hcor *)
117 ((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
119 ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275();
121 if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0)
124 debug("ehci-fsl: init hccr %p and hcor %p hc_length %d\n",
125 (void *)hccr, (void *)hcor,
126 HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
128 return ehci_register(dev, hccr, hcor, &fsl_ehci_ops, 0, USB_INIT_HOST);
131 static const struct udevice_id ehci_usb_ids[] = {
132 { .compatible = "fsl-usb2-mph", },
133 { .compatible = "fsl-usb2-dr", },
137 U_BOOT_DRIVER(ehci_fsl) = {
140 .of_match = ehci_usb_ids,
141 .ofdata_to_platdata = ehci_fsl_ofdata_to_platdata,
142 .probe = ehci_fsl_probe,
143 .remove = ehci_deregister,
144 .ops = &ehci_usb_ops,
145 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
146 .priv_auto_alloc_size = sizeof(struct ehci_fsl_priv),
147 .flags = DM_FLAG_ALLOC_PRIV_DMA,
151 * Create the appropriate control structures to manage
152 * a new EHCI host controller.
154 * Excerpts from linux ehci fsl driver.
156 int ehci_hcd_init(int index, enum usb_init_type init,
157 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
159 struct ehci_ctrl *ehci_ctrl = container_of(hccr,
160 struct ehci_ctrl, hccr);
161 struct usb_ehci *ehci = NULL;
165 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
168 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
171 printf("ERROR: wrong controller index!!\n");
175 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
176 *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
177 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
179 ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275();
181 return ehci_fsl_init(index, ehci, *hccr, *hcor);
185 * Destroy the appropriate control structures corresponding
186 * the the EHCI host controller.
188 int ehci_hcd_stop(int index)
194 #if CONFIG_IS_ENABLED(DM_USB)
195 static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
196 struct ehci_hccr *hccr, struct ehci_hcor *hcor)
198 static int ehci_fsl_init(int index, struct usb_ehci *ehci,
199 struct ehci_hccr *hccr, struct ehci_hcor *hcor)
202 const char *phy_type = NULL;
203 #if !CONFIG_IS_ENABLED(DM_USB)
205 char current_usb_controller[5];
207 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
212 if (has_erratum_a007075()) {
214 * A 5ms delay is needed after applying soft-reset to the
215 * controller to let external ULPI phy come out of reset.
216 * This delay needs to be added before re-initializing
217 * the controller after soft-resetting completes
222 /* Set to Host mode */
223 setbits_le32(&ehci->usbmode, CM_HOST);
225 out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
226 out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
229 #if CONFIG_IS_ENABLED(DM_USB)
231 phy_type = priv->phy_type;
233 memset(current_usb_controller, '\0', 5);
234 snprintf(current_usb_controller, sizeof(current_usb_controller),
237 if (hwconfig_sub(current_usb_controller, "phy_type"))
238 phy_type = hwconfig_subarg(current_usb_controller,
242 phy_type = env_get("usb_phy_type");
245 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
246 /* if none specified assume internal UTMI */
247 strcpy(usb_phy, "utmi");
250 printf("WARNING: USB phy type not defined !!\n");
255 if (!strncmp(phy_type, "utmi", 4)) {
256 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
257 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
259 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
261 udelay(1000); /* delay required for PHY Clk to appear */
263 out_le32(&(hcor)->or_portsc[0], PORT_PTS_UTMI);
264 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
267 clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
269 clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
270 CONTROL_REGISTER_W1C_MASK, USB_EN);
271 udelay(1000); /* delay required for PHY Clk to appear */
272 if (!usb_phy_clk_valid(ehci))
274 out_le32(&(hcor)->or_portsc[0], PORT_PTS_ULPI);
277 out_be32(&ehci->prictrl, 0x0000000c);
278 out_be32(&ehci->age_cnt_limit, 0x00000040);
279 out_be32(&ehci->sictrl, 0x00000001);
281 in_le32(&ehci->usbmode);
283 if (has_erratum_a007798())
284 set_txfifothresh(ehci, TXFIFOTHRESH);
286 if (has_erratum_a004477()) {
288 * When reset is issued while any ULPI transaction is ongoing
289 * then it may result to corruption of ULPI Function Control
290 * Register which eventually causes phy clock to enter low
291 * power mode which stops the clock. Thus delay is required
292 * before reset to let ongoing ULPI transaction complete.
300 * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
301 * to counter DDR latencies in writing data into Tx buffer.
302 * This prevents Tx buffer from getting underrun
304 static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
307 cmd = ehci_readl(&ehci->txfilltuning);
308 cmd &= ~TXFIFO_THRESH_MASK;
309 cmd |= TXFIFO_THRESH(txfifo_thresh);
310 ehci_writel(&ehci->txfilltuning, cmd);