2 * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc.
4 * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
6 * Author: Tor Krill tor@excito.com
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <usb/ehci-fsl.h>
32 #include "ehci-core.h"
35 * Create the appropriate control structures to manage
36 * a new EHCI host controller.
38 * Excerpts from linux ehci fsl driver.
40 int ehci_hcd_init(void)
42 struct usb_ehci *ehci;
44 const char *phy_type = NULL;
49 ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
50 hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
51 hcor = (struct ehci_hcor *)((uint32_t) hccr +
52 HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
54 /* Set to Host mode */
55 setbits_le32(&ehci->usbmode, CM_HOST);
57 out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
58 out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
61 if (hwconfig_sub("usb1", "phy_type"))
62 phy_type = hwconfig_subarg("usb1", "phy_type", &len);
64 phy_type = getenv("usb_phy_type");
67 #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
68 /* if none specified assume internal UTMI */
69 strcpy(usb_phy, "utmi");
72 printf("WARNING: USB phy type not defined !!\n");
77 if (!strcmp(phy_type, "utmi")) {
78 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
79 setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
80 setbits_be32(&ehci->control, UTMI_PHY_EN);
81 udelay(1000); /* delay required for PHY Clk to appear */
83 out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI);
85 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
86 clrbits_be32(&ehci->control, UTMI_PHY_EN);
87 setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
88 udelay(1000); /* delay required for PHY Clk to appear */
90 out_le32(&(hcor->or_portsc[0]), PORT_PTS_ULPI);
93 /* Enable interface. */
94 setbits_be32(&ehci->control, USB_EN);
96 out_be32(&ehci->prictrl, 0x0000000c);
97 out_be32(&ehci->age_cnt_limit, 0x00000040);
98 out_be32(&ehci->sictrl, 0x00000001);
100 in_le32(&ehci->usbmode);
106 * Destroy the appropriate control structures corresponding
107 * the the EHCI host controller.
109 int ehci_hcd_stop(void)