2 * SAMSUNG EXYNOS USB HOST EHCI Controller
4 * Copyright (C) 2012 Samsung Electronics Co.Ltd
5 * Vivek Gautam <gautam.vivek@samsung.com>
7 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/ehci.h>
18 #include <asm/arch/system.h>
19 #include <asm/arch/power.h>
21 #include <asm-generic/errno.h>
22 #include <linux/compat.h>
25 /* Declare global data pointer */
26 DECLARE_GLOBAL_DATA_PTR;
29 struct exynos_ehci_platdata {
30 struct usb_platdata usb_plat;
33 struct gpio_desc vbus_gpio;
38 * Contains pointers to register base addresses
39 * for the usb controller.
42 struct ehci_ctrl ctrl;
43 struct exynos_usb_phy *usb;
44 struct ehci_hccr *hcd;
46 struct gpio_desc vbus_gpio;
51 static struct exynos_ehci exynos;
55 static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
57 struct exynos_ehci_platdata *plat = dev_get_platdata(dev);
58 const void *blob = gd->fdt_blob;
63 * Get the base address for XHCI controller from the device node
65 plat->hcd_base = dev_get_addr(dev);
66 if (plat->hcd_base == FDT_ADDR_T_NONE) {
67 debug("Can't get the XHCI register base address\n");
72 node = fdtdec_next_compatible_subnode(blob, dev->of_offset,
73 COMPAT_SAMSUNG_EXYNOS_USB_PHY, &depth);
75 debug("XHCI: Can't get device node for usb3-phy controller\n");
80 * Get the base address for usbphy from the device node
82 plat->phy_base = fdtdec_get_addr(blob, node, "reg");
83 if (plat->phy_base == FDT_ADDR_T_NONE) {
84 debug("Can't get the usbphy register address\n");
89 gpio_request_by_name(dev, "samsung,vbus-gpio", 0,
90 &plat->vbus_gpio, GPIOD_IS_OUT);
95 static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos)
101 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_EHCI);
103 debug("EHCI: Can't get device node for ehci\n");
108 * Get the base address for EHCI controller from the device node
110 addr = fdtdec_get_addr(blob, node, "reg");
111 if (addr == FDT_ADDR_T_NONE) {
112 debug("Can't get the EHCI register address\n");
116 exynos->hcd = (struct ehci_hccr *)addr;
119 gpio_request_by_name_nodev(blob, node, "samsung,vbus-gpio", 0,
120 &exynos->vbus_gpio, GPIOD_IS_OUT);
123 node = fdtdec_next_compatible_subnode(blob, node,
124 COMPAT_SAMSUNG_EXYNOS_USB_PHY, &depth);
126 debug("EHCI: Can't get device node for usb-phy controller\n");
131 * Get the base address for usbphy from the device node
133 exynos->usb = (struct exynos_usb_phy *)fdtdec_get_addr(blob, node,
135 if (exynos->usb == NULL) {
136 debug("Can't get the usbphy register address\n");
144 static void exynos5_setup_usb_phy(struct exynos_usb_phy *usb)
148 clrbits_le32(&usb->usbphyctrl0,
149 HOST_CTRL0_FSEL_MASK |
150 HOST_CTRL0_COMMONON_N |
151 /* HOST Phy setting */
152 HOST_CTRL0_PHYSWRST |
153 HOST_CTRL0_PHYSWRSTALL |
155 HOST_CTRL0_FORCESUSPEND |
156 HOST_CTRL0_FORCESLEEP);
158 setbits_le32(&usb->usbphyctrl0,
159 /* Setting up the ref freq */
161 /* HOST Phy setting */
162 HOST_CTRL0_LINKSWRST |
163 HOST_CTRL0_UTMISWRST);
165 clrbits_le32(&usb->usbphyctrl0,
166 HOST_CTRL0_LINKSWRST |
167 HOST_CTRL0_UTMISWRST);
169 /* HSIC Phy Setting */
170 hsic_ctrl = (HSIC_CTRL_FORCESUSPEND |
171 HSIC_CTRL_FORCESLEEP |
174 clrbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
175 clrbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
177 hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK)
178 << HSIC_CTRL_REFCLKDIV_SHIFT)
179 | ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK)
180 << HSIC_CTRL_REFCLKSEL_SHIFT)
181 | HSIC_CTRL_UTMISWRST);
183 setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
184 setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
188 clrbits_le32(&usb->hsicphyctrl1, HSIC_CTRL_PHYSWRST |
189 HSIC_CTRL_UTMISWRST);
191 clrbits_le32(&usb->hsicphyctrl2, HSIC_CTRL_PHYSWRST |
192 HSIC_CTRL_UTMISWRST);
196 /* EHCI Ctrl setting */
197 setbits_le32(&usb->ehcictrl,
198 EHCICTRL_ENAINCRXALIGN |
204 static void exynos4412_setup_usb_phy(struct exynos4412_usb_phy *usb)
206 writel(CLK_24MHZ, &usb->usbphyclk);
208 clrbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
209 PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
210 PHYPWR_NORMAL_MASK_PHY0));
212 setbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
214 clrbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
217 static void setup_usb_phy(struct exynos_usb_phy *usb)
219 set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
221 set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
223 if (cpu_is_exynos5())
224 exynos5_setup_usb_phy(usb);
225 else if (cpu_is_exynos4())
226 if (proid_is_exynos4412())
227 exynos4412_setup_usb_phy((struct exynos4412_usb_phy *)
231 static void exynos5_reset_usb_phy(struct exynos_usb_phy *usb)
236 setbits_le32(&usb->usbphyctrl0,
237 HOST_CTRL0_PHYSWRST |
238 HOST_CTRL0_PHYSWRSTALL |
240 HOST_CTRL0_FORCESUSPEND |
241 HOST_CTRL0_FORCESLEEP);
244 hsic_ctrl = (HSIC_CTRL_FORCESUSPEND |
245 HSIC_CTRL_FORCESLEEP |
249 setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
250 setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
253 static void exynos4412_reset_usb_phy(struct exynos4412_usb_phy *usb)
255 setbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
256 PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
257 PHYPWR_NORMAL_MASK_PHY0));
260 /* Reset the EHCI host controller. */
261 static void reset_usb_phy(struct exynos_usb_phy *usb)
263 if (cpu_is_exynos5())
264 exynos5_reset_usb_phy(usb);
265 else if (cpu_is_exynos4())
266 if (proid_is_exynos4412())
267 exynos4412_reset_usb_phy((struct exynos4412_usb_phy *)
270 set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
273 #ifndef CONFIG_DM_USB
275 * EHCI-initialization
276 * Create the appropriate control structures to manage
277 * a new EHCI host controller.
279 int ehci_hcd_init(int index, enum usb_init_type init,
280 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
282 struct exynos_ehci *ctx = &exynos;
284 #ifdef CONFIG_OF_CONTROL
285 if (exynos_usb_parse_dt(gd->fdt_blob, ctx)) {
286 debug("Unable to parse device tree for ehci-exynos\n");
290 ctx->usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
291 ctx->hcd = (struct ehci_hccr *)samsung_get_base_usb_ehci();
294 #ifdef CONFIG_OF_CONTROL
295 /* setup the Vbus gpio here */
296 if (dm_gpio_is_valid(&ctx->vbus_gpio))
297 dm_gpio_set_value(&ctx->vbus_gpio, 1);
300 setup_usb_phy(ctx->usb);
302 board_usb_init(index, init);
305 *hcor = (struct ehci_hcor *)((uint32_t) *hccr
306 + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
308 debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
309 (uint32_t)*hccr, (uint32_t)*hcor,
310 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
316 * Destroy the appropriate control structures corresponding
317 * the EHCI host controller.
319 int ehci_hcd_stop(int index)
321 struct exynos_ehci *ctx = &exynos;
323 reset_usb_phy(ctx->usb);
330 static int ehci_usb_probe(struct udevice *dev)
332 struct exynos_ehci_platdata *plat = dev_get_platdata(dev);
333 struct exynos_ehci *ctx = dev_get_priv(dev);
334 struct ehci_hcor *hcor;
336 ctx->hcd = (struct ehci_hccr *)plat->hcd_base;
337 ctx->usb = (struct exynos_usb_phy *)plat->phy_base;
338 hcor = (struct ehci_hcor *)((uint32_t)ctx->hcd +
339 HC_LENGTH(ehci_readl(&ctx->hcd->cr_capbase)));
341 /* setup the Vbus gpio here */
342 if (dm_gpio_is_valid(&plat->vbus_gpio))
343 dm_gpio_set_value(&plat->vbus_gpio, 1);
345 setup_usb_phy(ctx->usb);
347 return ehci_register(dev, ctx->hcd, hcor, NULL, 0, USB_INIT_HOST);
350 static int ehci_usb_remove(struct udevice *dev)
352 struct exynos_ehci *ctx = dev_get_priv(dev);
355 ret = ehci_deregister(dev);
358 reset_usb_phy(ctx->usb);
363 static const struct udevice_id ehci_usb_ids[] = {
364 { .compatible = "samsung,exynos-ehci" },
368 U_BOOT_DRIVER(usb_ehci) = {
369 .name = "ehci_exynos",
371 .of_match = ehci_usb_ids,
372 .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
373 .probe = ehci_usb_probe,
374 .remove = ehci_usb_remove,
375 .ops = &ehci_usb_ops,
376 .priv_auto_alloc_size = sizeof(struct exynos_ehci),
377 .platdata_auto_alloc_size = sizeof(struct exynos_ehci_platdata),
378 .flags = DM_FLAG_ALLOC_PRIV_DMA,