2 * SAMSUNG EXYNOS USB HOST EHCI Controller
4 * Copyright (C) 2012 Samsung Electronics Co.Ltd
5 * Vivek Gautam <gautam.vivek@samsung.com>
7 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/ehci.h>
17 #include <asm/arch/system.h>
18 #include <asm/arch/power.h>
20 #include <asm-generic/errno.h>
21 #include <linux/compat.h>
24 /* Declare global data pointer */
25 DECLARE_GLOBAL_DATA_PTR;
28 * Contains pointers to register base addresses
29 * for the usb controller.
32 struct exynos_usb_phy *usb;
33 struct ehci_hccr *hcd;
34 struct fdt_gpio_state vbus_gpio;
37 static struct exynos_ehci exynos;
39 #ifdef CONFIG_OF_CONTROL
40 static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos)
46 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_EHCI);
48 debug("EHCI: Can't get device node for ehci\n");
53 * Get the base address for EHCI controller from the device node
55 addr = fdtdec_get_addr(blob, node, "reg");
56 if (addr == FDT_ADDR_T_NONE) {
57 debug("Can't get the EHCI register address\n");
61 exynos->hcd = (struct ehci_hccr *)addr;
64 fdtdec_decode_gpio(blob, node, "samsung,vbus-gpio", &exynos->vbus_gpio);
67 node = fdtdec_next_compatible_subnode(blob, node,
68 COMPAT_SAMSUNG_EXYNOS_USB_PHY, &depth);
70 debug("EHCI: Can't get device node for usb-phy controller\n");
75 * Get the base address for usbphy from the device node
77 exynos->usb = (struct exynos_usb_phy *)fdtdec_get_addr(blob, node,
79 if (exynos->usb == NULL) {
80 debug("Can't get the usbphy register address\n");
88 /* Setup the EHCI host controller. */
89 static void setup_usb_phy(struct exynos_usb_phy *usb)
91 set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
93 set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
95 clrbits_le32(&usb->usbphyctrl0,
96 HOST_CTRL0_FSEL_MASK |
97 HOST_CTRL0_COMMONON_N |
98 /* HOST Phy setting */
100 HOST_CTRL0_PHYSWRSTALL |
102 HOST_CTRL0_FORCESUSPEND |
103 HOST_CTRL0_FORCESLEEP);
105 setbits_le32(&usb->usbphyctrl0,
106 /* Setting up the ref freq */
108 /* HOST Phy setting */
109 HOST_CTRL0_LINKSWRST |
110 HOST_CTRL0_UTMISWRST);
112 clrbits_le32(&usb->usbphyctrl0,
113 HOST_CTRL0_LINKSWRST |
114 HOST_CTRL0_UTMISWRST);
117 /* EHCI Ctrl setting */
118 setbits_le32(&usb->ehcictrl,
119 EHCICTRL_ENAINCRXALIGN |
125 /* Reset the EHCI host controller. */
126 static void reset_usb_phy(struct exynos_usb_phy *usb)
129 setbits_le32(&usb->usbphyctrl0,
130 HOST_CTRL0_PHYSWRST |
131 HOST_CTRL0_PHYSWRSTALL |
133 HOST_CTRL0_FORCESUSPEND |
134 HOST_CTRL0_FORCESLEEP);
136 set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
140 * EHCI-initialization
141 * Create the appropriate control structures to manage
142 * a new EHCI host controller.
144 int ehci_hcd_init(int index, enum usb_init_type init,
145 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
147 struct exynos_ehci *ctx = &exynos;
149 #ifdef CONFIG_OF_CONTROL
150 if (exynos_usb_parse_dt(gd->fdt_blob, ctx)) {
151 debug("Unable to parse device tree for ehci-exynos\n");
155 ctx->usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
156 ctx->hcd = (struct ehci_hccr *)samsung_get_base_usb_ehci();
159 #ifdef CONFIG_OF_CONTROL
160 /* setup the Vbus gpio here */
161 if (!fdtdec_setup_gpio(&ctx->vbus_gpio))
162 gpio_direction_output(ctx->vbus_gpio.gpio, 1);
165 setup_usb_phy(ctx->usb);
168 *hcor = (struct ehci_hcor *)((uint32_t) *hccr
169 + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
171 debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
172 (uint32_t)*hccr, (uint32_t)*hcor,
173 (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
179 * Destroy the appropriate control structures corresponding
180 * the EHCI host controller.
182 int ehci_hcd_stop(int index)
184 struct exynos_ehci *ctx = &exynos;
186 reset_usb_phy(ctx->usb);