2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <usbroothubdes.h>
20 /* Use only HC channel 0. */
21 #define DWC2_HC_CHANNEL 0
23 #define DWC2_STATUS_BUF_SIZE 64
24 #define DWC2_DATA_BUF_SIZE (64 * 1024)
27 #define MAX_ENDPOINT 16
31 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
32 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
34 uint8_t *aligned_buffer;
35 uint8_t *status_buffer;
37 int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
38 struct dwc2_core_regs *regs;
43 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
44 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
46 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
49 static struct dwc2_priv local;
55 static int wait_for_bit(void *reg, const uint32_t mask, bool set)
57 unsigned int timeout = 1000000;
65 if ((val & mask) == mask)
71 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
72 __func__, reg, mask, set);
78 * Initializes the FSLSPClkSel field of the HCFG register
79 * depending on the PHY type.
81 static void init_fslspclksel(struct dwc2_core_regs *regs)
85 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
86 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
88 /* High speed PHY running at full speed or high speed */
89 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
92 #ifdef CONFIG_DWC2_ULPI_FS_LS
93 uint32_t hwcfg2 = readl(®s->ghwcfg2);
94 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
95 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
96 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
97 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
99 if (hval == 2 && fval == 1)
100 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
103 clrsetbits_le32(®s->host_regs.hcfg,
104 DWC2_HCFG_FSLSPCLKSEL_MASK,
105 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
111 * @param regs Programming view of DWC_otg controller.
112 * @param num Tx FIFO to flush.
114 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
118 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
120 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_TXFFLSH, 0);
122 printf("%s: Timeout!\n", __func__);
124 /* Wait for 3 PHY Clocks */
131 * @param regs Programming view of DWC_otg controller.
133 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
137 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl);
138 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_RXFFLSH, 0);
140 printf("%s: Timeout!\n", __func__);
142 /* Wait for 3 PHY Clocks */
147 * Do core a soft reset of the core. Be careful with this because it
148 * resets all the internal state machines of the core.
150 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
154 /* Wait for AHB master IDLE state. */
155 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_AHBIDLE, 1);
157 printf("%s: Timeout!\n", __func__);
159 /* Core Soft Reset */
160 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl);
161 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_CSFTRST, 0);
163 printf("%s: Timeout!\n", __func__);
166 * Wait for core to come out of reset.
167 * NOTE: This long sleep is _very_ important, otherwise the core will
168 * not stay in host mode after a connector ID change!
174 * This function initializes the DWC_otg controller registers for
177 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
178 * request queues. Host channels are reset to ensure that they are ready for
179 * performing transfers.
181 * @param regs Programming view of DWC_otg controller
184 static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
186 uint32_t nptxfifosize = 0;
187 uint32_t ptxfifosize = 0;
189 int i, ret, num_channels;
191 /* Restart the Phy Clock */
192 writel(0, ®s->pcgcctl);
194 /* Initialize Host Configuration Register */
195 init_fslspclksel(regs);
196 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
197 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
200 /* Configure data FIFO sizes */
201 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
202 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
204 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
206 /* Non-periodic Tx FIFO */
207 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
208 DWC2_FIFOSIZE_DEPTH_OFFSET;
209 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
210 DWC2_FIFOSIZE_STARTADDR_OFFSET;
211 writel(nptxfifosize, ®s->gnptxfsiz);
213 /* Periodic Tx FIFO */
214 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
215 DWC2_FIFOSIZE_DEPTH_OFFSET;
216 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
217 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
218 DWC2_FIFOSIZE_STARTADDR_OFFSET;
219 writel(ptxfifosize, ®s->hptxfsiz);
223 /* Clear Host Set HNP Enable in the OTG Control Register */
224 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
226 /* Make sure the FIFOs are flushed. */
227 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
228 dwc_otg_flush_rx_fifo(regs);
230 /* Flush out any leftover queued requests. */
231 num_channels = readl(®s->ghwcfg2);
232 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
233 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
236 for (i = 0; i < num_channels; i++)
237 clrsetbits_le32(®s->hc_regs[i].hcchar,
238 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
241 /* Halt all channels to put them into a known state. */
242 for (i = 0; i < num_channels; i++) {
243 clrsetbits_le32(®s->hc_regs[i].hcchar,
245 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
246 ret = wait_for_bit(®s->hc_regs[i].hcchar,
247 DWC2_HCCHAR_CHEN, 0);
249 printf("%s: Timeout!\n", __func__);
252 /* Turn on the vbus power. */
253 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
254 hprt0 = readl(®s->hprt0);
255 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
256 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
257 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
258 hprt0 |= DWC2_HPRT0_PRTPWR;
259 writel(hprt0, ®s->hprt0);
265 * This function initializes the DWC_otg controller registers and
266 * prepares the core for device mode or host mode operation.
268 * @param regs Programming view of the DWC_otg controller
270 static void dwc_otg_core_init(struct dwc2_core_regs *regs)
274 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
276 /* Common Initialization */
277 usbcfg = readl(®s->gusbcfg);
279 /* Program the ULPI External VBUS bit if needed */
280 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
281 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
283 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
286 /* Set external TS Dline pulsing */
287 #ifdef CONFIG_DWC2_TS_DLINE
288 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
290 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
292 writel(usbcfg, ®s->gusbcfg);
294 /* Reset the Controller */
295 dwc_otg_core_reset(regs);
298 * This programming sequence needs to happen in FS mode before
299 * any other programming occurs
301 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
302 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
303 /* If FS mode with FS PHY */
304 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL);
306 /* Reset after a PHY select */
307 dwc_otg_core_reset(regs);
310 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
311 * Also do this on HNP Dev/Host mode switches (done in dev_init
314 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
315 init_fslspclksel(regs);
317 #ifdef CONFIG_DWC2_I2C_ENABLE
318 /* Program GUSBCFG.OtgUtmifsSel to I2C */
319 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
321 /* Program GI2CCTL.I2CEn */
322 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN |
323 DWC2_GI2CCTL_I2CDEVADDR_MASK,
324 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
325 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN);
329 /* High speed PHY. */
332 * HS PHY parameters. These parameters are preserved during
333 * soft reset so only program the first time. Do a soft reset
334 * immediately after setting phyif.
336 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
337 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
339 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
340 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
341 usbcfg |= DWC2_GUSBCFG_DDRSEL;
343 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
345 } else { /* UTMI+ interface */
346 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
347 usbcfg |= DWC2_GUSBCFG_PHYIF;
351 writel(usbcfg, ®s->gusbcfg);
353 /* Reset after setting the PHY parameters */
354 dwc_otg_core_reset(regs);
357 usbcfg = readl(®s->gusbcfg);
358 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
359 #ifdef CONFIG_DWC2_ULPI_FS_LS
360 uint32_t hwcfg2 = readl(®s->ghwcfg2);
361 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
362 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
363 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
364 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
365 if (hval == 2 && fval == 1) {
366 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
367 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
370 writel(usbcfg, ®s->gusbcfg);
372 /* Program the GAHBCFG Register. */
373 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
374 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
376 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
377 while (brst_sz > 1) {
378 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
379 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
383 #ifdef CONFIG_DWC2_DMA_ENABLE
384 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
388 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
389 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
390 #ifdef CONFIG_DWC2_DMA_ENABLE
391 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
396 writel(ahbcfg, ®s->gahbcfg);
398 /* Program the GUSBCFG register for HNP/SRP. */
399 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
401 #ifdef CONFIG_DWC2_IC_USB_CAP
402 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
407 * Prepares a host channel for transferring packets to/from a specific
408 * endpoint. The HCCHARn register is set up with the characteristics specified
409 * in _hc. Host channel interrupts that may need to be serviced while this
410 * transfer is in progress are enabled.
412 * @param regs Programming view of DWC_otg controller
413 * @param hc Information needed to initialize the host channel
415 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
416 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
417 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
419 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num];
420 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
421 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
422 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
423 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
424 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
426 if (dev->speed == USB_SPEED_LOW)
427 hcchar |= DWC2_HCCHAR_LSPDDEV;
430 * Program the HCCHARn register with the endpoint characteristics
431 * for the current transfer.
433 writel(hcchar, &hc_regs->hcchar);
435 /* Program the HCSPLIT register, default to no SPLIT */
436 writel(0, &hc_regs->hcsplt);
439 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
440 uint8_t hub_devnum, uint8_t hub_port)
444 hcsplt = DWC2_HCSPLT_SPLTENA;
445 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
446 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
448 /* Program the HCSPLIT register for SPLITs */
449 writel(hcsplt, &hc_regs->hcsplt);
453 * DWC2 to USB API interface
455 /* Direction: In ; Request: Status */
456 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
457 struct usb_device *dev, void *buffer,
458 int txlen, struct devrequest *cmd)
461 uint32_t port_status = 0;
462 uint32_t port_change = 0;
466 switch (cmd->requesttype & ~USB_DIR_IN) {
468 *(uint16_t *)buffer = cpu_to_le16(1);
471 case USB_RECIP_INTERFACE:
472 case USB_RECIP_ENDPOINT:
473 *(uint16_t *)buffer = cpu_to_le16(0);
477 *(uint32_t *)buffer = cpu_to_le32(0);
480 case USB_RECIP_OTHER | USB_TYPE_CLASS:
481 hprt0 = readl(®s->hprt0);
482 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
483 port_status |= USB_PORT_STAT_CONNECTION;
484 if (hprt0 & DWC2_HPRT0_PRTENA)
485 port_status |= USB_PORT_STAT_ENABLE;
486 if (hprt0 & DWC2_HPRT0_PRTSUSP)
487 port_status |= USB_PORT_STAT_SUSPEND;
488 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
489 port_status |= USB_PORT_STAT_OVERCURRENT;
490 if (hprt0 & DWC2_HPRT0_PRTRST)
491 port_status |= USB_PORT_STAT_RESET;
492 if (hprt0 & DWC2_HPRT0_PRTPWR)
493 port_status |= USB_PORT_STAT_POWER;
495 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
496 port_status |= USB_PORT_STAT_LOW_SPEED;
497 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
498 DWC2_HPRT0_PRTSPD_HIGH)
499 port_status |= USB_PORT_STAT_HIGH_SPEED;
501 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
502 port_change |= USB_PORT_STAT_C_ENABLE;
503 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
504 port_change |= USB_PORT_STAT_C_CONNECTION;
505 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
506 port_change |= USB_PORT_STAT_C_OVERCURRENT;
508 *(uint32_t *)buffer = cpu_to_le32(port_status |
509 (port_change << 16));
513 puts("unsupported root hub command\n");
514 stat = USB_ST_STALLED;
517 dev->act_len = min(len, txlen);
523 /* Direction: In ; Request: Descriptor */
524 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
525 void *buffer, int txlen,
526 struct devrequest *cmd)
528 unsigned char data[32];
532 uint16_t wValue = cpu_to_le16(cmd->value);
533 uint16_t wLength = cpu_to_le16(cmd->length);
535 switch (cmd->requesttype & ~USB_DIR_IN) {
537 switch (wValue & 0xff00) {
538 case 0x0100: /* device descriptor */
539 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
540 memcpy(buffer, root_hub_dev_des, len);
542 case 0x0200: /* configuration descriptor */
543 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
544 memcpy(buffer, root_hub_config_des, len);
546 case 0x0300: /* string descriptors */
547 switch (wValue & 0xff) {
549 len = min3(txlen, (int)sizeof(root_hub_str_index0),
551 memcpy(buffer, root_hub_str_index0, len);
554 len = min3(txlen, (int)sizeof(root_hub_str_index1),
556 memcpy(buffer, root_hub_str_index1, len);
561 stat = USB_ST_STALLED;
566 /* Root port config, set 1 port and nothing else. */
569 data[0] = 9; /* min length; */
571 data[2] = dsc & RH_A_NDP;
577 else if (dsc & RH_A_OCPM)
580 /* corresponds to data[4-7] */
581 data[5] = (dsc & RH_A_POTPGT) >> 24;
582 data[7] = dsc & RH_B_DR;
587 data[8] = (dsc & RH_B_DR) >> 8;
592 len = min3(txlen, (int)data[0], (int)wLength);
593 memcpy(buffer, data, len);
596 puts("unsupported root hub command\n");
597 stat = USB_ST_STALLED;
600 dev->act_len = min(len, txlen);
606 /* Direction: In ; Request: Configuration */
607 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
608 void *buffer, int txlen,
609 struct devrequest *cmd)
614 switch (cmd->requesttype & ~USB_DIR_IN) {
616 *(uint8_t *)buffer = 0x01;
620 puts("unsupported root hub command\n");
621 stat = USB_ST_STALLED;
624 dev->act_len = min(len, txlen);
631 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
632 struct usb_device *dev, void *buffer,
633 int txlen, struct devrequest *cmd)
635 switch (cmd->request) {
636 case USB_REQ_GET_STATUS:
637 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
639 case USB_REQ_GET_DESCRIPTOR:
640 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
642 case USB_REQ_GET_CONFIGURATION:
643 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
646 puts("unsupported root hub command\n");
647 return USB_ST_STALLED;
652 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
653 struct usb_device *dev,
654 void *buffer, int txlen,
655 struct devrequest *cmd)
657 struct dwc2_core_regs *regs = priv->regs;
660 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
661 uint16_t wValue = cpu_to_le16(cmd->value);
663 switch (bmrtype_breq & ~USB_DIR_IN) {
664 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
665 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
668 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
670 case USB_PORT_FEAT_C_CONNECTION:
671 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET);
676 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
678 case USB_PORT_FEAT_SUSPEND:
681 case USB_PORT_FEAT_RESET:
682 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
683 DWC2_HPRT0_PRTCONNDET |
684 DWC2_HPRT0_PRTENCHNG |
685 DWC2_HPRT0_PRTOVRCURRCHNG,
688 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST);
691 case USB_PORT_FEAT_POWER:
692 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
693 DWC2_HPRT0_PRTCONNDET |
694 DWC2_HPRT0_PRTENCHNG |
695 DWC2_HPRT0_PRTOVRCURRCHNG,
699 case USB_PORT_FEAT_ENABLE:
703 case (USB_REQ_SET_ADDRESS << 8):
704 priv->root_hub_devnum = wValue;
706 case (USB_REQ_SET_CONFIGURATION << 8):
709 puts("unsupported root hub command\n");
710 stat = USB_ST_STALLED;
713 len = min(len, txlen);
721 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
722 unsigned long pipe, void *buffer, int txlen,
723 struct devrequest *cmd)
727 if (usb_pipeint(pipe)) {
728 puts("Root-Hub submit IRQ: NOT implemented\n");
732 if (cmd->requesttype & USB_DIR_IN)
733 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
735 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
742 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, int *toggle)
745 uint32_t hcint, hctsiz;
747 ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true);
751 hcint = readl(&hc_regs->hcint);
752 hctsiz = readl(&hc_regs->hctsiz);
753 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
754 DWC2_HCTSIZ_XFERSIZE_OFFSET;
755 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
757 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
760 if (hcint & DWC2_HCINT_XFERCOMP)
763 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
766 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
770 static int dwc2_eptype[] = {
771 DWC2_HCCHAR_EPTYPE_ISOC,
772 DWC2_HCCHAR_EPTYPE_INTR,
773 DWC2_HCCHAR_EPTYPE_CONTROL,
774 DWC2_HCCHAR_EPTYPE_BULK,
777 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
778 int *pid, int in, void *buffer, int num_packets,
779 int xfer_len, int *actual_len)
784 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
785 *pid, xfer_len, num_packets);
787 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
788 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
789 (*pid << DWC2_HCTSIZ_PID_OFFSET),
792 if (!in && xfer_len) {
793 memcpy(aligned_buffer, buffer, xfer_len);
795 flush_dcache_range((unsigned long)aligned_buffer,
796 (unsigned long)aligned_buffer +
797 roundup(xfer_len, ARCH_DMA_MINALIGN));
800 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
802 /* Clear old interrupt conditions for this host channel. */
803 writel(0x3fff, &hc_regs->hcint);
805 /* Set host channel enable after all other setup is complete. */
806 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
807 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
808 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
811 ret = wait_for_chhltd(hc_regs, &sub, pid);
818 invalidate_dcache_range((unsigned long)aligned_buffer,
819 (unsigned long)aligned_buffer +
820 roundup(xfer_len, ARCH_DMA_MINALIGN));
822 memcpy(buffer, aligned_buffer, xfer_len);
824 *actual_len = xfer_len;
829 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
830 unsigned long pipe, int *pid, int in, void *buffer, int len)
832 struct dwc2_core_regs *regs = priv->regs;
833 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
834 int devnum = usb_pipedevice(pipe);
835 int ep = usb_pipeendpoint(pipe);
836 int max = usb_maxpacket(dev, pipe);
837 int eptype = dwc2_eptype[usb_pipetype(pipe)];
841 int complete_split = 0;
843 uint32_t num_packets;
844 int stop_transfer = 0;
845 uint32_t max_xfer_len;
847 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
850 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
851 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
852 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
853 if (max_xfer_len > DWC2_DATA_BUF_SIZE)
854 max_xfer_len = DWC2_DATA_BUF_SIZE;
856 /* Make sure that max_xfer_len is a multiple of max packet size. */
857 num_packets = max_xfer_len / max;
858 max_xfer_len = num_packets * max;
860 /* Initialize channel */
861 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
864 /* Check if the target is a FS/LS device behind a HS hub */
865 if (dev->speed != USB_SPEED_HIGH) {
868 uint32_t hprt0 = readl(®s->hprt0);
869 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
870 DWC2_HPRT0_PRTSPD_HIGH) {
871 usb_find_usb2_hub_address_port(dev, &hub_addr,
873 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
884 xfer_len = len - done;
886 if (xfer_len > max_xfer_len)
887 xfer_len = max_xfer_len;
888 else if (xfer_len > max)
889 num_packets = (xfer_len + max - 1) / max;
894 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
896 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
898 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
899 in, (char *)buffer + done, num_packets,
900 xfer_len, &actual_len);
902 hcint = readl(&hc_regs->hcint);
903 if (complete_split) {
905 if (hcint & DWC2_HCINT_NYET)
909 } else if (do_split) {
910 if (hcint & DWC2_HCINT_ACK) {
919 if (actual_len < xfer_len)
924 /* Transactions are done when when either all data is transferred or
925 * there is a short transfer. In case of a SPLIT make sure the CSPLIT
928 } while (((done < len) && !stop_transfer) || complete_split);
930 writel(0, &hc_regs->hcintmsk);
931 writel(0xFFFFFFFF, &hc_regs->hcint);
939 /* U-Boot USB transmission interface */
940 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
941 unsigned long pipe, void *buffer, int len)
943 int devnum = usb_pipedevice(pipe);
944 int ep = usb_pipeendpoint(pipe);
946 if (devnum == priv->root_hub_devnum) {
951 return chunk_msg(priv, dev, pipe, &priv->bulk_data_toggle[devnum][ep],
952 usb_pipein(pipe), buffer, len);
955 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
956 unsigned long pipe, void *buffer, int len,
957 struct devrequest *setup)
959 int devnum = usb_pipedevice(pipe);
960 int pid, ret, act_len;
961 /* For CONTROL endpoint pid should start with DATA1 */
962 int status_direction;
964 if (devnum == priv->root_hub_devnum) {
966 dev->speed = USB_SPEED_HIGH;
967 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
972 pid = DWC2_HC_PID_SETUP;
974 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
975 } while (ret == -EAGAIN);
982 pid = DWC2_HC_PID_DATA1;
984 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
986 act_len += dev->act_len;
987 buffer += dev->act_len;
989 } while (ret == -EAGAIN);
992 status_direction = usb_pipeout(pipe);
994 /* No-data CONTROL always ends with an IN transaction */
995 status_direction = 1;
999 pid = DWC2_HC_PID_DATA1;
1001 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1002 priv->status_buffer, 0);
1003 } while (ret == -EAGAIN);
1007 dev->act_len = act_len;
1012 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1013 unsigned long pipe, void *buffer, int len, int interval)
1015 unsigned long timeout;
1018 /* FIXME: what is interval? */
1020 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1022 if (get_timer(0) > timeout) {
1023 printf("Timeout poll on interrupt endpoint\n");
1026 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1032 static int dwc2_init_common(struct dwc2_priv *priv)
1034 struct dwc2_core_regs *regs = priv->regs;
1038 snpsid = readl(®s->gsnpsid);
1039 printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
1041 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1042 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1043 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
1047 dwc_otg_core_init(regs);
1048 dwc_otg_core_host_init(regs);
1050 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1051 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1052 DWC2_HPRT0_PRTOVRCURRCHNG,
1055 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1056 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1059 for (i = 0; i < MAX_DEVICE; i++) {
1060 for (j = 0; j < MAX_ENDPOINT; j++)
1061 priv->bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1067 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1069 /* Put everything in reset. */
1070 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1071 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1072 DWC2_HPRT0_PRTOVRCURRCHNG,
1076 #ifndef CONFIG_DM_USB
1077 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1078 int len, struct devrequest *setup)
1080 return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1083 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1086 return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1089 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1090 int len, int interval)
1092 return _submit_int_msg(&local, dev, pipe, buffer, len, interval);
1095 /* U-Boot USB control interface */
1096 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1098 struct dwc2_priv *priv = &local;
1100 memset(priv, '\0', sizeof(*priv));
1101 priv->root_hub_devnum = 0;
1102 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1103 priv->aligned_buffer = aligned_buffer_addr;
1104 priv->status_buffer = status_buffer_addr;
1106 /* board-dependant init */
1107 if (board_usb_init(index, USB_INIT_HOST))
1110 return dwc2_init_common(priv);
1113 int usb_lowlevel_stop(int index)
1115 dwc2_uninit_common(local.regs);
1121 #ifdef CONFIG_DM_USB
1122 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1123 unsigned long pipe, void *buffer, int length,
1124 struct devrequest *setup)
1126 struct dwc2_priv *priv = dev_get_priv(dev);
1128 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1129 dev->name, udev, udev->dev->name, udev->portnr);
1131 return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1134 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1135 unsigned long pipe, void *buffer, int length)
1137 struct dwc2_priv *priv = dev_get_priv(dev);
1139 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1141 return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1144 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1145 unsigned long pipe, void *buffer, int length,
1148 struct dwc2_priv *priv = dev_get_priv(dev);
1150 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1152 return _submit_int_msg(priv, udev, pipe, buffer, length, interval);
1155 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1157 struct dwc2_priv *priv = dev_get_priv(dev);
1160 addr = dev_get_addr(dev);
1161 if (addr == FDT_ADDR_T_NONE)
1163 priv->regs = (struct dwc2_core_regs *)addr;
1168 static int dwc2_usb_probe(struct udevice *dev)
1170 struct dwc2_priv *priv = dev_get_priv(dev);
1172 return dwc2_init_common(priv);
1175 static int dwc2_usb_remove(struct udevice *dev)
1177 struct dwc2_priv *priv = dev_get_priv(dev);
1179 dwc2_uninit_common(priv->regs);
1184 struct dm_usb_ops dwc2_usb_ops = {
1185 .control = dwc2_submit_control_msg,
1186 .bulk = dwc2_submit_bulk_msg,
1187 .interrupt = dwc2_submit_int_msg,
1190 static const struct udevice_id dwc2_usb_ids[] = {
1191 { .compatible = "brcm,bcm2835-usb" },
1192 { .compatible = "snps,dwc2" },
1196 U_BOOT_DRIVER(usb_dwc2) = {
1199 .of_match = dwc2_usb_ids,
1200 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1201 .probe = dwc2_usb_probe,
1202 .remove = dwc2_usb_remove,
1203 .ops = &dwc2_usb_ops,
1204 .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1205 .flags = DM_FLAG_ALLOC_PRIV_DMA,