2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <usbroothubdes.h>
21 /* Use only HC channel 0. */
22 #define DWC2_HC_CHANNEL 0
24 #define DWC2_STATUS_BUF_SIZE 64
25 #define DWC2_DATA_BUF_SIZE (64 * 1024)
28 #define MAX_ENDPOINT 16
32 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
33 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
35 uint8_t *aligned_buffer;
36 uint8_t *status_buffer;
38 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
39 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
40 struct dwc2_core_regs *regs;
45 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
46 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
48 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
51 static struct dwc2_priv local;
59 * Initializes the FSLSPClkSel field of the HCFG register
60 * depending on the PHY type.
62 static void init_fslspclksel(struct dwc2_core_regs *regs)
66 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
67 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
69 /* High speed PHY running at full speed or high speed */
70 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
73 #ifdef CONFIG_DWC2_ULPI_FS_LS
74 uint32_t hwcfg2 = readl(®s->ghwcfg2);
75 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
76 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
77 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
78 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
80 if (hval == 2 && fval == 1)
81 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
84 clrsetbits_le32(®s->host_regs.hcfg,
85 DWC2_HCFG_FSLSPCLKSEL_MASK,
86 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
92 * @param regs Programming view of DWC_otg controller.
93 * @param num Tx FIFO to flush.
95 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
99 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
101 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_TXFFLSH,
104 printf("%s: Timeout!\n", __func__);
106 /* Wait for 3 PHY Clocks */
113 * @param regs Programming view of DWC_otg controller.
115 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
119 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl);
120 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_RXFFLSH,
123 printf("%s: Timeout!\n", __func__);
125 /* Wait for 3 PHY Clocks */
130 * Do core a soft reset of the core. Be careful with this because it
131 * resets all the internal state machines of the core.
133 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
137 /* Wait for AHB master IDLE state. */
138 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_AHBIDLE,
141 printf("%s: Timeout!\n", __func__);
143 /* Core Soft Reset */
144 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl);
145 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_CSFTRST,
148 printf("%s: Timeout!\n", __func__);
151 * Wait for core to come out of reset.
152 * NOTE: This long sleep is _very_ important, otherwise the core will
153 * not stay in host mode after a connector ID change!
159 * This function initializes the DWC_otg controller registers for
162 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
163 * request queues. Host channels are reset to ensure that they are ready for
164 * performing transfers.
166 * @param regs Programming view of DWC_otg controller
169 static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
171 uint32_t nptxfifosize = 0;
172 uint32_t ptxfifosize = 0;
174 int i, ret, num_channels;
176 /* Restart the Phy Clock */
177 writel(0, ®s->pcgcctl);
179 /* Initialize Host Configuration Register */
180 init_fslspclksel(regs);
181 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
182 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
185 /* Configure data FIFO sizes */
186 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
187 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
189 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
191 /* Non-periodic Tx FIFO */
192 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
193 DWC2_FIFOSIZE_DEPTH_OFFSET;
194 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
195 DWC2_FIFOSIZE_STARTADDR_OFFSET;
196 writel(nptxfifosize, ®s->gnptxfsiz);
198 /* Periodic Tx FIFO */
199 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
200 DWC2_FIFOSIZE_DEPTH_OFFSET;
201 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
202 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
203 DWC2_FIFOSIZE_STARTADDR_OFFSET;
204 writel(ptxfifosize, ®s->hptxfsiz);
208 /* Clear Host Set HNP Enable in the OTG Control Register */
209 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
211 /* Make sure the FIFOs are flushed. */
212 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
213 dwc_otg_flush_rx_fifo(regs);
215 /* Flush out any leftover queued requests. */
216 num_channels = readl(®s->ghwcfg2);
217 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
218 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
221 for (i = 0; i < num_channels; i++)
222 clrsetbits_le32(®s->hc_regs[i].hcchar,
223 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
226 /* Halt all channels to put them into a known state. */
227 for (i = 0; i < num_channels; i++) {
228 clrsetbits_le32(®s->hc_regs[i].hcchar,
230 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
231 ret = wait_for_bit(__func__, ®s->hc_regs[i].hcchar,
232 DWC2_HCCHAR_CHEN, false, 1000, false);
234 printf("%s: Timeout!\n", __func__);
237 /* Turn on the vbus power. */
238 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
239 hprt0 = readl(®s->hprt0);
240 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
241 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
242 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
243 hprt0 |= DWC2_HPRT0_PRTPWR;
244 writel(hprt0, ®s->hprt0);
250 * This function initializes the DWC_otg controller registers and
251 * prepares the core for device mode or host mode operation.
253 * @param regs Programming view of the DWC_otg controller
255 static void dwc_otg_core_init(struct dwc2_core_regs *regs)
259 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
261 /* Common Initialization */
262 usbcfg = readl(®s->gusbcfg);
264 /* Program the ULPI External VBUS bit if needed */
265 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
266 usbcfg |= (DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV |
267 DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
268 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH);
270 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
273 /* Set external TS Dline pulsing */
274 #ifdef CONFIG_DWC2_TS_DLINE
275 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
277 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
279 writel(usbcfg, ®s->gusbcfg);
281 /* Reset the Controller */
282 dwc_otg_core_reset(regs);
285 * This programming sequence needs to happen in FS mode before
286 * any other programming occurs
288 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
289 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
290 /* If FS mode with FS PHY */
291 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL);
293 /* Reset after a PHY select */
294 dwc_otg_core_reset(regs);
297 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
298 * Also do this on HNP Dev/Host mode switches (done in dev_init
301 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
302 init_fslspclksel(regs);
304 #ifdef CONFIG_DWC2_I2C_ENABLE
305 /* Program GUSBCFG.OtgUtmifsSel to I2C */
306 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
308 /* Program GI2CCTL.I2CEn */
309 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN |
310 DWC2_GI2CCTL_I2CDEVADDR_MASK,
311 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
312 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN);
316 /* High speed PHY. */
319 * HS PHY parameters. These parameters are preserved during
320 * soft reset so only program the first time. Do a soft reset
321 * immediately after setting phyif.
323 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
324 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
326 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
327 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
328 usbcfg |= DWC2_GUSBCFG_DDRSEL;
330 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
332 } else { /* UTMI+ interface */
333 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
334 usbcfg |= DWC2_GUSBCFG_PHYIF;
338 writel(usbcfg, ®s->gusbcfg);
340 /* Reset after setting the PHY parameters */
341 dwc_otg_core_reset(regs);
344 usbcfg = readl(®s->gusbcfg);
345 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
346 #ifdef CONFIG_DWC2_ULPI_FS_LS
347 uint32_t hwcfg2 = readl(®s->ghwcfg2);
348 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
349 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
350 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
351 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
352 if (hval == 2 && fval == 1) {
353 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
354 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
357 writel(usbcfg, ®s->gusbcfg);
359 /* Program the GAHBCFG Register. */
360 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
361 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
363 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
364 while (brst_sz > 1) {
365 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
366 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
370 #ifdef CONFIG_DWC2_DMA_ENABLE
371 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
375 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
376 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
377 #ifdef CONFIG_DWC2_DMA_ENABLE
378 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
383 writel(ahbcfg, ®s->gahbcfg);
385 /* Program the GUSBCFG register for HNP/SRP. */
386 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
388 #ifdef CONFIG_DWC2_IC_USB_CAP
389 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
394 * Prepares a host channel for transferring packets to/from a specific
395 * endpoint. The HCCHARn register is set up with the characteristics specified
396 * in _hc. Host channel interrupts that may need to be serviced while this
397 * transfer is in progress are enabled.
399 * @param regs Programming view of DWC_otg controller
400 * @param hc Information needed to initialize the host channel
402 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
403 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
404 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
406 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num];
407 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
408 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
409 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
410 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
411 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
413 if (dev->speed == USB_SPEED_LOW)
414 hcchar |= DWC2_HCCHAR_LSPDDEV;
417 * Program the HCCHARn register with the endpoint characteristics
418 * for the current transfer.
420 writel(hcchar, &hc_regs->hcchar);
422 /* Program the HCSPLIT register, default to no SPLIT */
423 writel(0, &hc_regs->hcsplt);
426 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
427 uint8_t hub_devnum, uint8_t hub_port)
431 hcsplt = DWC2_HCSPLT_SPLTENA;
432 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
433 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
435 /* Program the HCSPLIT register for SPLITs */
436 writel(hcsplt, &hc_regs->hcsplt);
440 * DWC2 to USB API interface
442 /* Direction: In ; Request: Status */
443 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
444 struct usb_device *dev, void *buffer,
445 int txlen, struct devrequest *cmd)
448 uint32_t port_status = 0;
449 uint32_t port_change = 0;
453 switch (cmd->requesttype & ~USB_DIR_IN) {
455 *(uint16_t *)buffer = cpu_to_le16(1);
458 case USB_RECIP_INTERFACE:
459 case USB_RECIP_ENDPOINT:
460 *(uint16_t *)buffer = cpu_to_le16(0);
464 *(uint32_t *)buffer = cpu_to_le32(0);
467 case USB_RECIP_OTHER | USB_TYPE_CLASS:
468 hprt0 = readl(®s->hprt0);
469 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
470 port_status |= USB_PORT_STAT_CONNECTION;
471 if (hprt0 & DWC2_HPRT0_PRTENA)
472 port_status |= USB_PORT_STAT_ENABLE;
473 if (hprt0 & DWC2_HPRT0_PRTSUSP)
474 port_status |= USB_PORT_STAT_SUSPEND;
475 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
476 port_status |= USB_PORT_STAT_OVERCURRENT;
477 if (hprt0 & DWC2_HPRT0_PRTRST)
478 port_status |= USB_PORT_STAT_RESET;
479 if (hprt0 & DWC2_HPRT0_PRTPWR)
480 port_status |= USB_PORT_STAT_POWER;
482 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
483 port_status |= USB_PORT_STAT_LOW_SPEED;
484 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
485 DWC2_HPRT0_PRTSPD_HIGH)
486 port_status |= USB_PORT_STAT_HIGH_SPEED;
488 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
489 port_change |= USB_PORT_STAT_C_ENABLE;
490 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
491 port_change |= USB_PORT_STAT_C_CONNECTION;
492 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
493 port_change |= USB_PORT_STAT_C_OVERCURRENT;
495 *(uint32_t *)buffer = cpu_to_le32(port_status |
496 (port_change << 16));
500 puts("unsupported root hub command\n");
501 stat = USB_ST_STALLED;
504 dev->act_len = min(len, txlen);
510 /* Direction: In ; Request: Descriptor */
511 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
512 void *buffer, int txlen,
513 struct devrequest *cmd)
515 unsigned char data[32];
519 uint16_t wValue = cpu_to_le16(cmd->value);
520 uint16_t wLength = cpu_to_le16(cmd->length);
522 switch (cmd->requesttype & ~USB_DIR_IN) {
524 switch (wValue & 0xff00) {
525 case 0x0100: /* device descriptor */
526 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
527 memcpy(buffer, root_hub_dev_des, len);
529 case 0x0200: /* configuration descriptor */
530 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
531 memcpy(buffer, root_hub_config_des, len);
533 case 0x0300: /* string descriptors */
534 switch (wValue & 0xff) {
536 len = min3(txlen, (int)sizeof(root_hub_str_index0),
538 memcpy(buffer, root_hub_str_index0, len);
541 len = min3(txlen, (int)sizeof(root_hub_str_index1),
543 memcpy(buffer, root_hub_str_index1, len);
548 stat = USB_ST_STALLED;
553 /* Root port config, set 1 port and nothing else. */
556 data[0] = 9; /* min length; */
558 data[2] = dsc & RH_A_NDP;
564 else if (dsc & RH_A_OCPM)
567 /* corresponds to data[4-7] */
568 data[5] = (dsc & RH_A_POTPGT) >> 24;
569 data[7] = dsc & RH_B_DR;
574 data[8] = (dsc & RH_B_DR) >> 8;
579 len = min3(txlen, (int)data[0], (int)wLength);
580 memcpy(buffer, data, len);
583 puts("unsupported root hub command\n");
584 stat = USB_ST_STALLED;
587 dev->act_len = min(len, txlen);
593 /* Direction: In ; Request: Configuration */
594 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
595 void *buffer, int txlen,
596 struct devrequest *cmd)
601 switch (cmd->requesttype & ~USB_DIR_IN) {
603 *(uint8_t *)buffer = 0x01;
607 puts("unsupported root hub command\n");
608 stat = USB_ST_STALLED;
611 dev->act_len = min(len, txlen);
618 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
619 struct usb_device *dev, void *buffer,
620 int txlen, struct devrequest *cmd)
622 switch (cmd->request) {
623 case USB_REQ_GET_STATUS:
624 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
626 case USB_REQ_GET_DESCRIPTOR:
627 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
629 case USB_REQ_GET_CONFIGURATION:
630 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
633 puts("unsupported root hub command\n");
634 return USB_ST_STALLED;
639 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
640 struct usb_device *dev,
641 void *buffer, int txlen,
642 struct devrequest *cmd)
644 struct dwc2_core_regs *regs = priv->regs;
647 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
648 uint16_t wValue = cpu_to_le16(cmd->value);
650 switch (bmrtype_breq & ~USB_DIR_IN) {
651 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
652 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
655 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
657 case USB_PORT_FEAT_C_CONNECTION:
658 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET);
663 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
665 case USB_PORT_FEAT_SUSPEND:
668 case USB_PORT_FEAT_RESET:
669 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
670 DWC2_HPRT0_PRTCONNDET |
671 DWC2_HPRT0_PRTENCHNG |
672 DWC2_HPRT0_PRTOVRCURRCHNG,
675 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST);
678 case USB_PORT_FEAT_POWER:
679 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
680 DWC2_HPRT0_PRTCONNDET |
681 DWC2_HPRT0_PRTENCHNG |
682 DWC2_HPRT0_PRTOVRCURRCHNG,
686 case USB_PORT_FEAT_ENABLE:
690 case (USB_REQ_SET_ADDRESS << 8):
691 priv->root_hub_devnum = wValue;
693 case (USB_REQ_SET_CONFIGURATION << 8):
696 puts("unsupported root hub command\n");
697 stat = USB_ST_STALLED;
700 len = min(len, txlen);
708 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
709 unsigned long pipe, void *buffer, int txlen,
710 struct devrequest *cmd)
714 if (usb_pipeint(pipe)) {
715 puts("Root-Hub submit IRQ: NOT implemented\n");
719 if (cmd->requesttype & USB_DIR_IN)
720 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
722 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
729 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
732 uint32_t hcint, hctsiz;
734 ret = wait_for_bit(__func__, &hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
739 hcint = readl(&hc_regs->hcint);
740 hctsiz = readl(&hc_regs->hctsiz);
741 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
742 DWC2_HCTSIZ_XFERSIZE_OFFSET;
743 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
745 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
748 if (hcint & DWC2_HCINT_XFERCOMP)
751 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
754 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
758 static int dwc2_eptype[] = {
759 DWC2_HCCHAR_EPTYPE_ISOC,
760 DWC2_HCCHAR_EPTYPE_INTR,
761 DWC2_HCCHAR_EPTYPE_CONTROL,
762 DWC2_HCCHAR_EPTYPE_BULK,
765 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
766 u8 *pid, int in, void *buffer, int num_packets,
767 int xfer_len, int *actual_len, int odd_frame)
772 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
773 *pid, xfer_len, num_packets);
775 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
776 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
777 (*pid << DWC2_HCTSIZ_PID_OFFSET),
780 if (!in && xfer_len) {
781 memcpy(aligned_buffer, buffer, xfer_len);
783 flush_dcache_range((unsigned long)aligned_buffer,
784 (unsigned long)aligned_buffer +
785 roundup(xfer_len, ARCH_DMA_MINALIGN));
788 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
790 /* Clear old interrupt conditions for this host channel. */
791 writel(0x3fff, &hc_regs->hcint);
793 /* Set host channel enable after all other setup is complete. */
794 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
795 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
797 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
798 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
801 ret = wait_for_chhltd(hc_regs, &sub, pid);
808 invalidate_dcache_range((unsigned long)aligned_buffer,
809 (unsigned long)aligned_buffer +
810 roundup(xfer_len, ARCH_DMA_MINALIGN));
812 memcpy(buffer, aligned_buffer, xfer_len);
814 *actual_len = xfer_len;
819 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
820 unsigned long pipe, u8 *pid, int in, void *buffer, int len)
822 struct dwc2_core_regs *regs = priv->regs;
823 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
824 struct dwc2_host_regs *host_regs = ®s->host_regs;
825 int devnum = usb_pipedevice(pipe);
826 int ep = usb_pipeendpoint(pipe);
827 int max = usb_maxpacket(dev, pipe);
828 int eptype = dwc2_eptype[usb_pipetype(pipe)];
832 int complete_split = 0;
834 uint32_t num_packets;
835 int stop_transfer = 0;
836 uint32_t max_xfer_len;
837 int ssplit_frame_num = 0;
839 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
842 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
843 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
844 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
845 if (max_xfer_len > DWC2_DATA_BUF_SIZE)
846 max_xfer_len = DWC2_DATA_BUF_SIZE;
848 /* Make sure that max_xfer_len is a multiple of max packet size. */
849 num_packets = max_xfer_len / max;
850 max_xfer_len = num_packets * max;
852 /* Initialize channel */
853 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
856 /* Check if the target is a FS/LS device behind a HS hub */
857 if (dev->speed != USB_SPEED_HIGH) {
860 uint32_t hprt0 = readl(®s->hprt0);
861 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
862 DWC2_HPRT0_PRTSPD_HIGH) {
863 usb_find_usb2_hub_address_port(dev, &hub_addr,
865 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
877 xfer_len = len - done;
879 if (xfer_len > max_xfer_len)
880 xfer_len = max_xfer_len;
881 else if (xfer_len > max)
882 num_packets = (xfer_len + max - 1) / max;
887 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
889 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
891 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
892 int uframe_num = readl(&host_regs->hfnum);
893 if (!(uframe_num & 0x1))
897 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
898 in, (char *)buffer + done, num_packets,
899 xfer_len, &actual_len, odd_frame);
901 hcint = readl(&hc_regs->hcint);
902 if (complete_split) {
904 if (hcint & DWC2_HCINT_NYET) {
906 int frame_num = DWC2_HFNUM_MAX_FRNUM &
907 readl(&host_regs->hfnum);
908 if (((frame_num - ssplit_frame_num) &
909 DWC2_HFNUM_MAX_FRNUM) > 4)
913 } else if (do_split) {
914 if (hcint & DWC2_HCINT_ACK) {
915 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
916 readl(&host_regs->hfnum);
925 if (actual_len < xfer_len)
930 /* Transactions are done when when either all data is transferred or
931 * there is a short transfer. In case of a SPLIT make sure the CSPLIT
934 } while (((done < len) && !stop_transfer) || complete_split);
936 writel(0, &hc_regs->hcintmsk);
937 writel(0xFFFFFFFF, &hc_regs->hcint);
945 /* U-Boot USB transmission interface */
946 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
947 unsigned long pipe, void *buffer, int len)
949 int devnum = usb_pipedevice(pipe);
950 int ep = usb_pipeendpoint(pipe);
953 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
958 if (usb_pipein(pipe))
959 pid = &priv->in_data_toggle[devnum][ep];
961 pid = &priv->out_data_toggle[devnum][ep];
963 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
966 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
967 unsigned long pipe, void *buffer, int len,
968 struct devrequest *setup)
970 int devnum = usb_pipedevice(pipe);
973 /* For CONTROL endpoint pid should start with DATA1 */
974 int status_direction;
976 if (devnum == priv->root_hub_devnum) {
978 dev->speed = USB_SPEED_HIGH;
979 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
984 pid = DWC2_HC_PID_SETUP;
986 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
987 } while (ret == -EAGAIN);
994 pid = DWC2_HC_PID_DATA1;
996 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
998 act_len += dev->act_len;
999 buffer += dev->act_len;
1000 len -= dev->act_len;
1001 } while (ret == -EAGAIN);
1004 status_direction = usb_pipeout(pipe);
1006 /* No-data CONTROL always ends with an IN transaction */
1007 status_direction = 1;
1011 pid = DWC2_HC_PID_DATA1;
1013 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1014 priv->status_buffer, 0);
1015 } while (ret == -EAGAIN);
1019 dev->act_len = act_len;
1024 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1025 unsigned long pipe, void *buffer, int len, int interval)
1027 unsigned long timeout;
1030 /* FIXME: what is interval? */
1032 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1034 if (get_timer(0) > timeout) {
1035 printf("Timeout poll on interrupt endpoint\n");
1038 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1044 static int dwc2_init_common(struct dwc2_priv *priv)
1046 struct dwc2_core_regs *regs = priv->regs;
1050 snpsid = readl(®s->gsnpsid);
1051 printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
1053 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1054 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1055 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
1059 dwc_otg_core_init(regs);
1060 dwc_otg_core_host_init(regs);
1062 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1063 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1064 DWC2_HPRT0_PRTOVRCURRCHNG,
1067 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1068 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1071 for (i = 0; i < MAX_DEVICE; i++) {
1072 for (j = 0; j < MAX_ENDPOINT; j++) {
1073 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1074 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1081 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1083 /* Put everything in reset. */
1084 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1085 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1086 DWC2_HPRT0_PRTOVRCURRCHNG,
1090 #ifndef CONFIG_DM_USB
1091 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1092 int len, struct devrequest *setup)
1094 return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1097 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1100 return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1103 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1104 int len, int interval)
1106 return _submit_int_msg(&local, dev, pipe, buffer, len, interval);
1109 /* U-Boot USB control interface */
1110 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1112 struct dwc2_priv *priv = &local;
1114 memset(priv, '\0', sizeof(*priv));
1115 priv->root_hub_devnum = 0;
1116 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1117 priv->aligned_buffer = aligned_buffer_addr;
1118 priv->status_buffer = status_buffer_addr;
1120 /* board-dependant init */
1121 if (board_usb_init(index, USB_INIT_HOST))
1124 return dwc2_init_common(priv);
1127 int usb_lowlevel_stop(int index)
1129 dwc2_uninit_common(local.regs);
1135 #ifdef CONFIG_DM_USB
1136 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1137 unsigned long pipe, void *buffer, int length,
1138 struct devrequest *setup)
1140 struct dwc2_priv *priv = dev_get_priv(dev);
1142 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1143 dev->name, udev, udev->dev->name, udev->portnr);
1145 return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1148 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1149 unsigned long pipe, void *buffer, int length)
1151 struct dwc2_priv *priv = dev_get_priv(dev);
1153 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1155 return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1158 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1159 unsigned long pipe, void *buffer, int length,
1162 struct dwc2_priv *priv = dev_get_priv(dev);
1164 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1166 return _submit_int_msg(priv, udev, pipe, buffer, length, interval);
1169 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1171 struct dwc2_priv *priv = dev_get_priv(dev);
1174 addr = dev_get_addr(dev);
1175 if (addr == FDT_ADDR_T_NONE)
1177 priv->regs = (struct dwc2_core_regs *)addr;
1182 static int dwc2_usb_probe(struct udevice *dev)
1184 struct dwc2_priv *priv = dev_get_priv(dev);
1186 return dwc2_init_common(priv);
1189 static int dwc2_usb_remove(struct udevice *dev)
1191 struct dwc2_priv *priv = dev_get_priv(dev);
1193 dwc2_uninit_common(priv->regs);
1198 struct dm_usb_ops dwc2_usb_ops = {
1199 .control = dwc2_submit_control_msg,
1200 .bulk = dwc2_submit_bulk_msg,
1201 .interrupt = dwc2_submit_int_msg,
1204 static const struct udevice_id dwc2_usb_ids[] = {
1205 { .compatible = "brcm,bcm2835-usb" },
1206 { .compatible = "snps,dwc2" },
1210 U_BOOT_DRIVER(usb_dwc2) = {
1213 .of_match = dwc2_usb_ids,
1214 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1215 .probe = dwc2_usb_probe,
1216 .remove = dwc2_usb_remove,
1217 .ops = &dwc2_usb_ops,
1218 .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1219 .flags = DM_FLAG_ALLOC_PRIV_DMA,