drivers/usb/host/dwc2.c

   1 /*
   2  * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
   3  * Copyright (C) 2014 Marek Vasut <marex@denx.de>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <usb.h>
  12 #include <malloc.h>
  13 #include <memalign.h>
  14 #include <phys2bus.h>
  15 #include <usbroothubdes.h>
  16 #include <asm/io.h>
  17
  18 #include "dwc2.h"
  19
  20 /* Use only HC channel 0. */
  21 #define DWC2_HC_CHANNEL                 0
  22
  23 #define DWC2_STATUS_BUF_SIZE            64
  24 #define DWC2_DATA_BUF_SIZE              (64 * 1024)
  25
  26 #define MAX_DEVICE                      16
  27 #define MAX_ENDPOINT                    16
  28
  29 struct dwc2_priv {
  30 #ifdef CONFIG_DM_USB
  31         uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  32         uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  33 #else
  34         uint8_t *aligned_buffer;
  35         uint8_t *status_buffer;
  36 #endif
  37         u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  38         u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  39         struct dwc2_core_regs *regs;
  40         int root_hub_devnum;
  41 };
  42
  43 #ifndef CONFIG_DM_USB
  44 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
  45 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
  46                 ARCH_DMA_MINALIGN);
  47 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
  48                 ARCH_DMA_MINALIGN);
  49
  50 static struct dwc2_priv local;
  51 #endif
  52
  53 /*
  54  * DWC2 IP interface
  55  */
  56 static int wait_for_bit(void *reg, const uint32_t mask, bool set)
  57 {
  58         unsigned int timeout = 1000000;
  59         uint32_t val;
  60
  61         while (--timeout) {
  62                 val = readl(reg);
  63                 if (!set)
  64                         val = ~val;
  65
  66                 if ((val & mask) == mask)
  67                         return 0;
  68
  69                 udelay(1);
  70         }
  71
  72         debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
  73               __func__, reg, mask, set);
  74
  75         return -ETIMEDOUT;
  76 }
  77
  78 /*
  79  * Initializes the FSLSPClkSel field of the HCFG register
  80  * depending on the PHY type.
  81  */
  82 static void init_fslspclksel(struct dwc2_core_regs *regs)
  83 {
  84         uint32_t phyclk;
  85
  86 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
  87         phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
  88 #else
  89         /* High speed PHY running at full speed or high speed */
  90         phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
  91 #endif
  92
  93 #ifdef CONFIG_DWC2_ULPI_FS_LS
  94         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
  95         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
  96                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
  97         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
  98                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
  99
 100         if (hval == 2 && fval == 1)
 101                 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
 102 #endif
 103
 104         clrsetbits_le32(&regs->host_regs.hcfg,
 105                         DWC2_HCFG_FSLSPCLKSEL_MASK,
 106                         phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
 107 }
 108
 109 /*
 110  * Flush a Tx FIFO.
 111  *
 112  * @param regs Programming view of DWC_otg controller.
 113  * @param num Tx FIFO to flush.
 114  */
 115 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
 116 {
 117         int ret;
 118
 119         writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
 120                &regs->grstctl);
 121         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH, 0);
 122         if (ret)
 123                 printf("%s: Timeout!\n", __func__);
 124
 125         /* Wait for 3 PHY Clocks */
 126         udelay(1);
 127 }
 128
 129 /*
 130  * Flush Rx FIFO.
 131  *
 132  * @param regs Programming view of DWC_otg controller.
 133  */
 134 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
 135 {
 136         int ret;
 137
 138         writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
 139         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH, 0);
 140         if (ret)
 141                 printf("%s: Timeout!\n", __func__);
 142
 143         /* Wait for 3 PHY Clocks */
 144         udelay(1);
 145 }
 146
 147 /*
 148  * Do core a soft reset of the core.  Be careful with this because it
 149  * resets all the internal state machines of the core.
 150  */
 151 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
 152 {
 153         int ret;
 154
 155         /* Wait for AHB master IDLE state. */
 156         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE, 1);
 157         if (ret)
 158                 printf("%s: Timeout!\n", __func__);
 159
 160         /* Core Soft Reset */
 161         writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
 162         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_CSFTRST, 0);
 163         if (ret)
 164                 printf("%s: Timeout!\n", __func__);
 165
 166         /*
 167          * Wait for core to come out of reset.
 168          * NOTE: This long sleep is _very_ important, otherwise the core will
 169          *       not stay in host mode after a connector ID change!
 170          */
 171         mdelay(100);
 172 }
 173
 174 /*
 175  * This function initializes the DWC_otg controller registers for
 176  * host mode.
 177  *
 178  * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
 179  * request queues. Host channels are reset to ensure that they are ready for
 180  * performing transfers.
 181  *
 182  * @param regs Programming view of DWC_otg controller
 183  *
 184  */
 185 static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
 186 {
 187         uint32_t nptxfifosize = 0;
 188         uint32_t ptxfifosize = 0;
 189         uint32_t hprt0 = 0;
 190         int i, ret, num_channels;
 191
 192         /* Restart the Phy Clock */
 193         writel(0, &regs->pcgcctl);
 194
 195         /* Initialize Host Configuration Register */
 196         init_fslspclksel(regs);
 197 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
 198         setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
 199 #endif
 200
 201         /* Configure data FIFO sizes */
 202 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
 203         if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
 204                 /* Rx FIFO */
 205                 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
 206
 207                 /* Non-periodic Tx FIFO */
 208                 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
 209                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 210                 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
 211                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 212                 writel(nptxfifosize, &regs->gnptxfsiz);
 213
 214                 /* Periodic Tx FIFO */
 215                 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
 216                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 217                 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
 218                                 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
 219                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 220                 writel(ptxfifosize, &regs->hptxfsiz);
 221         }
 222 #endif
 223
 224         /* Clear Host Set HNP Enable in the OTG Control Register */
 225         clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
 226
 227         /* Make sure the FIFOs are flushed. */
 228         dwc_otg_flush_tx_fifo(regs, 0x10);      /* All Tx FIFOs */
 229         dwc_otg_flush_rx_fifo(regs);
 230
 231         /* Flush out any leftover queued requests. */
 232         num_channels = readl(&regs->ghwcfg2);
 233         num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
 234         num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
 235         num_channels += 1;
 236
 237         for (i = 0; i < num_channels; i++)
 238                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 239                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
 240                                 DWC2_HCCHAR_CHDIS);
 241
 242         /* Halt all channels to put them into a known state. */
 243         for (i = 0; i < num_channels; i++) {
 244                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 245                                 DWC2_HCCHAR_EPDIR,
 246                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
 247                 ret = wait_for_bit(&regs->hc_regs[i].hcchar,
 248                                    DWC2_HCCHAR_CHEN, 0);
 249                 if (ret)
 250                         printf("%s: Timeout!\n", __func__);
 251         }
 252
 253         /* Turn on the vbus power. */
 254         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
 255                 hprt0 = readl(&regs->hprt0);
 256                 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
 257                 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
 258                 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
 259                         hprt0 |= DWC2_HPRT0_PRTPWR;
 260                         writel(hprt0, &regs->hprt0);
 261                 }
 262         }
 263 }
 264
 265 /*
 266  * This function initializes the DWC_otg controller registers and
 267  * prepares the core for device mode or host mode operation.
 268  *
 269  * @param regs Programming view of the DWC_otg controller
 270  */
 271 static void dwc_otg_core_init(struct dwc2_core_regs *regs)
 272 {
 273         uint32_t ahbcfg = 0;
 274         uint32_t usbcfg = 0;
 275         uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
 276
 277         /* Common Initialization */
 278         usbcfg = readl(&regs->gusbcfg);
 279
 280         /* Program the ULPI External VBUS bit if needed */
 281 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
 282         usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 283 #else
 284         usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 285 #endif
 286
 287         /* Set external TS Dline pulsing */
 288 #ifdef CONFIG_DWC2_TS_DLINE
 289         usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 290 #else
 291         usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 292 #endif
 293         writel(usbcfg, &regs->gusbcfg);
 294
 295         /* Reset the Controller */
 296         dwc_otg_core_reset(regs);
 297
 298         /*
 299          * This programming sequence needs to happen in FS mode before
 300          * any other programming occurs
 301          */
 302 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
 303         (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
 304         /* If FS mode with FS PHY */
 305         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
 306
 307         /* Reset after a PHY select */
 308         dwc_otg_core_reset(regs);
 309
 310         /*
 311          * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
 312          * Also do this on HNP Dev/Host mode switches (done in dev_init
 313          * and host_init).
 314          */
 315         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
 316                 init_fslspclksel(regs);
 317
 318 #ifdef CONFIG_DWC2_I2C_ENABLE
 319         /* Program GUSBCFG.OtgUtmifsSel to I2C */
 320         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
 321
 322         /* Program GI2CCTL.I2CEn */
 323         clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
 324                         DWC2_GI2CCTL_I2CDEVADDR_MASK,
 325                         1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
 326         setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
 327 #endif
 328
 329 #else
 330         /* High speed PHY. */
 331
 332         /*
 333          * HS PHY parameters. These parameters are preserved during
 334          * soft reset so only program the first time. Do a soft reset
 335          * immediately after setting phyif.
 336          */
 337         usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
 338         usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
 339
 340         if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) {      /* ULPI interface */
 341 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
 342                 usbcfg |= DWC2_GUSBCFG_DDRSEL;
 343 #else
 344                 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
 345 #endif
 346         } else {        /* UTMI+ interface */
 347 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
 348                 usbcfg |= DWC2_GUSBCFG_PHYIF;
 349 #endif
 350         }
 351
 352         writel(usbcfg, &regs->gusbcfg);
 353
 354         /* Reset after setting the PHY parameters */
 355         dwc_otg_core_reset(regs);
 356 #endif
 357
 358         usbcfg = readl(&regs->gusbcfg);
 359         usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
 360 #ifdef CONFIG_DWC2_ULPI_FS_LS
 361         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
 362         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
 363                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
 364         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
 365                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
 366         if (hval == 2 && fval == 1) {
 367                 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
 368                 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
 369         }
 370 #endif
 371         writel(usbcfg, &regs->gusbcfg);
 372
 373         /* Program the GAHBCFG Register. */
 374         switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
 375         case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
 376                 break;
 377         case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
 378                 while (brst_sz > 1) {
 379                         ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
 380                         ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
 381                         brst_sz >>= 1;
 382                 }
 383
 384 #ifdef CONFIG_DWC2_DMA_ENABLE
 385                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 386 #endif
 387                 break;
 388
 389         case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
 390                 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
 391 #ifdef CONFIG_DWC2_DMA_ENABLE
 392                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 393 #endif
 394                 break;
 395         }
 396
 397         writel(ahbcfg, &regs->gahbcfg);
 398
 399         /* Program the GUSBCFG register for HNP/SRP. */
 400         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
 401
 402 #ifdef CONFIG_DWC2_IC_USB_CAP
 403         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
 404 #endif
 405 }
 406
 407 /*
 408  * Prepares a host channel for transferring packets to/from a specific
 409  * endpoint. The HCCHARn register is set up with the characteristics specified
 410  * in _hc. Host channel interrupts that may need to be serviced while this
 411  * transfer is in progress are enabled.
 412  *
 413  * @param regs Programming view of DWC_otg controller
 414  * @param hc Information needed to initialize the host channel
 415  */
 416 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
 417                 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
 418                 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
 419 {
 420         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
 421         uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
 422                           (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
 423                           (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
 424                           (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
 425                           (max_packet << DWC2_HCCHAR_MPS_OFFSET);
 426
 427         if (dev->speed == USB_SPEED_LOW)
 428                 hcchar |= DWC2_HCCHAR_LSPDDEV;
 429
 430         /*
 431          * Program the HCCHARn register with the endpoint characteristics
 432          * for the current transfer.
 433          */
 434         writel(hcchar, &hc_regs->hcchar);
 435
 436         /* Program the HCSPLIT register, default to no SPLIT */
 437         writel(0, &hc_regs->hcsplt);
 438 }
 439
 440 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
 441                                   uint8_t hub_devnum, uint8_t hub_port)
 442 {
 443         uint32_t hcsplt = 0;
 444
 445         hcsplt = DWC2_HCSPLT_SPLTENA;
 446         hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
 447         hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
 448
 449         /* Program the HCSPLIT register for SPLITs */
 450         writel(hcsplt, &hc_regs->hcsplt);
 451 }
 452
 453 /*
 454  * DWC2 to USB API interface
 455  */
 456 /* Direction: In ; Request: Status */
 457 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
 458                                            struct usb_device *dev, void *buffer,
 459                                            int txlen, struct devrequest *cmd)
 460 {
 461         uint32_t hprt0 = 0;
 462         uint32_t port_status = 0;
 463         uint32_t port_change = 0;
 464         int len = 0;
 465         int stat = 0;
 466
 467         switch (cmd->requesttype & ~USB_DIR_IN) {
 468         case 0:
 469                 *(uint16_t *)buffer = cpu_to_le16(1);
 470                 len = 2;
 471                 break;
 472         case USB_RECIP_INTERFACE:
 473         case USB_RECIP_ENDPOINT:
 474                 *(uint16_t *)buffer = cpu_to_le16(0);
 475                 len = 2;
 476                 break;
 477         case USB_TYPE_CLASS:
 478                 *(uint32_t *)buffer = cpu_to_le32(0);
 479                 len = 4;
 480                 break;
 481         case USB_RECIP_OTHER | USB_TYPE_CLASS:
 482                 hprt0 = readl(&regs->hprt0);
 483                 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
 484                         port_status |= USB_PORT_STAT_CONNECTION;
 485                 if (hprt0 & DWC2_HPRT0_PRTENA)
 486                         port_status |= USB_PORT_STAT_ENABLE;
 487                 if (hprt0 & DWC2_HPRT0_PRTSUSP)
 488                         port_status |= USB_PORT_STAT_SUSPEND;
 489                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
 490                         port_status |= USB_PORT_STAT_OVERCURRENT;
 491                 if (hprt0 & DWC2_HPRT0_PRTRST)
 492                         port_status |= USB_PORT_STAT_RESET;
 493                 if (hprt0 & DWC2_HPRT0_PRTPWR)
 494                         port_status |= USB_PORT_STAT_POWER;
 495
 496                 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
 497                         port_status |= USB_PORT_STAT_LOW_SPEED;
 498                 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
 499                          DWC2_HPRT0_PRTSPD_HIGH)
 500                         port_status |= USB_PORT_STAT_HIGH_SPEED;
 501
 502                 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
 503                         port_change |= USB_PORT_STAT_C_ENABLE;
 504                 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
 505                         port_change |= USB_PORT_STAT_C_CONNECTION;
 506                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
 507                         port_change |= USB_PORT_STAT_C_OVERCURRENT;
 508
 509                 *(uint32_t *)buffer = cpu_to_le32(port_status |
 510                                         (port_change << 16));
 511                 len = 4;
 512                 break;
 513         default:
 514                 puts("unsupported root hub command\n");
 515                 stat = USB_ST_STALLED;
 516         }
 517
 518         dev->act_len = min(len, txlen);
 519         dev->status = stat;
 520
 521         return stat;
 522 }
 523
 524 /* Direction: In ; Request: Descriptor */
 525 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
 526                                                void *buffer, int txlen,
 527                                                struct devrequest *cmd)
 528 {
 529         unsigned char data[32];
 530         uint32_t dsc;
 531         int len = 0;
 532         int stat = 0;
 533         uint16_t wValue = cpu_to_le16(cmd->value);
 534         uint16_t wLength = cpu_to_le16(cmd->length);
 535
 536         switch (cmd->requesttype & ~USB_DIR_IN) {
 537         case 0:
 538                 switch (wValue & 0xff00) {
 539                 case 0x0100:    /* device descriptor */
 540                         len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
 541                         memcpy(buffer, root_hub_dev_des, len);
 542                         break;
 543                 case 0x0200:    /* configuration descriptor */
 544                         len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
 545                         memcpy(buffer, root_hub_config_des, len);
 546                         break;
 547                 case 0x0300:    /* string descriptors */
 548                         switch (wValue & 0xff) {
 549                         case 0x00:
 550                                 len = min3(txlen, (int)sizeof(root_hub_str_index0),
 551                                            (int)wLength);
 552                                 memcpy(buffer, root_hub_str_index0, len);
 553                                 break;
 554                         case 0x01:
 555                                 len = min3(txlen, (int)sizeof(root_hub_str_index1),
 556                                            (int)wLength);
 557                                 memcpy(buffer, root_hub_str_index1, len);
 558                                 break;
 559                         }
 560                         break;
 561                 default:
 562                         stat = USB_ST_STALLED;
 563                 }
 564                 break;
 565
 566         case USB_TYPE_CLASS:
 567                 /* Root port config, set 1 port and nothing else. */
 568                 dsc = 0x00000001;
 569
 570                 data[0] = 9;            /* min length; */
 571                 data[1] = 0x29;
 572                 data[2] = dsc & RH_A_NDP;
 573                 data[3] = 0;
 574                 if (dsc & RH_A_PSM)
 575                         data[3] |= 0x1;
 576                 if (dsc & RH_A_NOCP)
 577                         data[3] |= 0x10;
 578                 else if (dsc & RH_A_OCPM)
 579                         data[3] |= 0x8;
 580
 581                 /* corresponds to data[4-7] */
 582                 data[5] = (dsc & RH_A_POTPGT) >> 24;
 583                 data[7] = dsc & RH_B_DR;
 584                 if (data[2] < 7) {
 585                         data[8] = 0xff;
 586                 } else {
 587                         data[0] += 2;
 588                         data[8] = (dsc & RH_B_DR) >> 8;
 589                         data[9] = 0xff;
 590                         data[10] = data[9];
 591                 }
 592
 593                 len = min3(txlen, (int)data[0], (int)wLength);
 594                 memcpy(buffer, data, len);
 595                 break;
 596         default:
 597                 puts("unsupported root hub command\n");
 598                 stat = USB_ST_STALLED;
 599         }
 600
 601         dev->act_len = min(len, txlen);
 602         dev->status = stat;
 603
 604         return stat;
 605 }
 606
 607 /* Direction: In ; Request: Configuration */
 608 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
 609                                                   void *buffer, int txlen,
 610                                                   struct devrequest *cmd)
 611 {
 612         int len = 0;
 613         int stat = 0;
 614
 615         switch (cmd->requesttype & ~USB_DIR_IN) {
 616         case 0:
 617                 *(uint8_t *)buffer = 0x01;
 618                 len = 1;
 619                 break;
 620         default:
 621                 puts("unsupported root hub command\n");
 622                 stat = USB_ST_STALLED;
 623         }
 624
 625         dev->act_len = min(len, txlen);
 626         dev->status = stat;
 627
 628         return stat;
 629 }
 630
 631 /* Direction: In */
 632 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
 633                                     struct usb_device *dev, void *buffer,
 634                                     int txlen, struct devrequest *cmd)
 635 {
 636         switch (cmd->request) {
 637         case USB_REQ_GET_STATUS:
 638                 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
 639                                                        txlen, cmd);
 640         case USB_REQ_GET_DESCRIPTOR:
 641                 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
 642                                                            txlen, cmd);
 643         case USB_REQ_GET_CONFIGURATION:
 644                 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
 645                                                               txlen, cmd);
 646         default:
 647                 puts("unsupported root hub command\n");
 648                 return USB_ST_STALLED;
 649         }
 650 }
 651
 652 /* Direction: Out */
 653 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
 654                                      struct usb_device *dev,
 655                                      void *buffer, int txlen,
 656                                      struct devrequest *cmd)
 657 {
 658         struct dwc2_core_regs *regs = priv->regs;
 659         int len = 0;
 660         int stat = 0;
 661         uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
 662         uint16_t wValue = cpu_to_le16(cmd->value);
 663
 664         switch (bmrtype_breq & ~USB_DIR_IN) {
 665         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
 666         case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
 667                 break;
 668
 669         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 670                 switch (wValue) {
 671                 case USB_PORT_FEAT_C_CONNECTION:
 672                         setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
 673                         break;
 674                 }
 675                 break;
 676
 677         case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 678                 switch (wValue) {
 679                 case USB_PORT_FEAT_SUSPEND:
 680                         break;
 681
 682                 case USB_PORT_FEAT_RESET:
 683                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 684                                         DWC2_HPRT0_PRTCONNDET |
 685                                         DWC2_HPRT0_PRTENCHNG |
 686                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 687                                         DWC2_HPRT0_PRTRST);
 688                         mdelay(50);
 689                         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
 690                         break;
 691
 692                 case USB_PORT_FEAT_POWER:
 693                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 694                                         DWC2_HPRT0_PRTCONNDET |
 695                                         DWC2_HPRT0_PRTENCHNG |
 696                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 697                                         DWC2_HPRT0_PRTRST);
 698                         break;
 699
 700                 case USB_PORT_FEAT_ENABLE:
 701                         break;
 702                 }
 703                 break;
 704         case (USB_REQ_SET_ADDRESS << 8):
 705                 priv->root_hub_devnum = wValue;
 706                 break;
 707         case (USB_REQ_SET_CONFIGURATION << 8):
 708                 break;
 709         default:
 710                 puts("unsupported root hub command\n");
 711                 stat = USB_ST_STALLED;
 712         }
 713
 714         len = min(len, txlen);
 715
 716         dev->act_len = len;
 717         dev->status = stat;
 718
 719         return stat;
 720 }
 721
 722 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
 723                                  unsigned long pipe, void *buffer, int txlen,
 724                                  struct devrequest *cmd)
 725 {
 726         int stat = 0;
 727
 728         if (usb_pipeint(pipe)) {
 729                 puts("Root-Hub submit IRQ: NOT implemented\n");
 730                 return 0;
 731         }
 732
 733         if (cmd->requesttype & USB_DIR_IN)
 734                 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
 735         else
 736                 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
 737
 738         mdelay(1);
 739
 740         return stat;
 741 }
 742
 743 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
 744 {
 745         int ret;
 746         uint32_t hcint, hctsiz;
 747
 748         ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true);
 749         if (ret)
 750                 return ret;
 751
 752         hcint = readl(&hc_regs->hcint);
 753         hctsiz = readl(&hc_regs->hctsiz);
 754         *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
 755                 DWC2_HCTSIZ_XFERSIZE_OFFSET;
 756         *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
 757
 758         debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
 759               *toggle);
 760
 761         if (hcint & DWC2_HCINT_XFERCOMP)
 762                 return 0;
 763
 764         if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
 765                 return -EAGAIN;
 766
 767         debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
 768         return -EINVAL;
 769 }
 770
 771 static int dwc2_eptype[] = {
 772         DWC2_HCCHAR_EPTYPE_ISOC,
 773         DWC2_HCCHAR_EPTYPE_INTR,
 774         DWC2_HCCHAR_EPTYPE_CONTROL,
 775         DWC2_HCCHAR_EPTYPE_BULK,
 776 };
 777
 778 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
 779                           u8 *pid, int in, void *buffer, int num_packets,
 780                           int xfer_len, int *actual_len, int odd_frame)
 781 {
 782         int ret = 0;
 783         uint32_t sub;
 784
 785         debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
 786               *pid, xfer_len, num_packets);
 787
 788         writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
 789                (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
 790                (*pid << DWC2_HCTSIZ_PID_OFFSET),
 791                &hc_regs->hctsiz);
 792
 793         if (!in && xfer_len) {
 794                 memcpy(aligned_buffer, buffer, xfer_len);
 795
 796                 flush_dcache_range((unsigned long)aligned_buffer,
 797                                    (unsigned long)aligned_buffer +
 798                                    roundup(xfer_len, ARCH_DMA_MINALIGN));
 799         }
 800
 801         writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
 802
 803         /* Clear old interrupt conditions for this host channel. */
 804         writel(0x3fff, &hc_regs->hcint);
 805
 806         /* Set host channel enable after all other setup is complete. */
 807         clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
 808                         DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
 809                         DWC2_HCCHAR_ODDFRM,
 810                         (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
 811                         (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
 812                         DWC2_HCCHAR_CHEN);
 813
 814         ret = wait_for_chhltd(hc_regs, &sub, pid);
 815         if (ret < 0)
 816                 return ret;
 817
 818         if (in) {
 819                 xfer_len -= sub;
 820
 821                 invalidate_dcache_range((unsigned long)aligned_buffer,
 822                                         (unsigned long)aligned_buffer +
 823                                         roundup(xfer_len, ARCH_DMA_MINALIGN));
 824
 825                 memcpy(buffer, aligned_buffer, xfer_len);
 826         }
 827         *actual_len = xfer_len;
 828
 829         return ret;
 830 }
 831
 832 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
 833               unsigned long pipe, u8 *pid, int in, void *buffer, int len)
 834 {
 835         struct dwc2_core_regs *regs = priv->regs;
 836         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
 837         struct dwc2_host_regs *host_regs = &regs->host_regs;
 838         int devnum = usb_pipedevice(pipe);
 839         int ep = usb_pipeendpoint(pipe);
 840         int max = usb_maxpacket(dev, pipe);
 841         int eptype = dwc2_eptype[usb_pipetype(pipe)];
 842         int done = 0;
 843         int ret = 0;
 844         int do_split = 0;
 845         int complete_split = 0;
 846         uint32_t xfer_len;
 847         uint32_t num_packets;
 848         int stop_transfer = 0;
 849         uint32_t max_xfer_len;
 850         int ssplit_frame_num = 0;
 851
 852         debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
 853               in, len);
 854
 855         max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
 856         if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
 857                 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
 858         if (max_xfer_len > DWC2_DATA_BUF_SIZE)
 859                 max_xfer_len = DWC2_DATA_BUF_SIZE;
 860
 861         /* Make sure that max_xfer_len is a multiple of max packet size. */
 862         num_packets = max_xfer_len / max;
 863         max_xfer_len = num_packets * max;
 864
 865         /* Initialize channel */
 866         dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
 867                         eptype, max);
 868
 869         /* Check if the target is a FS/LS device behind a HS hub */
 870         if (dev->speed != USB_SPEED_HIGH) {
 871                 uint8_t hub_addr;
 872                 uint8_t hub_port;
 873                 uint32_t hprt0 = readl(&regs->hprt0);
 874                 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
 875                      DWC2_HPRT0_PRTSPD_HIGH) {
 876                         usb_find_usb2_hub_address_port(dev, &hub_addr,
 877                                                        &hub_port);
 878                         dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
 879
 880                         do_split = 1;
 881                         num_packets = 1;
 882                         max_xfer_len = max;
 883                 }
 884         }
 885
 886         do {
 887                 int actual_len = 0;
 888                 uint32_t hcint;
 889                 int odd_frame = 0;
 890                 xfer_len = len - done;
 891
 892                 if (xfer_len > max_xfer_len)
 893                         xfer_len = max_xfer_len;
 894                 else if (xfer_len > max)
 895                         num_packets = (xfer_len + max - 1) / max;
 896                 else
 897                         num_packets = 1;
 898
 899                 if (complete_split)
 900                         setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
 901                 else if (do_split)
 902                         clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
 903
 904                 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
 905                         int uframe_num = readl(&host_regs->hfnum);
 906                         if (!(uframe_num & 0x1))
 907                                 odd_frame = 1;
 908                 }
 909
 910                 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
 911                                      in, (char *)buffer + done, num_packets,
 912                                      xfer_len, &actual_len, odd_frame);
 913
 914                 hcint = readl(&hc_regs->hcint);
 915                 if (complete_split) {
 916                         stop_transfer = 0;
 917                         if (hcint & DWC2_HCINT_NYET) {
 918                                 ret = 0;
 919                                 int frame_num = DWC2_HFNUM_MAX_FRNUM &
 920                                                 readl(&host_regs->hfnum);
 921                                 if (((frame_num - ssplit_frame_num) &
 922                                     DWC2_HFNUM_MAX_FRNUM) > 4)
 923                                         ret = -EAGAIN;
 924                         } else
 925                                 complete_split = 0;
 926                 } else if (do_split) {
 927                         if (hcint & DWC2_HCINT_ACK) {
 928                                 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
 929                                                    readl(&host_regs->hfnum);
 930                                 ret = 0;
 931                                 complete_split = 1;
 932                         }
 933                 }
 934
 935                 if (ret)
 936                         break;
 937
 938                 if (actual_len < xfer_len)
 939                         stop_transfer = 1;
 940
 941                 done += actual_len;
 942
 943         /* Transactions are done when when either all data is transferred or
 944          * there is a short transfer. In case of a SPLIT make sure the CSPLIT
 945          * is executed.
 946          */
 947         } while (((done < len) && !stop_transfer) || complete_split);
 948
 949         writel(0, &hc_regs->hcintmsk);
 950         writel(0xFFFFFFFF, &hc_regs->hcint);
 951
 952         dev->status = 0;
 953         dev->act_len = done;
 954
 955         return ret;
 956 }
 957
 958 /* U-Boot USB transmission interface */
 959 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
 960                      unsigned long pipe, void *buffer, int len)
 961 {
 962         int devnum = usb_pipedevice(pipe);
 963         int ep = usb_pipeendpoint(pipe);
 964         u8* pid;
 965
 966         if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
 967                 dev->status = 0;
 968                 return -EINVAL;
 969         }
 970
 971         if (usb_pipein(pipe))
 972                 pid = &priv->in_data_toggle[devnum][ep];
 973         else
 974                 pid = &priv->out_data_toggle[devnum][ep];
 975
 976         return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
 977 }
 978
 979 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
 980                                unsigned long pipe, void *buffer, int len,
 981                                struct devrequest *setup)
 982 {
 983         int devnum = usb_pipedevice(pipe);
 984         int ret, act_len;
 985         u8 pid;
 986         /* For CONTROL endpoint pid should start with DATA1 */
 987         int status_direction;
 988
 989         if (devnum == priv->root_hub_devnum) {
 990                 dev->status = 0;
 991                 dev->speed = USB_SPEED_HIGH;
 992                 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
 993                                              setup);
 994         }
 995
 996         /* SETUP stage */
 997         pid = DWC2_HC_PID_SETUP;
 998         do {
 999                 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
1000         } while (ret == -EAGAIN);
1001         if (ret)
1002                 return ret;
1003
1004         /* DATA stage */
1005         act_len = 0;
1006         if (buffer) {
1007                 pid = DWC2_HC_PID_DATA1;
1008                 do {
1009                         ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
1010                                         buffer, len);
1011                         act_len += dev->act_len;
1012                         buffer += dev->act_len;
1013                         len -= dev->act_len;
1014                 } while (ret == -EAGAIN);
1015                 if (ret)
1016                         return ret;
1017                 status_direction = usb_pipeout(pipe);
1018         } else {
1019                 /* No-data CONTROL always ends with an IN transaction */
1020                 status_direction = 1;
1021         }
1022
1023         /* STATUS stage */
1024         pid = DWC2_HC_PID_DATA1;
1025         do {
1026                 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1027                                 priv->status_buffer, 0);
1028         } while (ret == -EAGAIN);
1029         if (ret)
1030                 return ret;
1031
1032         dev->act_len = act_len;
1033
1034         return 0;
1035 }
1036
1037 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1038                     unsigned long pipe, void *buffer, int len, int interval)
1039 {
1040         unsigned long timeout;
1041         int ret;
1042
1043         /* FIXME: what is interval? */
1044
1045         timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1046         for (;;) {
1047                 if (get_timer(0) > timeout) {
1048                         printf("Timeout poll on interrupt endpoint\n");
1049                         return -ETIMEDOUT;
1050                 }
1051                 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1052                 if (ret != -EAGAIN)
1053                         return ret;
1054         }
1055 }
1056
1057 static int dwc2_init_common(struct dwc2_priv *priv)
1058 {
1059         struct dwc2_core_regs *regs = priv->regs;
1060         uint32_t snpsid;
1061         int i, j;
1062
1063         snpsid = readl(&regs->gsnpsid);
1064         printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
1065
1066         if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1067             (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1068                 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
1069                 return -ENODEV;
1070         }
1071
1072         dwc_otg_core_init(regs);
1073         dwc_otg_core_host_init(regs);
1074
1075         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1076                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1077                         DWC2_HPRT0_PRTOVRCURRCHNG,
1078                         DWC2_HPRT0_PRTRST);
1079         mdelay(50);
1080         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1081                      DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1082                      DWC2_HPRT0_PRTRST);
1083
1084         for (i = 0; i < MAX_DEVICE; i++) {
1085                 for (j = 0; j < MAX_ENDPOINT; j++) {
1086                         priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1087                         priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1088                 }
1089         }
1090
1091         return 0;
1092 }
1093
1094 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1095 {
1096         /* Put everything in reset. */
1097         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
1098                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1099                         DWC2_HPRT0_PRTOVRCURRCHNG,
1100                         DWC2_HPRT0_PRTRST);
1101 }
1102
1103 #ifndef CONFIG_DM_USB
1104 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1105                        int len, struct devrequest *setup)
1106 {
1107         return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1108 }
1109
1110 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1111                     int len)
1112 {
1113         return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1114 }
1115
1116 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1117                    int len, int interval)
1118 {
1119         return _submit_int_msg(&local, dev, pipe, buffer, len, interval);
1120 }
1121
1122 /* U-Boot USB control interface */
1123 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1124 {
1125         struct dwc2_priv *priv = &local;
1126
1127         memset(priv, '\0', sizeof(*priv));
1128         priv->root_hub_devnum = 0;
1129         priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1130         priv->aligned_buffer = aligned_buffer_addr;
1131         priv->status_buffer = status_buffer_addr;
1132
1133         /* board-dependant init */
1134         if (board_usb_init(index, USB_INIT_HOST))
1135                 return -1;
1136
1137         return dwc2_init_common(priv);
1138 }
1139
1140 int usb_lowlevel_stop(int index)
1141 {
1142         dwc2_uninit_common(local.regs);
1143
1144         return 0;
1145 }
1146 #endif
1147
1148 #ifdef CONFIG_DM_USB
1149 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1150                                    unsigned long pipe, void *buffer, int length,
1151                                    struct devrequest *setup)
1152 {
1153         struct dwc2_priv *priv = dev_get_priv(dev);
1154
1155         debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1156               dev->name, udev, udev->dev->name, udev->portnr);
1157
1158         return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1159 }
1160
1161 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1162                                 unsigned long pipe, void *buffer, int length)
1163 {
1164         struct dwc2_priv *priv = dev_get_priv(dev);
1165
1166         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1167
1168         return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1169 }
1170
1171 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1172                                unsigned long pipe, void *buffer, int length,
1173                                int interval)
1174 {
1175         struct dwc2_priv *priv = dev_get_priv(dev);
1176
1177         debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1178
1179         return _submit_int_msg(priv, udev, pipe, buffer, length, interval);
1180 }
1181
1182 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1183 {
1184         struct dwc2_priv *priv = dev_get_priv(dev);
1185         fdt_addr_t addr;
1186
1187         addr = dev_get_addr(dev);
1188         if (addr == FDT_ADDR_T_NONE)
1189                 return -EINVAL;
1190         priv->regs = (struct dwc2_core_regs *)addr;
1191
1192         return 0;
1193 }
1194
1195 static int dwc2_usb_probe(struct udevice *dev)
1196 {
1197         struct dwc2_priv *priv = dev_get_priv(dev);
1198
1199         return dwc2_init_common(priv);
1200 }
1201
1202 static int dwc2_usb_remove(struct udevice *dev)
1203 {
1204         struct dwc2_priv *priv = dev_get_priv(dev);
1205
1206         dwc2_uninit_common(priv->regs);
1207
1208         return 0;
1209 }
1210
1211 struct dm_usb_ops dwc2_usb_ops = {
1212         .control = dwc2_submit_control_msg,
1213         .bulk = dwc2_submit_bulk_msg,
1214         .interrupt = dwc2_submit_int_msg,
1215 };
1216
1217 static const struct udevice_id dwc2_usb_ids[] = {
1218         { .compatible = "brcm,bcm2835-usb" },
1219         { .compatible = "snps,dwc2" },
1220         { }
1221 };
1222
1223 U_BOOT_DRIVER(usb_dwc2) = {
1224         .name   = "dwc2_usb",
1225         .id     = UCLASS_USB,
1226         .of_match = dwc2_usb_ids,
1227         .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1228         .probe  = dwc2_usb_probe,
1229         .remove = dwc2_usb_remove,
1230         .ops    = &dwc2_usb_ops,
1231         .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1232         .flags  = DM_FLAG_ALLOC_PRIV_DMA,
1233 };
1234 #endif