2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
15 #include <usbroothubdes.h>
18 #include <power/regulator.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 /* Use only HC channel 0. */
25 #define DWC2_HC_CHANNEL 0
27 #define DWC2_STATUS_BUF_SIZE 64
28 #define DWC2_DATA_BUF_SIZE (64 * 1024)
31 #define MAX_ENDPOINT 16
35 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
36 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
38 uint8_t *aligned_buffer;
39 uint8_t *status_buffer;
41 u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
42 u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
43 struct dwc2_core_regs *regs;
50 /* We need cacheline-aligned buffers for DMA transfers and dcache support */
51 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
53 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
56 static struct dwc2_priv local;
64 * Initializes the FSLSPClkSel field of the HCFG register
65 * depending on the PHY type.
67 static void init_fslspclksel(struct dwc2_core_regs *regs)
71 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
72 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
74 /* High speed PHY running at full speed or high speed */
75 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
78 #ifdef CONFIG_DWC2_ULPI_FS_LS
79 uint32_t hwcfg2 = readl(®s->ghwcfg2);
80 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
81 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
82 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
83 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
85 if (hval == 2 && fval == 1)
86 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
89 clrsetbits_le32(®s->host_regs.hcfg,
90 DWC2_HCFG_FSLSPCLKSEL_MASK,
91 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
97 * @param regs Programming view of DWC_otg controller.
98 * @param num Tx FIFO to flush.
100 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
104 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
106 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_TXFFLSH,
109 printf("%s: Timeout!\n", __func__);
111 /* Wait for 3 PHY Clocks */
118 * @param regs Programming view of DWC_otg controller.
120 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
124 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl);
125 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_RXFFLSH,
128 printf("%s: Timeout!\n", __func__);
130 /* Wait for 3 PHY Clocks */
135 * Do core a soft reset of the core. Be careful with this because it
136 * resets all the internal state machines of the core.
138 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
142 /* Wait for AHB master IDLE state. */
143 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_AHBIDLE,
146 printf("%s: Timeout!\n", __func__);
148 /* Core Soft Reset */
149 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl);
150 ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_CSFTRST,
153 printf("%s: Timeout!\n", __func__);
156 * Wait for core to come out of reset.
157 * NOTE: This long sleep is _very_ important, otherwise the core will
158 * not stay in host mode after a connector ID change!
163 #if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR)
164 static int dwc_vbus_supply_init(struct udevice *dev)
166 struct udevice *vbus_supply;
169 ret = device_get_supply_regulator(dev, "vbus-supply", &vbus_supply);
171 debug("%s: No vbus supply\n", dev->name);
175 ret = regulator_set_enable(vbus_supply, true);
177 error("Error enabling vbus supply\n");
184 static int dwc_vbus_supply_init(struct udevice *dev)
191 * This function initializes the DWC_otg controller registers for
194 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
195 * request queues. Host channels are reset to ensure that they are ready for
196 * performing transfers.
198 * @param dev USB Device (NULL if driver model is not being used)
199 * @param regs Programming view of DWC_otg controller
202 static void dwc_otg_core_host_init(struct udevice *dev,
203 struct dwc2_core_regs *regs)
205 uint32_t nptxfifosize = 0;
206 uint32_t ptxfifosize = 0;
208 int i, ret, num_channels;
210 /* Restart the Phy Clock */
211 writel(0, ®s->pcgcctl);
213 /* Initialize Host Configuration Register */
214 init_fslspclksel(regs);
215 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
216 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
219 /* Configure data FIFO sizes */
220 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
221 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
223 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
225 /* Non-periodic Tx FIFO */
226 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
227 DWC2_FIFOSIZE_DEPTH_OFFSET;
228 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
229 DWC2_FIFOSIZE_STARTADDR_OFFSET;
230 writel(nptxfifosize, ®s->gnptxfsiz);
232 /* Periodic Tx FIFO */
233 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
234 DWC2_FIFOSIZE_DEPTH_OFFSET;
235 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
236 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
237 DWC2_FIFOSIZE_STARTADDR_OFFSET;
238 writel(ptxfifosize, ®s->hptxfsiz);
242 /* Clear Host Set HNP Enable in the OTG Control Register */
243 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
245 /* Make sure the FIFOs are flushed. */
246 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
247 dwc_otg_flush_rx_fifo(regs);
249 /* Flush out any leftover queued requests. */
250 num_channels = readl(®s->ghwcfg2);
251 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
252 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
255 for (i = 0; i < num_channels; i++)
256 clrsetbits_le32(®s->hc_regs[i].hcchar,
257 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
260 /* Halt all channels to put them into a known state. */
261 for (i = 0; i < num_channels; i++) {
262 clrsetbits_le32(®s->hc_regs[i].hcchar,
264 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
265 ret = wait_for_bit(__func__, ®s->hc_regs[i].hcchar,
266 DWC2_HCCHAR_CHEN, false, 1000, false);
268 printf("%s: Timeout!\n", __func__);
271 /* Turn on the vbus power. */
272 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
273 hprt0 = readl(®s->hprt0);
274 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
275 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
276 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
277 hprt0 |= DWC2_HPRT0_PRTPWR;
278 writel(hprt0, ®s->hprt0);
283 dwc_vbus_supply_init(dev);
287 * This function initializes the DWC_otg controller registers and
288 * prepares the core for device mode or host mode operation.
290 * @param regs Programming view of the DWC_otg controller
292 static void dwc_otg_core_init(struct dwc2_priv *priv)
294 struct dwc2_core_regs *regs = priv->regs;
297 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
299 /* Common Initialization */
300 usbcfg = readl(®s->gusbcfg);
302 /* Program the ULPI External VBUS bit if needed */
303 if (priv->ext_vbus) {
304 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
305 if (!priv->oc_disable) {
306 usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
307 DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
310 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
313 /* Set external TS Dline pulsing */
314 #ifdef CONFIG_DWC2_TS_DLINE
315 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
317 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
319 writel(usbcfg, ®s->gusbcfg);
321 /* Reset the Controller */
322 dwc_otg_core_reset(regs);
325 * This programming sequence needs to happen in FS mode before
326 * any other programming occurs
328 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
329 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
330 /* If FS mode with FS PHY */
331 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL);
333 /* Reset after a PHY select */
334 dwc_otg_core_reset(regs);
337 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
338 * Also do this on HNP Dev/Host mode switches (done in dev_init
341 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
342 init_fslspclksel(regs);
344 #ifdef CONFIG_DWC2_I2C_ENABLE
345 /* Program GUSBCFG.OtgUtmifsSel to I2C */
346 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
348 /* Program GI2CCTL.I2CEn */
349 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN |
350 DWC2_GI2CCTL_I2CDEVADDR_MASK,
351 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
352 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN);
356 /* High speed PHY. */
359 * HS PHY parameters. These parameters are preserved during
360 * soft reset so only program the first time. Do a soft reset
361 * immediately after setting phyif.
363 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
364 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
366 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
367 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
368 usbcfg |= DWC2_GUSBCFG_DDRSEL;
370 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
372 } else { /* UTMI+ interface */
373 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
374 usbcfg |= DWC2_GUSBCFG_PHYIF;
378 writel(usbcfg, ®s->gusbcfg);
380 /* Reset after setting the PHY parameters */
381 dwc_otg_core_reset(regs);
384 usbcfg = readl(®s->gusbcfg);
385 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
386 #ifdef CONFIG_DWC2_ULPI_FS_LS
387 uint32_t hwcfg2 = readl(®s->ghwcfg2);
388 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
389 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
390 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
391 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
392 if (hval == 2 && fval == 1) {
393 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
394 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
397 writel(usbcfg, ®s->gusbcfg);
399 /* Program the GAHBCFG Register. */
400 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
401 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
403 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
404 while (brst_sz > 1) {
405 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
406 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
410 #ifdef CONFIG_DWC2_DMA_ENABLE
411 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
415 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
416 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
417 #ifdef CONFIG_DWC2_DMA_ENABLE
418 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
423 writel(ahbcfg, ®s->gahbcfg);
425 /* Program the GUSBCFG register for HNP/SRP. */
426 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
428 #ifdef CONFIG_DWC2_IC_USB_CAP
429 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
434 * Prepares a host channel for transferring packets to/from a specific
435 * endpoint. The HCCHARn register is set up with the characteristics specified
436 * in _hc. Host channel interrupts that may need to be serviced while this
437 * transfer is in progress are enabled.
439 * @param regs Programming view of DWC_otg controller
440 * @param hc Information needed to initialize the host channel
442 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
443 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
444 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
446 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num];
447 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
448 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
449 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
450 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
451 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
453 if (dev->speed == USB_SPEED_LOW)
454 hcchar |= DWC2_HCCHAR_LSPDDEV;
457 * Program the HCCHARn register with the endpoint characteristics
458 * for the current transfer.
460 writel(hcchar, &hc_regs->hcchar);
462 /* Program the HCSPLIT register, default to no SPLIT */
463 writel(0, &hc_regs->hcsplt);
466 static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
467 uint8_t hub_devnum, uint8_t hub_port)
471 hcsplt = DWC2_HCSPLT_SPLTENA;
472 hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
473 hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
475 /* Program the HCSPLIT register for SPLITs */
476 writel(hcsplt, &hc_regs->hcsplt);
480 * DWC2 to USB API interface
482 /* Direction: In ; Request: Status */
483 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
484 struct usb_device *dev, void *buffer,
485 int txlen, struct devrequest *cmd)
488 uint32_t port_status = 0;
489 uint32_t port_change = 0;
493 switch (cmd->requesttype & ~USB_DIR_IN) {
495 *(uint16_t *)buffer = cpu_to_le16(1);
498 case USB_RECIP_INTERFACE:
499 case USB_RECIP_ENDPOINT:
500 *(uint16_t *)buffer = cpu_to_le16(0);
504 *(uint32_t *)buffer = cpu_to_le32(0);
507 case USB_RECIP_OTHER | USB_TYPE_CLASS:
508 hprt0 = readl(®s->hprt0);
509 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
510 port_status |= USB_PORT_STAT_CONNECTION;
511 if (hprt0 & DWC2_HPRT0_PRTENA)
512 port_status |= USB_PORT_STAT_ENABLE;
513 if (hprt0 & DWC2_HPRT0_PRTSUSP)
514 port_status |= USB_PORT_STAT_SUSPEND;
515 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
516 port_status |= USB_PORT_STAT_OVERCURRENT;
517 if (hprt0 & DWC2_HPRT0_PRTRST)
518 port_status |= USB_PORT_STAT_RESET;
519 if (hprt0 & DWC2_HPRT0_PRTPWR)
520 port_status |= USB_PORT_STAT_POWER;
522 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
523 port_status |= USB_PORT_STAT_LOW_SPEED;
524 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
525 DWC2_HPRT0_PRTSPD_HIGH)
526 port_status |= USB_PORT_STAT_HIGH_SPEED;
528 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
529 port_change |= USB_PORT_STAT_C_ENABLE;
530 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
531 port_change |= USB_PORT_STAT_C_CONNECTION;
532 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
533 port_change |= USB_PORT_STAT_C_OVERCURRENT;
535 *(uint32_t *)buffer = cpu_to_le32(port_status |
536 (port_change << 16));
540 puts("unsupported root hub command\n");
541 stat = USB_ST_STALLED;
544 dev->act_len = min(len, txlen);
550 /* Direction: In ; Request: Descriptor */
551 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
552 void *buffer, int txlen,
553 struct devrequest *cmd)
555 unsigned char data[32];
559 uint16_t wValue = cpu_to_le16(cmd->value);
560 uint16_t wLength = cpu_to_le16(cmd->length);
562 switch (cmd->requesttype & ~USB_DIR_IN) {
564 switch (wValue & 0xff00) {
565 case 0x0100: /* device descriptor */
566 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
567 memcpy(buffer, root_hub_dev_des, len);
569 case 0x0200: /* configuration descriptor */
570 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
571 memcpy(buffer, root_hub_config_des, len);
573 case 0x0300: /* string descriptors */
574 switch (wValue & 0xff) {
576 len = min3(txlen, (int)sizeof(root_hub_str_index0),
578 memcpy(buffer, root_hub_str_index0, len);
581 len = min3(txlen, (int)sizeof(root_hub_str_index1),
583 memcpy(buffer, root_hub_str_index1, len);
588 stat = USB_ST_STALLED;
593 /* Root port config, set 1 port and nothing else. */
596 data[0] = 9; /* min length; */
598 data[2] = dsc & RH_A_NDP;
604 else if (dsc & RH_A_OCPM)
607 /* corresponds to data[4-7] */
608 data[5] = (dsc & RH_A_POTPGT) >> 24;
609 data[7] = dsc & RH_B_DR;
614 data[8] = (dsc & RH_B_DR) >> 8;
619 len = min3(txlen, (int)data[0], (int)wLength);
620 memcpy(buffer, data, len);
623 puts("unsupported root hub command\n");
624 stat = USB_ST_STALLED;
627 dev->act_len = min(len, txlen);
633 /* Direction: In ; Request: Configuration */
634 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
635 void *buffer, int txlen,
636 struct devrequest *cmd)
641 switch (cmd->requesttype & ~USB_DIR_IN) {
643 *(uint8_t *)buffer = 0x01;
647 puts("unsupported root hub command\n");
648 stat = USB_ST_STALLED;
651 dev->act_len = min(len, txlen);
658 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
659 struct usb_device *dev, void *buffer,
660 int txlen, struct devrequest *cmd)
662 switch (cmd->request) {
663 case USB_REQ_GET_STATUS:
664 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
666 case USB_REQ_GET_DESCRIPTOR:
667 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
669 case USB_REQ_GET_CONFIGURATION:
670 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
673 puts("unsupported root hub command\n");
674 return USB_ST_STALLED;
679 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
680 struct usb_device *dev,
681 void *buffer, int txlen,
682 struct devrequest *cmd)
684 struct dwc2_core_regs *regs = priv->regs;
687 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
688 uint16_t wValue = cpu_to_le16(cmd->value);
690 switch (bmrtype_breq & ~USB_DIR_IN) {
691 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
692 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
695 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
697 case USB_PORT_FEAT_C_CONNECTION:
698 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET);
703 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
705 case USB_PORT_FEAT_SUSPEND:
708 case USB_PORT_FEAT_RESET:
709 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
710 DWC2_HPRT0_PRTCONNDET |
711 DWC2_HPRT0_PRTENCHNG |
712 DWC2_HPRT0_PRTOVRCURRCHNG,
715 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST);
718 case USB_PORT_FEAT_POWER:
719 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
720 DWC2_HPRT0_PRTCONNDET |
721 DWC2_HPRT0_PRTENCHNG |
722 DWC2_HPRT0_PRTOVRCURRCHNG,
726 case USB_PORT_FEAT_ENABLE:
730 case (USB_REQ_SET_ADDRESS << 8):
731 priv->root_hub_devnum = wValue;
733 case (USB_REQ_SET_CONFIGURATION << 8):
736 puts("unsupported root hub command\n");
737 stat = USB_ST_STALLED;
740 len = min(len, txlen);
748 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
749 unsigned long pipe, void *buffer, int txlen,
750 struct devrequest *cmd)
754 if (usb_pipeint(pipe)) {
755 puts("Root-Hub submit IRQ: NOT implemented\n");
759 if (cmd->requesttype & USB_DIR_IN)
760 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
762 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
769 int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
772 uint32_t hcint, hctsiz;
774 ret = wait_for_bit(__func__, &hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
779 hcint = readl(&hc_regs->hcint);
780 hctsiz = readl(&hc_regs->hctsiz);
781 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
782 DWC2_HCTSIZ_XFERSIZE_OFFSET;
783 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
785 debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
788 if (hcint & DWC2_HCINT_XFERCOMP)
791 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
794 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
798 static int dwc2_eptype[] = {
799 DWC2_HCCHAR_EPTYPE_ISOC,
800 DWC2_HCCHAR_EPTYPE_INTR,
801 DWC2_HCCHAR_EPTYPE_CONTROL,
802 DWC2_HCCHAR_EPTYPE_BULK,
805 static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
806 u8 *pid, int in, void *buffer, int num_packets,
807 int xfer_len, int *actual_len, int odd_frame)
812 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
813 *pid, xfer_len, num_packets);
815 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
816 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
817 (*pid << DWC2_HCTSIZ_PID_OFFSET),
820 if (!in && xfer_len) {
821 memcpy(aligned_buffer, buffer, xfer_len);
823 flush_dcache_range((unsigned long)aligned_buffer,
824 (unsigned long)aligned_buffer +
825 roundup(xfer_len, ARCH_DMA_MINALIGN));
828 writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
830 /* Clear old interrupt conditions for this host channel. */
831 writel(0x3fff, &hc_regs->hcint);
833 /* Set host channel enable after all other setup is complete. */
834 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
835 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
837 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
838 (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
841 ret = wait_for_chhltd(hc_regs, &sub, pid);
848 invalidate_dcache_range((unsigned long)aligned_buffer,
849 (unsigned long)aligned_buffer +
850 roundup(xfer_len, ARCH_DMA_MINALIGN));
852 memcpy(buffer, aligned_buffer, xfer_len);
854 *actual_len = xfer_len;
859 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
860 unsigned long pipe, u8 *pid, int in, void *buffer, int len)
862 struct dwc2_core_regs *regs = priv->regs;
863 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
864 struct dwc2_host_regs *host_regs = ®s->host_regs;
865 int devnum = usb_pipedevice(pipe);
866 int ep = usb_pipeendpoint(pipe);
867 int max = usb_maxpacket(dev, pipe);
868 int eptype = dwc2_eptype[usb_pipetype(pipe)];
872 int complete_split = 0;
874 uint32_t num_packets;
875 int stop_transfer = 0;
876 uint32_t max_xfer_len;
877 int ssplit_frame_num = 0;
879 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
882 max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
883 if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
884 max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
885 if (max_xfer_len > DWC2_DATA_BUF_SIZE)
886 max_xfer_len = DWC2_DATA_BUF_SIZE;
888 /* Make sure that max_xfer_len is a multiple of max packet size. */
889 num_packets = max_xfer_len / max;
890 max_xfer_len = num_packets * max;
892 /* Initialize channel */
893 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
896 /* Check if the target is a FS/LS device behind a HS hub */
897 if (dev->speed != USB_SPEED_HIGH) {
900 uint32_t hprt0 = readl(®s->hprt0);
901 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
902 DWC2_HPRT0_PRTSPD_HIGH) {
903 usb_find_usb2_hub_address_port(dev, &hub_addr,
905 dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
917 xfer_len = len - done;
919 if (xfer_len > max_xfer_len)
920 xfer_len = max_xfer_len;
921 else if (xfer_len > max)
922 num_packets = (xfer_len + max - 1) / max;
927 setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
929 clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
931 if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
932 int uframe_num = readl(&host_regs->hfnum);
933 if (!(uframe_num & 0x1))
937 ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
938 in, (char *)buffer + done, num_packets,
939 xfer_len, &actual_len, odd_frame);
941 hcint = readl(&hc_regs->hcint);
942 if (complete_split) {
944 if (hcint & DWC2_HCINT_NYET) {
946 int frame_num = DWC2_HFNUM_MAX_FRNUM &
947 readl(&host_regs->hfnum);
948 if (((frame_num - ssplit_frame_num) &
949 DWC2_HFNUM_MAX_FRNUM) > 4)
953 } else if (do_split) {
954 if (hcint & DWC2_HCINT_ACK) {
955 ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
956 readl(&host_regs->hfnum);
965 if (actual_len < xfer_len)
970 /* Transactions are done when when either all data is transferred or
971 * there is a short transfer. In case of a SPLIT make sure the CSPLIT
974 } while (((done < len) && !stop_transfer) || complete_split);
976 writel(0, &hc_regs->hcintmsk);
977 writel(0xFFFFFFFF, &hc_regs->hcint);
985 /* U-Boot USB transmission interface */
986 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
987 unsigned long pipe, void *buffer, int len)
989 int devnum = usb_pipedevice(pipe);
990 int ep = usb_pipeendpoint(pipe);
993 if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
998 if (usb_pipein(pipe))
999 pid = &priv->in_data_toggle[devnum][ep];
1001 pid = &priv->out_data_toggle[devnum][ep];
1003 return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
1006 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
1007 unsigned long pipe, void *buffer, int len,
1008 struct devrequest *setup)
1010 int devnum = usb_pipedevice(pipe);
1013 /* For CONTROL endpoint pid should start with DATA1 */
1014 int status_direction;
1016 if (devnum == priv->root_hub_devnum) {
1018 dev->speed = USB_SPEED_HIGH;
1019 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
1024 pid = DWC2_HC_PID_SETUP;
1026 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
1027 } while (ret == -EAGAIN);
1034 pid = DWC2_HC_PID_DATA1;
1036 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
1038 act_len += dev->act_len;
1039 buffer += dev->act_len;
1040 len -= dev->act_len;
1041 } while (ret == -EAGAIN);
1044 status_direction = usb_pipeout(pipe);
1046 /* No-data CONTROL always ends with an IN transaction */
1047 status_direction = 1;
1051 pid = DWC2_HC_PID_DATA1;
1053 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
1054 priv->status_buffer, 0);
1055 } while (ret == -EAGAIN);
1059 dev->act_len = act_len;
1064 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
1065 unsigned long pipe, void *buffer, int len, int interval)
1067 unsigned long timeout;
1070 /* FIXME: what is interval? */
1072 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
1074 if (get_timer(0) > timeout) {
1075 printf("Timeout poll on interrupt endpoint\n");
1078 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
1084 static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
1086 struct dwc2_core_regs *regs = priv->regs;
1090 snpsid = readl(®s->gsnpsid);
1091 printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
1093 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
1094 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
1095 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
1099 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
1105 dwc_otg_core_init(priv);
1106 dwc_otg_core_host_init(dev, regs);
1108 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1109 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1110 DWC2_HPRT0_PRTOVRCURRCHNG,
1113 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
1114 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
1117 for (i = 0; i < MAX_DEVICE; i++) {
1118 for (j = 0; j < MAX_ENDPOINT; j++) {
1119 priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1120 priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
1125 * Add a 1 second delay here. This gives the host controller
1126 * a bit time before the comminucation with the USB devices
1127 * is started (the bus is scanned) and fixes the USB detection
1128 * problems with some problematic USB keys.
1130 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
1136 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
1138 /* Put everything in reset. */
1139 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
1140 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
1141 DWC2_HPRT0_PRTOVRCURRCHNG,
1145 #ifndef CONFIG_DM_USB
1146 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1147 int len, struct devrequest *setup)
1149 return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
1152 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1155 return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1158 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1159 int len, int interval)
1161 return _submit_int_msg(&local, dev, pipe, buffer, len, interval);
1164 /* U-Boot USB control interface */
1165 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1167 struct dwc2_priv *priv = &local;
1169 memset(priv, '\0', sizeof(*priv));
1170 priv->root_hub_devnum = 0;
1171 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1172 priv->aligned_buffer = aligned_buffer_addr;
1173 priv->status_buffer = status_buffer_addr;
1175 /* board-dependant init */
1176 if (board_usb_init(index, USB_INIT_HOST))
1179 return dwc2_init_common(NULL, priv);
1182 int usb_lowlevel_stop(int index)
1184 dwc2_uninit_common(local.regs);
1190 #ifdef CONFIG_DM_USB
1191 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1192 unsigned long pipe, void *buffer, int length,
1193 struct devrequest *setup)
1195 struct dwc2_priv *priv = dev_get_priv(dev);
1197 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1198 dev->name, udev, udev->dev->name, udev->portnr);
1200 return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1203 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1204 unsigned long pipe, void *buffer, int length)
1206 struct dwc2_priv *priv = dev_get_priv(dev);
1208 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1210 return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1213 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1214 unsigned long pipe, void *buffer, int length,
1217 struct dwc2_priv *priv = dev_get_priv(dev);
1219 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1221 return _submit_int_msg(priv, udev, pipe, buffer, length, interval);
1224 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1226 struct dwc2_priv *priv = dev_get_priv(dev);
1230 addr = dev_get_addr(dev);
1231 if (addr == FDT_ADDR_T_NONE)
1233 priv->regs = (struct dwc2_core_regs *)addr;
1235 prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
1236 "disable-over-current", NULL);
1238 priv->oc_disable = true;
1243 static int dwc2_usb_probe(struct udevice *dev)
1245 struct dwc2_priv *priv = dev_get_priv(dev);
1246 struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
1248 bus_priv->desc_before_addr = true;
1250 return dwc2_init_common(dev, priv);
1253 static int dwc2_usb_remove(struct udevice *dev)
1255 struct dwc2_priv *priv = dev_get_priv(dev);
1257 dwc2_uninit_common(priv->regs);
1262 struct dm_usb_ops dwc2_usb_ops = {
1263 .control = dwc2_submit_control_msg,
1264 .bulk = dwc2_submit_bulk_msg,
1265 .interrupt = dwc2_submit_int_msg,
1268 static const struct udevice_id dwc2_usb_ids[] = {
1269 { .compatible = "brcm,bcm2835-usb" },
1270 { .compatible = "snps,dwc2" },
1274 U_BOOT_DRIVER(usb_dwc2) = {
1277 .of_match = dwc2_usb_ids,
1278 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1279 .probe = dwc2_usb_probe,
1280 .remove = dwc2_usb_remove,
1281 .ops = &dwc2_usb_ops,
1282 .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1283 .flags = DM_FLAG_ALLOC_PRIV_DMA,