drivers/usb/host/dwc2.c

   1 /*
   2  * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
   3  * Copyright (C) 2014 Marek Vasut <marex@denx.de>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <errno.h>
  10 #include <usb.h>
  11 #include <malloc.h>
  12 #include <phys2bus.h>
  13 #include <usbroothubdes.h>
  14 #include <asm/io.h>
  15
  16 #include "dwc2.h"
  17
  18 /* Use only HC channel 0. */
  19 #define DWC2_HC_CHANNEL                 0
  20
  21 #define DWC2_STATUS_BUF_SIZE            64
  22 #define DWC2_DATA_BUF_SIZE              (64 * 1024)
  23
  24 #define MAX_DEVICE                      16
  25 #define MAX_ENDPOINT                    16
  26
  27 struct dwc2_priv {
  28         uint8_t *aligned_buffer;
  29         uint8_t *status_buffer;
  30         int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  31         struct dwc2_core_regs *regs;
  32         int root_hub_devnum;
  33 };
  34
  35 /* We need doubleword-aligned buffers for DMA transfers */
  36 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE, 8);
  37 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE, 8);
  38
  39 static struct dwc2_priv local;
  40
  41 /*
  42  * DWC2 IP interface
  43  */
  44 static int wait_for_bit(void *reg, const uint32_t mask, bool set)
  45 {
  46         unsigned int timeout = 1000000;
  47         uint32_t val;
  48
  49         while (--timeout) {
  50                 val = readl(reg);
  51                 if (!set)
  52                         val = ~val;
  53
  54                 if ((val & mask) == mask)
  55                         return 0;
  56
  57                 udelay(1);
  58         }
  59
  60         debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
  61               __func__, reg, mask, set);
  62
  63         return -ETIMEDOUT;
  64 }
  65
  66 /*
  67  * Initializes the FSLSPClkSel field of the HCFG register
  68  * depending on the PHY type.
  69  */
  70 static void init_fslspclksel(struct dwc2_core_regs *regs)
  71 {
  72         uint32_t phyclk;
  73
  74 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
  75         phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
  76 #else
  77         /* High speed PHY running at full speed or high speed */
  78         phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
  79 #endif
  80
  81 #ifdef CONFIG_DWC2_ULPI_FS_LS
  82         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
  83         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
  84                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
  85         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
  86                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
  87
  88         if (hval == 2 && fval == 1)
  89                 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ;  /* Full speed PHY */
  90 #endif
  91
  92         clrsetbits_le32(&regs->host_regs.hcfg,
  93                         DWC2_HCFG_FSLSPCLKSEL_MASK,
  94                         phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
  95 }
  96
  97 /*
  98  * Flush a Tx FIFO.
  99  *
 100  * @param regs Programming view of DWC_otg controller.
 101  * @param num Tx FIFO to flush.
 102  */
 103 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
 104 {
 105         int ret;
 106
 107         writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
 108                &regs->grstctl);
 109         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH, 0);
 110         if (ret)
 111                 printf("%s: Timeout!\n", __func__);
 112
 113         /* Wait for 3 PHY Clocks */
 114         udelay(1);
 115 }
 116
 117 /*
 118  * Flush Rx FIFO.
 119  *
 120  * @param regs Programming view of DWC_otg controller.
 121  */
 122 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
 123 {
 124         int ret;
 125
 126         writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
 127         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH, 0);
 128         if (ret)
 129                 printf("%s: Timeout!\n", __func__);
 130
 131         /* Wait for 3 PHY Clocks */
 132         udelay(1);
 133 }
 134
 135 /*
 136  * Do core a soft reset of the core.  Be careful with this because it
 137  * resets all the internal state machines of the core.
 138  */
 139 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
 140 {
 141         int ret;
 142
 143         /* Wait for AHB master IDLE state. */
 144         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE, 1);
 145         if (ret)
 146                 printf("%s: Timeout!\n", __func__);
 147
 148         /* Core Soft Reset */
 149         writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
 150         ret = wait_for_bit(&regs->grstctl, DWC2_GRSTCTL_CSFTRST, 0);
 151         if (ret)
 152                 printf("%s: Timeout!\n", __func__);
 153
 154         /*
 155          * Wait for core to come out of reset.
 156          * NOTE: This long sleep is _very_ important, otherwise the core will
 157          *       not stay in host mode after a connector ID change!
 158          */
 159         mdelay(100);
 160 }
 161
 162 /*
 163  * This function initializes the DWC_otg controller registers for
 164  * host mode.
 165  *
 166  * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
 167  * request queues. Host channels are reset to ensure that they are ready for
 168  * performing transfers.
 169  *
 170  * @param regs Programming view of DWC_otg controller
 171  *
 172  */
 173 static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
 174 {
 175         uint32_t nptxfifosize = 0;
 176         uint32_t ptxfifosize = 0;
 177         uint32_t hprt0 = 0;
 178         int i, ret, num_channels;
 179
 180         /* Restart the Phy Clock */
 181         writel(0, &regs->pcgcctl);
 182
 183         /* Initialize Host Configuration Register */
 184         init_fslspclksel(regs);
 185 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
 186         setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
 187 #endif
 188
 189         /* Configure data FIFO sizes */
 190 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
 191         if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
 192                 /* Rx FIFO */
 193                 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
 194
 195                 /* Non-periodic Tx FIFO */
 196                 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
 197                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 198                 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
 199                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 200                 writel(nptxfifosize, &regs->gnptxfsiz);
 201
 202                 /* Periodic Tx FIFO */
 203                 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
 204                                 DWC2_FIFOSIZE_DEPTH_OFFSET;
 205                 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
 206                                 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
 207                                 DWC2_FIFOSIZE_STARTADDR_OFFSET;
 208                 writel(ptxfifosize, &regs->hptxfsiz);
 209         }
 210 #endif
 211
 212         /* Clear Host Set HNP Enable in the OTG Control Register */
 213         clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
 214
 215         /* Make sure the FIFOs are flushed. */
 216         dwc_otg_flush_tx_fifo(regs, 0x10);      /* All Tx FIFOs */
 217         dwc_otg_flush_rx_fifo(regs);
 218
 219         /* Flush out any leftover queued requests. */
 220         num_channels = readl(&regs->ghwcfg2);
 221         num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
 222         num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
 223         num_channels += 1;
 224
 225         for (i = 0; i < num_channels; i++)
 226                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 227                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
 228                                 DWC2_HCCHAR_CHDIS);
 229
 230         /* Halt all channels to put them into a known state. */
 231         for (i = 0; i < num_channels; i++) {
 232                 clrsetbits_le32(&regs->hc_regs[i].hcchar,
 233                                 DWC2_HCCHAR_EPDIR,
 234                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
 235                 ret = wait_for_bit(&regs->hc_regs[i].hcchar,
 236                                    DWC2_HCCHAR_CHEN, 0);
 237                 if (ret)
 238                         printf("%s: Timeout!\n", __func__);
 239         }
 240
 241         /* Turn on the vbus power. */
 242         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
 243                 hprt0 = readl(&regs->hprt0);
 244                 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
 245                 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
 246                 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
 247                         hprt0 |= DWC2_HPRT0_PRTPWR;
 248                         writel(hprt0, &regs->hprt0);
 249                 }
 250         }
 251 }
 252
 253 /*
 254  * This function initializes the DWC_otg controller registers and
 255  * prepares the core for device mode or host mode operation.
 256  *
 257  * @param regs Programming view of the DWC_otg controller
 258  */
 259 static void dwc_otg_core_init(struct dwc2_core_regs *regs)
 260 {
 261         uint32_t ahbcfg = 0;
 262         uint32_t usbcfg = 0;
 263         uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
 264
 265         /* Common Initialization */
 266         usbcfg = readl(&regs->gusbcfg);
 267
 268         /* Program the ULPI External VBUS bit if needed */
 269 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
 270         usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 271 #else
 272         usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
 273 #endif
 274
 275         /* Set external TS Dline pulsing */
 276 #ifdef CONFIG_DWC2_TS_DLINE
 277         usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 278 #else
 279         usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
 280 #endif
 281         writel(usbcfg, &regs->gusbcfg);
 282
 283         /* Reset the Controller */
 284         dwc_otg_core_reset(regs);
 285
 286         /*
 287          * This programming sequence needs to happen in FS mode before
 288          * any other programming occurs
 289          */
 290 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
 291         (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
 292         /* If FS mode with FS PHY */
 293         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
 294
 295         /* Reset after a PHY select */
 296         dwc_otg_core_reset(regs);
 297
 298         /*
 299          * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
 300          * Also do this on HNP Dev/Host mode switches (done in dev_init
 301          * and host_init).
 302          */
 303         if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
 304                 init_fslspclksel(regs);
 305
 306 #ifdef CONFIG_DWC2_I2C_ENABLE
 307         /* Program GUSBCFG.OtgUtmifsSel to I2C */
 308         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
 309
 310         /* Program GI2CCTL.I2CEn */
 311         clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
 312                         DWC2_GI2CCTL_I2CDEVADDR_MASK,
 313                         1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
 314         setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
 315 #endif
 316
 317 #else
 318         /* High speed PHY. */
 319
 320         /*
 321          * HS PHY parameters. These parameters are preserved during
 322          * soft reset so only program the first time. Do a soft reset
 323          * immediately after setting phyif.
 324          */
 325         usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
 326         usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
 327
 328         if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) {      /* ULPI interface */
 329 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
 330                 usbcfg |= DWC2_GUSBCFG_DDRSEL;
 331 #else
 332                 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
 333 #endif
 334         } else {        /* UTMI+ interface */
 335 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
 336                 usbcfg |= DWC2_GUSBCFG_PHYIF;
 337 #endif
 338         }
 339
 340         writel(usbcfg, &regs->gusbcfg);
 341
 342         /* Reset after setting the PHY parameters */
 343         dwc_otg_core_reset(regs);
 344 #endif
 345
 346         usbcfg = readl(&regs->gusbcfg);
 347         usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
 348 #ifdef CONFIG_DWC2_ULPI_FS_LS
 349         uint32_t hwcfg2 = readl(&regs->ghwcfg2);
 350         uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
 351                         DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
 352         uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
 353                         DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
 354         if (hval == 2 && fval == 1) {
 355                 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
 356                 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
 357         }
 358 #endif
 359         writel(usbcfg, &regs->gusbcfg);
 360
 361         /* Program the GAHBCFG Register. */
 362         switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
 363         case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
 364                 break;
 365         case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
 366                 while (brst_sz > 1) {
 367                         ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
 368                         ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
 369                         brst_sz >>= 1;
 370                 }
 371
 372 #ifdef CONFIG_DWC2_DMA_ENABLE
 373                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 374 #endif
 375                 break;
 376
 377         case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
 378                 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
 379 #ifdef CONFIG_DWC2_DMA_ENABLE
 380                 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
 381 #endif
 382                 break;
 383         }
 384
 385         writel(ahbcfg, &regs->gahbcfg);
 386
 387         /* Program the GUSBCFG register for HNP/SRP. */
 388         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
 389
 390 #ifdef CONFIG_DWC2_IC_USB_CAP
 391         setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
 392 #endif
 393 }
 394
 395 /*
 396  * Prepares a host channel for transferring packets to/from a specific
 397  * endpoint. The HCCHARn register is set up with the characteristics specified
 398  * in _hc. Host channel interrupts that may need to be serviced while this
 399  * transfer is in progress are enabled.
 400  *
 401  * @param regs Programming view of DWC_otg controller
 402  * @param hc Information needed to initialize the host channel
 403  */
 404 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
 405                 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
 406                 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
 407 {
 408         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
 409         uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
 410                           (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
 411                           (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
 412                           (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
 413                           (max_packet << DWC2_HCCHAR_MPS_OFFSET);
 414
 415         if (dev->speed == USB_SPEED_LOW)
 416                 hcchar |= DWC2_HCCHAR_LSPDDEV;
 417
 418         /* Clear old interrupt conditions for this host channel. */
 419         writel(0x3fff, &hc_regs->hcint);
 420
 421         /*
 422          * Program the HCCHARn register with the endpoint characteristics
 423          * for the current transfer.
 424          */
 425         writel(hcchar, &hc_regs->hcchar);
 426
 427         /* Program the HCSPLIT register for SPLITs */
 428         writel(0, &hc_regs->hcsplt);
 429 }
 430
 431 /*
 432  * DWC2 to USB API interface
 433  */
 434 /* Direction: In ; Request: Status */
 435 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
 436                                            struct usb_device *dev, void *buffer,
 437                                            int txlen, struct devrequest *cmd)
 438 {
 439         uint32_t hprt0 = 0;
 440         uint32_t port_status = 0;
 441         uint32_t port_change = 0;
 442         int len = 0;
 443         int stat = 0;
 444
 445         switch (cmd->requesttype & ~USB_DIR_IN) {
 446         case 0:
 447                 *(uint16_t *)buffer = cpu_to_le16(1);
 448                 len = 2;
 449                 break;
 450         case USB_RECIP_INTERFACE:
 451         case USB_RECIP_ENDPOINT:
 452                 *(uint16_t *)buffer = cpu_to_le16(0);
 453                 len = 2;
 454                 break;
 455         case USB_TYPE_CLASS:
 456                 *(uint32_t *)buffer = cpu_to_le32(0);
 457                 len = 4;
 458                 break;
 459         case USB_RECIP_OTHER | USB_TYPE_CLASS:
 460                 hprt0 = readl(&regs->hprt0);
 461                 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
 462                         port_status |= USB_PORT_STAT_CONNECTION;
 463                 if (hprt0 & DWC2_HPRT0_PRTENA)
 464                         port_status |= USB_PORT_STAT_ENABLE;
 465                 if (hprt0 & DWC2_HPRT0_PRTSUSP)
 466                         port_status |= USB_PORT_STAT_SUSPEND;
 467                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
 468                         port_status |= USB_PORT_STAT_OVERCURRENT;
 469                 if (hprt0 & DWC2_HPRT0_PRTRST)
 470                         port_status |= USB_PORT_STAT_RESET;
 471                 if (hprt0 & DWC2_HPRT0_PRTPWR)
 472                         port_status |= USB_PORT_STAT_POWER;
 473
 474                 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
 475                         port_status |= USB_PORT_STAT_LOW_SPEED;
 476                 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
 477                          DWC2_HPRT0_PRTSPD_HIGH)
 478                         port_status |= USB_PORT_STAT_HIGH_SPEED;
 479
 480                 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
 481                         port_change |= USB_PORT_STAT_C_ENABLE;
 482                 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
 483                         port_change |= USB_PORT_STAT_C_CONNECTION;
 484                 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
 485                         port_change |= USB_PORT_STAT_C_OVERCURRENT;
 486
 487                 *(uint32_t *)buffer = cpu_to_le32(port_status |
 488                                         (port_change << 16));
 489                 len = 4;
 490                 break;
 491         default:
 492                 puts("unsupported root hub command\n");
 493                 stat = USB_ST_STALLED;
 494         }
 495
 496         dev->act_len = min(len, txlen);
 497         dev->status = stat;
 498
 499         return stat;
 500 }
 501
 502 /* Direction: In ; Request: Descriptor */
 503 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
 504                                                void *buffer, int txlen,
 505                                                struct devrequest *cmd)
 506 {
 507         unsigned char data[32];
 508         uint32_t dsc;
 509         int len = 0;
 510         int stat = 0;
 511         uint16_t wValue = cpu_to_le16(cmd->value);
 512         uint16_t wLength = cpu_to_le16(cmd->length);
 513
 514         switch (cmd->requesttype & ~USB_DIR_IN) {
 515         case 0:
 516                 switch (wValue & 0xff00) {
 517                 case 0x0100:    /* device descriptor */
 518                         len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
 519                         memcpy(buffer, root_hub_dev_des, len);
 520                         break;
 521                 case 0x0200:    /* configuration descriptor */
 522                         len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
 523                         memcpy(buffer, root_hub_config_des, len);
 524                         break;
 525                 case 0x0300:    /* string descriptors */
 526                         switch (wValue & 0xff) {
 527                         case 0x00:
 528                                 len = min3(txlen, (int)sizeof(root_hub_str_index0),
 529                                            (int)wLength);
 530                                 memcpy(buffer, root_hub_str_index0, len);
 531                                 break;
 532                         case 0x01:
 533                                 len = min3(txlen, (int)sizeof(root_hub_str_index1),
 534                                            (int)wLength);
 535                                 memcpy(buffer, root_hub_str_index1, len);
 536                                 break;
 537                         }
 538                         break;
 539                 default:
 540                         stat = USB_ST_STALLED;
 541                 }
 542                 break;
 543
 544         case USB_TYPE_CLASS:
 545                 /* Root port config, set 1 port and nothing else. */
 546                 dsc = 0x00000001;
 547
 548                 data[0] = 9;            /* min length; */
 549                 data[1] = 0x29;
 550                 data[2] = dsc & RH_A_NDP;
 551                 data[3] = 0;
 552                 if (dsc & RH_A_PSM)
 553                         data[3] |= 0x1;
 554                 if (dsc & RH_A_NOCP)
 555                         data[3] |= 0x10;
 556                 else if (dsc & RH_A_OCPM)
 557                         data[3] |= 0x8;
 558
 559                 /* corresponds to data[4-7] */
 560                 data[5] = (dsc & RH_A_POTPGT) >> 24;
 561                 data[7] = dsc & RH_B_DR;
 562                 if (data[2] < 7) {
 563                         data[8] = 0xff;
 564                 } else {
 565                         data[0] += 2;
 566                         data[8] = (dsc & RH_B_DR) >> 8;
 567                         data[9] = 0xff;
 568                         data[10] = data[9];
 569                 }
 570
 571                 len = min3(txlen, (int)data[0], (int)wLength);
 572                 memcpy(buffer, data, len);
 573                 break;
 574         default:
 575                 puts("unsupported root hub command\n");
 576                 stat = USB_ST_STALLED;
 577         }
 578
 579         dev->act_len = min(len, txlen);
 580         dev->status = stat;
 581
 582         return stat;
 583 }
 584
 585 /* Direction: In ; Request: Configuration */
 586 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
 587                                                   void *buffer, int txlen,
 588                                                   struct devrequest *cmd)
 589 {
 590         int len = 0;
 591         int stat = 0;
 592
 593         switch (cmd->requesttype & ~USB_DIR_IN) {
 594         case 0:
 595                 *(uint8_t *)buffer = 0x01;
 596                 len = 1;
 597                 break;
 598         default:
 599                 puts("unsupported root hub command\n");
 600                 stat = USB_ST_STALLED;
 601         }
 602
 603         dev->act_len = min(len, txlen);
 604         dev->status = stat;
 605
 606         return stat;
 607 }
 608
 609 /* Direction: In */
 610 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
 611                                     struct usb_device *dev, void *buffer,
 612                                     int txlen, struct devrequest *cmd)
 613 {
 614         switch (cmd->request) {
 615         case USB_REQ_GET_STATUS:
 616                 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
 617                                                        txlen, cmd);
 618         case USB_REQ_GET_DESCRIPTOR:
 619                 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
 620                                                            txlen, cmd);
 621         case USB_REQ_GET_CONFIGURATION:
 622                 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
 623                                                               txlen, cmd);
 624         default:
 625                 puts("unsupported root hub command\n");
 626                 return USB_ST_STALLED;
 627         }
 628 }
 629
 630 /* Direction: Out */
 631 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
 632                                      struct usb_device *dev,
 633                                      void *buffer, int txlen,
 634                                      struct devrequest *cmd)
 635 {
 636         struct dwc2_core_regs *regs = priv->regs;
 637         int len = 0;
 638         int stat = 0;
 639         uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
 640         uint16_t wValue = cpu_to_le16(cmd->value);
 641
 642         switch (bmrtype_breq & ~USB_DIR_IN) {
 643         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
 644         case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
 645                 break;
 646
 647         case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 648                 switch (wValue) {
 649                 case USB_PORT_FEAT_C_CONNECTION:
 650                         setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
 651                         break;
 652                 }
 653                 break;
 654
 655         case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
 656                 switch (wValue) {
 657                 case USB_PORT_FEAT_SUSPEND:
 658                         break;
 659
 660                 case USB_PORT_FEAT_RESET:
 661                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 662                                         DWC2_HPRT0_PRTCONNDET |
 663                                         DWC2_HPRT0_PRTENCHNG |
 664                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 665                                         DWC2_HPRT0_PRTRST);
 666                         mdelay(50);
 667                         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
 668                         break;
 669
 670                 case USB_PORT_FEAT_POWER:
 671                         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 672                                         DWC2_HPRT0_PRTCONNDET |
 673                                         DWC2_HPRT0_PRTENCHNG |
 674                                         DWC2_HPRT0_PRTOVRCURRCHNG,
 675                                         DWC2_HPRT0_PRTRST);
 676                         break;
 677
 678                 case USB_PORT_FEAT_ENABLE:
 679                         break;
 680                 }
 681                 break;
 682         case (USB_REQ_SET_ADDRESS << 8):
 683                 priv->root_hub_devnum = wValue;
 684                 break;
 685         case (USB_REQ_SET_CONFIGURATION << 8):
 686                 break;
 687         default:
 688                 puts("unsupported root hub command\n");
 689                 stat = USB_ST_STALLED;
 690         }
 691
 692         len = min(len, txlen);
 693
 694         dev->act_len = len;
 695         dev->status = stat;
 696
 697         return stat;
 698 }
 699
 700 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
 701                                  unsigned long pipe, void *buffer, int txlen,
 702                                  struct devrequest *cmd)
 703 {
 704         int stat = 0;
 705
 706         if (usb_pipeint(pipe)) {
 707                 puts("Root-Hub submit IRQ: NOT implemented\n");
 708                 return 0;
 709         }
 710
 711         if (cmd->requesttype & USB_DIR_IN)
 712                 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
 713         else
 714                 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
 715
 716         mdelay(1);
 717
 718         return stat;
 719 }
 720
 721 int wait_for_chhltd(struct dwc2_core_regs *regs, uint32_t *sub, int *toggle,
 722                     bool ignore_ack)
 723 {
 724         uint32_t hcint_comp_hlt_ack = DWC2_HCINT_XFERCOMP | DWC2_HCINT_CHHLTD;
 725         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
 726         int ret;
 727         uint32_t hcint, hctsiz;
 728
 729         ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true);
 730         if (ret)
 731                 return ret;
 732
 733         hcint = readl(&hc_regs->hcint);
 734         if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
 735                 return -EAGAIN;
 736         if (ignore_ack)
 737                 hcint &= ~DWC2_HCINT_ACK;
 738         else
 739                 hcint_comp_hlt_ack |= DWC2_HCINT_ACK;
 740         if (hcint != hcint_comp_hlt_ack) {
 741                 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
 742                 return -EINVAL;
 743         }
 744
 745         hctsiz = readl(&hc_regs->hctsiz);
 746         *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
 747                 DWC2_HCTSIZ_XFERSIZE_OFFSET;
 748         *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
 749
 750         debug("%s: sub=%u toggle=%d\n", __func__, *sub, *toggle);
 751
 752         return 0;
 753 }
 754
 755 static int dwc2_eptype[] = {
 756         DWC2_HCCHAR_EPTYPE_ISOC,
 757         DWC2_HCCHAR_EPTYPE_INTR,
 758         DWC2_HCCHAR_EPTYPE_CONTROL,
 759         DWC2_HCCHAR_EPTYPE_BULK,
 760 };
 761
 762 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
 763               unsigned long pipe, int *pid, int in, void *buffer, int len,
 764               bool ignore_ack)
 765 {
 766         struct dwc2_core_regs *regs = priv->regs;
 767         struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
 768         int devnum = usb_pipedevice(pipe);
 769         int ep = usb_pipeendpoint(pipe);
 770         int max = usb_maxpacket(dev, pipe);
 771         int eptype = dwc2_eptype[usb_pipetype(pipe)];
 772         int done = 0;
 773         int ret = 0;
 774         uint32_t sub;
 775         uint32_t xfer_len;
 776         uint32_t num_packets;
 777         int stop_transfer = 0;
 778
 779         debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
 780               in, len);
 781
 782         do {
 783                 /* Initialize channel */
 784                 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
 785                                 eptype, max);
 786
 787                 xfer_len = len - done;
 788                 if (xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
 789                         xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE - max + 1;
 790                 if (xfer_len > DWC2_DATA_BUF_SIZE)
 791                         xfer_len = DWC2_DATA_BUF_SIZE - max + 1;
 792
 793                 /* Make sure that xfer_len is a multiple of max packet size. */
 794                 if (xfer_len > 0) {
 795                         num_packets = (xfer_len + max - 1) / max;
 796                         if (num_packets > CONFIG_DWC2_MAX_PACKET_COUNT) {
 797                                 num_packets = CONFIG_DWC2_MAX_PACKET_COUNT;
 798                                 xfer_len = num_packets * max;
 799                         }
 800                 } else {
 801                         num_packets = 1;
 802                 }
 803
 804                 if (in)
 805                         xfer_len = num_packets * max;
 806
 807                 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
 808                       *pid, xfer_len, num_packets);
 809
 810                 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
 811                        (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
 812                        (*pid << DWC2_HCTSIZ_PID_OFFSET),
 813                        &hc_regs->hctsiz);
 814
 815                 if (!in) {
 816                         memcpy(priv->aligned_buffer, (char *)buffer + done,
 817                                len);
 818                 }
 819
 820                 writel(phys_to_bus((unsigned long)priv->aligned_buffer),
 821                        &hc_regs->hcdma);
 822
 823                 /* Set host channel enable after all other setup is complete. */
 824                 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
 825                                 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
 826                                 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
 827                                 DWC2_HCCHAR_CHEN);
 828
 829                 ret = wait_for_chhltd(regs, &sub, pid, ignore_ack);
 830                 if (ret)
 831                         break;
 832
 833                 if (in) {
 834                         xfer_len -= sub;
 835                         memcpy(buffer + done, priv->aligned_buffer, xfer_len);
 836                         if (sub)
 837                                 stop_transfer = 1;
 838                 }
 839
 840                 done += xfer_len;
 841
 842         } while ((done < len) && !stop_transfer);
 843
 844         writel(0, &hc_regs->hcintmsk);
 845         writel(0xFFFFFFFF, &hc_regs->hcint);
 846
 847         dev->status = 0;
 848         dev->act_len = done;
 849
 850         return ret;
 851 }
 852
 853 /* U-Boot USB transmission interface */
 854 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
 855                      unsigned long pipe, void *buffer, int len)
 856 {
 857         int devnum = usb_pipedevice(pipe);
 858         int ep = usb_pipeendpoint(pipe);
 859
 860         if (devnum == priv->root_hub_devnum) {
 861                 dev->status = 0;
 862                 return -EINVAL;
 863         }
 864
 865         return chunk_msg(priv, dev, pipe, &priv->bulk_data_toggle[devnum][ep],
 866                          usb_pipein(pipe), buffer, len, true);
 867 }
 868
 869 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
 870                                unsigned long pipe, void *buffer, int len,
 871                                struct devrequest *setup)
 872 {
 873         int devnum = usb_pipedevice(pipe);
 874         int pid, ret, act_len;
 875         /* For CONTROL endpoint pid should start with DATA1 */
 876         int status_direction;
 877
 878         if (devnum == priv->root_hub_devnum) {
 879                 dev->status = 0;
 880                 dev->speed = USB_SPEED_HIGH;
 881                 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
 882                                              setup);
 883         }
 884
 885         pid = DWC2_HC_PID_SETUP;
 886         ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8, true);
 887         if (ret)
 888                 return ret;
 889
 890         if (buffer) {
 891                 pid = DWC2_HC_PID_DATA1;
 892                 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe), buffer,
 893                                 len, false);
 894                 if (ret)
 895                         return ret;
 896                 act_len = dev->act_len;
 897         } /* End of DATA stage */
 898         else
 899                 act_len = 0;
 900
 901         /* STATUS stage */
 902         if ((len == 0) || usb_pipeout(pipe))
 903                 status_direction = 1;
 904         else
 905                 status_direction = 0;
 906
 907         pid = DWC2_HC_PID_DATA1;
 908         ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
 909                         priv->status_buffer, 0, false);
 910         if (ret)
 911                 return ret;
 912
 913         dev->act_len = act_len;
 914
 915         return 0;
 916 }
 917
 918 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
 919                     unsigned long pipe, void *buffer, int len, int interval)
 920 {
 921         unsigned long timeout;
 922         int ret;
 923
 924         /* FIXME: what is interval? */
 925
 926         timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
 927         for (;;) {
 928                 if (get_timer(0) > timeout) {
 929                         printf("Timeout poll on interrupt endpoint\n");
 930                         return -ETIMEDOUT;
 931                 }
 932                 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
 933                 if (ret != -EAGAIN)
 934                         return ret;
 935         }
 936 }
 937
 938 static int dwc2_init_common(struct dwc2_priv *priv)
 939 {
 940         struct dwc2_core_regs *regs = priv->regs;
 941         uint32_t snpsid;
 942         int i, j;
 943
 944         snpsid = readl(&regs->gsnpsid);
 945         printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
 946
 947         if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
 948             (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
 949                 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
 950                 return -ENODEV;
 951         }
 952
 953         dwc_otg_core_init(regs);
 954         dwc_otg_core_host_init(regs);
 955
 956         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 957                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
 958                         DWC2_HPRT0_PRTOVRCURRCHNG,
 959                         DWC2_HPRT0_PRTRST);
 960         mdelay(50);
 961         clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
 962                      DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
 963                      DWC2_HPRT0_PRTRST);
 964
 965         for (i = 0; i < MAX_DEVICE; i++) {
 966                 for (j = 0; j < MAX_ENDPOINT; j++)
 967                         priv->bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0;
 968         }
 969
 970         return 0;
 971 }
 972
 973 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
 974 {
 975         /* Put everything in reset. */
 976         clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
 977                         DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
 978                         DWC2_HPRT0_PRTOVRCURRCHNG,
 979                         DWC2_HPRT0_PRTRST);
 980 }
 981
 982 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 983                        int len, struct devrequest *setup)
 984 {
 985         return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
 986 }
 987
 988 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 989                     int len)
 990 {
 991         return _submit_bulk_msg(&local, dev, pipe, buffer, len);
 992 }
 993
 994 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 995                    int len, int interval)
 996 {
 997         return _submit_int_msg(&local, dev, pipe, buffer, len, interval);
 998 }
 999
1000 /* U-Boot USB control interface */
1001 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1002 {
1003         struct dwc2_priv *priv = &local;
1004
1005         memset(priv, '\0', sizeof(*priv));
1006         priv->root_hub_devnum = 0;
1007         priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1008         priv->aligned_buffer = aligned_buffer_addr;
1009         priv->status_buffer = status_buffer_addr;
1010
1011         /* board-dependant init */
1012         if (board_usb_init(index, USB_INIT_HOST))
1013                 return -1;
1014
1015         return dwc2_init_common(priv);
1016 }
1017
1018 int usb_lowlevel_stop(int index)
1019 {
1020         dwc2_uninit_common(local.regs);
1021
1022         return 0;
1023 }