2 * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
5 * SPDX-License-Identifier: GPL-2.0+
14 #include <usbroothubdes.h>
19 /* Use only HC channel 0. */
20 #define DWC2_HC_CHANNEL 0
22 #define DWC2_STATUS_BUF_SIZE 64
23 #define DWC2_DATA_BUF_SIZE (64 * 1024)
26 #define MAX_ENDPOINT 16
30 uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(8);
31 uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(8);
33 uint8_t *aligned_buffer;
34 uint8_t *status_buffer;
36 int bulk_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
37 struct dwc2_core_regs *regs;
42 /* We need doubleword-aligned buffers for DMA transfers */
43 DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE, 8);
44 DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE, 8);
46 static struct dwc2_priv local;
52 static int wait_for_bit(void *reg, const uint32_t mask, bool set)
54 unsigned int timeout = 1000000;
62 if ((val & mask) == mask)
68 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
69 __func__, reg, mask, set);
75 * Initializes the FSLSPClkSel field of the HCFG register
76 * depending on the PHY type.
78 static void init_fslspclksel(struct dwc2_core_regs *regs)
82 #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
83 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
85 /* High speed PHY running at full speed or high speed */
86 phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
89 #ifdef CONFIG_DWC2_ULPI_FS_LS
90 uint32_t hwcfg2 = readl(®s->ghwcfg2);
91 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
92 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
93 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
94 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
96 if (hval == 2 && fval == 1)
97 phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
100 clrsetbits_le32(®s->host_regs.hcfg,
101 DWC2_HCFG_FSLSPCLKSEL_MASK,
102 phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
108 * @param regs Programming view of DWC_otg controller.
109 * @param num Tx FIFO to flush.
111 static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
115 writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
117 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_TXFFLSH, 0);
119 printf("%s: Timeout!\n", __func__);
121 /* Wait for 3 PHY Clocks */
128 * @param regs Programming view of DWC_otg controller.
130 static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
134 writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl);
135 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_RXFFLSH, 0);
137 printf("%s: Timeout!\n", __func__);
139 /* Wait for 3 PHY Clocks */
144 * Do core a soft reset of the core. Be careful with this because it
145 * resets all the internal state machines of the core.
147 static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
151 /* Wait for AHB master IDLE state. */
152 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_AHBIDLE, 1);
154 printf("%s: Timeout!\n", __func__);
156 /* Core Soft Reset */
157 writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl);
158 ret = wait_for_bit(®s->grstctl, DWC2_GRSTCTL_CSFTRST, 0);
160 printf("%s: Timeout!\n", __func__);
163 * Wait for core to come out of reset.
164 * NOTE: This long sleep is _very_ important, otherwise the core will
165 * not stay in host mode after a connector ID change!
171 * This function initializes the DWC_otg controller registers for
174 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
175 * request queues. Host channels are reset to ensure that they are ready for
176 * performing transfers.
178 * @param regs Programming view of DWC_otg controller
181 static void dwc_otg_core_host_init(struct dwc2_core_regs *regs)
183 uint32_t nptxfifosize = 0;
184 uint32_t ptxfifosize = 0;
186 int i, ret, num_channels;
188 /* Restart the Phy Clock */
189 writel(0, ®s->pcgcctl);
191 /* Initialize Host Configuration Register */
192 init_fslspclksel(regs);
193 #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
194 setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
197 /* Configure data FIFO sizes */
198 #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
199 if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
201 writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz);
203 /* Non-periodic Tx FIFO */
204 nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
205 DWC2_FIFOSIZE_DEPTH_OFFSET;
206 nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
207 DWC2_FIFOSIZE_STARTADDR_OFFSET;
208 writel(nptxfifosize, ®s->gnptxfsiz);
210 /* Periodic Tx FIFO */
211 ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
212 DWC2_FIFOSIZE_DEPTH_OFFSET;
213 ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
214 CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
215 DWC2_FIFOSIZE_STARTADDR_OFFSET;
216 writel(ptxfifosize, ®s->hptxfsiz);
220 /* Clear Host Set HNP Enable in the OTG Control Register */
221 clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
223 /* Make sure the FIFOs are flushed. */
224 dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
225 dwc_otg_flush_rx_fifo(regs);
227 /* Flush out any leftover queued requests. */
228 num_channels = readl(®s->ghwcfg2);
229 num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
230 num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
233 for (i = 0; i < num_channels; i++)
234 clrsetbits_le32(®s->hc_regs[i].hcchar,
235 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
238 /* Halt all channels to put them into a known state. */
239 for (i = 0; i < num_channels; i++) {
240 clrsetbits_le32(®s->hc_regs[i].hcchar,
242 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
243 ret = wait_for_bit(®s->hc_regs[i].hcchar,
244 DWC2_HCCHAR_CHEN, 0);
246 printf("%s: Timeout!\n", __func__);
249 /* Turn on the vbus power. */
250 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
251 hprt0 = readl(®s->hprt0);
252 hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
253 hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
254 if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
255 hprt0 |= DWC2_HPRT0_PRTPWR;
256 writel(hprt0, ®s->hprt0);
262 * This function initializes the DWC_otg controller registers and
263 * prepares the core for device mode or host mode operation.
265 * @param regs Programming view of the DWC_otg controller
267 static void dwc_otg_core_init(struct dwc2_core_regs *regs)
271 uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
273 /* Common Initialization */
274 usbcfg = readl(®s->gusbcfg);
276 /* Program the ULPI External VBUS bit if needed */
277 #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
278 usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
280 usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
283 /* Set external TS Dline pulsing */
284 #ifdef CONFIG_DWC2_TS_DLINE
285 usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
287 usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
289 writel(usbcfg, ®s->gusbcfg);
291 /* Reset the Controller */
292 dwc_otg_core_reset(regs);
295 * This programming sequence needs to happen in FS mode before
296 * any other programming occurs
298 #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
299 (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
300 /* If FS mode with FS PHY */
301 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL);
303 /* Reset after a PHY select */
304 dwc_otg_core_reset(regs);
307 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
308 * Also do this on HNP Dev/Host mode switches (done in dev_init
311 if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
312 init_fslspclksel(regs);
314 #ifdef CONFIG_DWC2_I2C_ENABLE
315 /* Program GUSBCFG.OtgUtmifsSel to I2C */
316 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
318 /* Program GI2CCTL.I2CEn */
319 clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN |
320 DWC2_GI2CCTL_I2CDEVADDR_MASK,
321 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
322 setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN);
326 /* High speed PHY. */
329 * HS PHY parameters. These parameters are preserved during
330 * soft reset so only program the first time. Do a soft reset
331 * immediately after setting phyif.
333 usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
334 usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
336 if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
337 #ifdef CONFIG_DWC2_PHY_ULPI_DDR
338 usbcfg |= DWC2_GUSBCFG_DDRSEL;
340 usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
342 } else { /* UTMI+ interface */
343 #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16)
344 usbcfg |= DWC2_GUSBCFG_PHYIF;
348 writel(usbcfg, ®s->gusbcfg);
350 /* Reset after setting the PHY parameters */
351 dwc_otg_core_reset(regs);
354 usbcfg = readl(®s->gusbcfg);
355 usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
356 #ifdef CONFIG_DWC2_ULPI_FS_LS
357 uint32_t hwcfg2 = readl(®s->ghwcfg2);
358 uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
359 DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
360 uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
361 DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
362 if (hval == 2 && fval == 1) {
363 usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
364 usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
367 writel(usbcfg, ®s->gusbcfg);
369 /* Program the GAHBCFG Register. */
370 switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
371 case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
373 case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
374 while (brst_sz > 1) {
375 ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
376 ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
380 #ifdef CONFIG_DWC2_DMA_ENABLE
381 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
385 case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
386 ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
387 #ifdef CONFIG_DWC2_DMA_ENABLE
388 ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
393 writel(ahbcfg, ®s->gahbcfg);
395 /* Program the GUSBCFG register for HNP/SRP. */
396 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP);
398 #ifdef CONFIG_DWC2_IC_USB_CAP
399 setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP);
404 * Prepares a host channel for transferring packets to/from a specific
405 * endpoint. The HCCHARn register is set up with the characteristics specified
406 * in _hc. Host channel interrupts that may need to be serviced while this
407 * transfer is in progress are enabled.
409 * @param regs Programming view of DWC_otg controller
410 * @param hc Information needed to initialize the host channel
412 static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
413 struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
414 uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
416 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num];
417 uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
418 (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
419 (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
420 (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
421 (max_packet << DWC2_HCCHAR_MPS_OFFSET);
423 if (dev->speed == USB_SPEED_LOW)
424 hcchar |= DWC2_HCCHAR_LSPDDEV;
426 /* Clear old interrupt conditions for this host channel. */
427 writel(0x3fff, &hc_regs->hcint);
430 * Program the HCCHARn register with the endpoint characteristics
431 * for the current transfer.
433 writel(hcchar, &hc_regs->hcchar);
435 /* Program the HCSPLIT register for SPLITs */
436 writel(0, &hc_regs->hcsplt);
440 * DWC2 to USB API interface
442 /* Direction: In ; Request: Status */
443 static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
444 struct usb_device *dev, void *buffer,
445 int txlen, struct devrequest *cmd)
448 uint32_t port_status = 0;
449 uint32_t port_change = 0;
453 switch (cmd->requesttype & ~USB_DIR_IN) {
455 *(uint16_t *)buffer = cpu_to_le16(1);
458 case USB_RECIP_INTERFACE:
459 case USB_RECIP_ENDPOINT:
460 *(uint16_t *)buffer = cpu_to_le16(0);
464 *(uint32_t *)buffer = cpu_to_le32(0);
467 case USB_RECIP_OTHER | USB_TYPE_CLASS:
468 hprt0 = readl(®s->hprt0);
469 if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
470 port_status |= USB_PORT_STAT_CONNECTION;
471 if (hprt0 & DWC2_HPRT0_PRTENA)
472 port_status |= USB_PORT_STAT_ENABLE;
473 if (hprt0 & DWC2_HPRT0_PRTSUSP)
474 port_status |= USB_PORT_STAT_SUSPEND;
475 if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
476 port_status |= USB_PORT_STAT_OVERCURRENT;
477 if (hprt0 & DWC2_HPRT0_PRTRST)
478 port_status |= USB_PORT_STAT_RESET;
479 if (hprt0 & DWC2_HPRT0_PRTPWR)
480 port_status |= USB_PORT_STAT_POWER;
482 if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
483 port_status |= USB_PORT_STAT_LOW_SPEED;
484 else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
485 DWC2_HPRT0_PRTSPD_HIGH)
486 port_status |= USB_PORT_STAT_HIGH_SPEED;
488 if (hprt0 & DWC2_HPRT0_PRTENCHNG)
489 port_change |= USB_PORT_STAT_C_ENABLE;
490 if (hprt0 & DWC2_HPRT0_PRTCONNDET)
491 port_change |= USB_PORT_STAT_C_CONNECTION;
492 if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
493 port_change |= USB_PORT_STAT_C_OVERCURRENT;
495 *(uint32_t *)buffer = cpu_to_le32(port_status |
496 (port_change << 16));
500 puts("unsupported root hub command\n");
501 stat = USB_ST_STALLED;
504 dev->act_len = min(len, txlen);
510 /* Direction: In ; Request: Descriptor */
511 static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
512 void *buffer, int txlen,
513 struct devrequest *cmd)
515 unsigned char data[32];
519 uint16_t wValue = cpu_to_le16(cmd->value);
520 uint16_t wLength = cpu_to_le16(cmd->length);
522 switch (cmd->requesttype & ~USB_DIR_IN) {
524 switch (wValue & 0xff00) {
525 case 0x0100: /* device descriptor */
526 len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
527 memcpy(buffer, root_hub_dev_des, len);
529 case 0x0200: /* configuration descriptor */
530 len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
531 memcpy(buffer, root_hub_config_des, len);
533 case 0x0300: /* string descriptors */
534 switch (wValue & 0xff) {
536 len = min3(txlen, (int)sizeof(root_hub_str_index0),
538 memcpy(buffer, root_hub_str_index0, len);
541 len = min3(txlen, (int)sizeof(root_hub_str_index1),
543 memcpy(buffer, root_hub_str_index1, len);
548 stat = USB_ST_STALLED;
553 /* Root port config, set 1 port and nothing else. */
556 data[0] = 9; /* min length; */
558 data[2] = dsc & RH_A_NDP;
564 else if (dsc & RH_A_OCPM)
567 /* corresponds to data[4-7] */
568 data[5] = (dsc & RH_A_POTPGT) >> 24;
569 data[7] = dsc & RH_B_DR;
574 data[8] = (dsc & RH_B_DR) >> 8;
579 len = min3(txlen, (int)data[0], (int)wLength);
580 memcpy(buffer, data, len);
583 puts("unsupported root hub command\n");
584 stat = USB_ST_STALLED;
587 dev->act_len = min(len, txlen);
593 /* Direction: In ; Request: Configuration */
594 static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
595 void *buffer, int txlen,
596 struct devrequest *cmd)
601 switch (cmd->requesttype & ~USB_DIR_IN) {
603 *(uint8_t *)buffer = 0x01;
607 puts("unsupported root hub command\n");
608 stat = USB_ST_STALLED;
611 dev->act_len = min(len, txlen);
618 static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
619 struct usb_device *dev, void *buffer,
620 int txlen, struct devrequest *cmd)
622 switch (cmd->request) {
623 case USB_REQ_GET_STATUS:
624 return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
626 case USB_REQ_GET_DESCRIPTOR:
627 return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
629 case USB_REQ_GET_CONFIGURATION:
630 return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
633 puts("unsupported root hub command\n");
634 return USB_ST_STALLED;
639 static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
640 struct usb_device *dev,
641 void *buffer, int txlen,
642 struct devrequest *cmd)
644 struct dwc2_core_regs *regs = priv->regs;
647 uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
648 uint16_t wValue = cpu_to_le16(cmd->value);
650 switch (bmrtype_breq & ~USB_DIR_IN) {
651 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
652 case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
655 case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
657 case USB_PORT_FEAT_C_CONNECTION:
658 setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET);
663 case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
665 case USB_PORT_FEAT_SUSPEND:
668 case USB_PORT_FEAT_RESET:
669 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
670 DWC2_HPRT0_PRTCONNDET |
671 DWC2_HPRT0_PRTENCHNG |
672 DWC2_HPRT0_PRTOVRCURRCHNG,
675 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST);
678 case USB_PORT_FEAT_POWER:
679 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
680 DWC2_HPRT0_PRTCONNDET |
681 DWC2_HPRT0_PRTENCHNG |
682 DWC2_HPRT0_PRTOVRCURRCHNG,
686 case USB_PORT_FEAT_ENABLE:
690 case (USB_REQ_SET_ADDRESS << 8):
691 priv->root_hub_devnum = wValue;
693 case (USB_REQ_SET_CONFIGURATION << 8):
696 puts("unsupported root hub command\n");
697 stat = USB_ST_STALLED;
700 len = min(len, txlen);
708 static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
709 unsigned long pipe, void *buffer, int txlen,
710 struct devrequest *cmd)
714 if (usb_pipeint(pipe)) {
715 puts("Root-Hub submit IRQ: NOT implemented\n");
719 if (cmd->requesttype & USB_DIR_IN)
720 stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
722 stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
729 int wait_for_chhltd(struct dwc2_core_regs *regs, uint32_t *sub, int *toggle,
732 uint32_t hcint_comp_hlt_ack = DWC2_HCINT_XFERCOMP | DWC2_HCINT_CHHLTD;
733 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
735 uint32_t hcint, hctsiz;
737 ret = wait_for_bit(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true);
741 hcint = readl(&hc_regs->hcint);
742 if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
745 hcint &= ~DWC2_HCINT_ACK;
747 hcint_comp_hlt_ack |= DWC2_HCINT_ACK;
748 if (hcint != hcint_comp_hlt_ack) {
749 debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
753 hctsiz = readl(&hc_regs->hctsiz);
754 *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
755 DWC2_HCTSIZ_XFERSIZE_OFFSET;
756 *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
758 debug("%s: sub=%u toggle=%d\n", __func__, *sub, *toggle);
763 static int dwc2_eptype[] = {
764 DWC2_HCCHAR_EPTYPE_ISOC,
765 DWC2_HCCHAR_EPTYPE_INTR,
766 DWC2_HCCHAR_EPTYPE_CONTROL,
767 DWC2_HCCHAR_EPTYPE_BULK,
770 int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
771 unsigned long pipe, int *pid, int in, void *buffer, int len,
774 struct dwc2_core_regs *regs = priv->regs;
775 struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL];
776 int devnum = usb_pipedevice(pipe);
777 int ep = usb_pipeendpoint(pipe);
778 int max = usb_maxpacket(dev, pipe);
779 int eptype = dwc2_eptype[usb_pipetype(pipe)];
784 uint32_t num_packets;
785 int stop_transfer = 0;
787 debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
791 /* Initialize channel */
792 dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
795 xfer_len = len - done;
796 if (xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
797 xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE - max + 1;
798 if (xfer_len > DWC2_DATA_BUF_SIZE)
799 xfer_len = DWC2_DATA_BUF_SIZE - max + 1;
801 /* Make sure that xfer_len is a multiple of max packet size. */
803 num_packets = (xfer_len + max - 1) / max;
804 if (num_packets > CONFIG_DWC2_MAX_PACKET_COUNT) {
805 num_packets = CONFIG_DWC2_MAX_PACKET_COUNT;
806 xfer_len = num_packets * max;
813 xfer_len = num_packets * max;
815 debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
816 *pid, xfer_len, num_packets);
818 writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
819 (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
820 (*pid << DWC2_HCTSIZ_PID_OFFSET),
824 memcpy(priv->aligned_buffer, (char *)buffer + done,
828 writel(phys_to_bus((unsigned long)priv->aligned_buffer),
831 /* Set host channel enable after all other setup is complete. */
832 clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
833 DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS,
834 (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
837 ret = wait_for_chhltd(regs, &sub, pid, ignore_ack);
843 memcpy(buffer + done, priv->aligned_buffer, xfer_len);
850 } while ((done < len) && !stop_transfer);
852 writel(0, &hc_regs->hcintmsk);
853 writel(0xFFFFFFFF, &hc_regs->hcint);
861 /* U-Boot USB transmission interface */
862 int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
863 unsigned long pipe, void *buffer, int len)
865 int devnum = usb_pipedevice(pipe);
866 int ep = usb_pipeendpoint(pipe);
868 if (devnum == priv->root_hub_devnum) {
873 return chunk_msg(priv, dev, pipe, &priv->bulk_data_toggle[devnum][ep],
874 usb_pipein(pipe), buffer, len, true);
877 static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
878 unsigned long pipe, void *buffer, int len,
879 struct devrequest *setup)
881 int devnum = usb_pipedevice(pipe);
882 int pid, ret, act_len;
883 /* For CONTROL endpoint pid should start with DATA1 */
884 int status_direction;
886 if (devnum == priv->root_hub_devnum) {
888 dev->speed = USB_SPEED_HIGH;
889 return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
893 pid = DWC2_HC_PID_SETUP;
894 ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8, true);
899 pid = DWC2_HC_PID_DATA1;
900 ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe), buffer,
904 act_len = dev->act_len;
905 } /* End of DATA stage */
910 if ((len == 0) || usb_pipeout(pipe))
911 status_direction = 1;
913 status_direction = 0;
915 pid = DWC2_HC_PID_DATA1;
916 ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
917 priv->status_buffer, 0, false);
921 dev->act_len = act_len;
926 int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
927 unsigned long pipe, void *buffer, int len, int interval)
929 unsigned long timeout;
932 /* FIXME: what is interval? */
934 timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
936 if (get_timer(0) > timeout) {
937 printf("Timeout poll on interrupt endpoint\n");
940 ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
946 static int dwc2_init_common(struct dwc2_priv *priv)
948 struct dwc2_core_regs *regs = priv->regs;
952 snpsid = readl(®s->gsnpsid);
953 printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff);
955 if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
956 (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
957 printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid);
961 dwc_otg_core_init(regs);
962 dwc_otg_core_host_init(regs);
964 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
965 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
966 DWC2_HPRT0_PRTOVRCURRCHNG,
969 clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
970 DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
973 for (i = 0; i < MAX_DEVICE; i++) {
974 for (j = 0; j < MAX_ENDPOINT; j++)
975 priv->bulk_data_toggle[i][j] = DWC2_HC_PID_DATA0;
981 static void dwc2_uninit_common(struct dwc2_core_regs *regs)
983 /* Put everything in reset. */
984 clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA |
985 DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
986 DWC2_HPRT0_PRTOVRCURRCHNG,
990 #ifndef CONFIG_DM_USB
991 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
992 int len, struct devrequest *setup)
994 return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
997 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1000 return _submit_bulk_msg(&local, dev, pipe, buffer, len);
1003 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1004 int len, int interval)
1006 return _submit_int_msg(&local, dev, pipe, buffer, len, interval);
1009 /* U-Boot USB control interface */
1010 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1012 struct dwc2_priv *priv = &local;
1014 memset(priv, '\0', sizeof(*priv));
1015 priv->root_hub_devnum = 0;
1016 priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
1017 priv->aligned_buffer = aligned_buffer_addr;
1018 priv->status_buffer = status_buffer_addr;
1020 /* board-dependant init */
1021 if (board_usb_init(index, USB_INIT_HOST))
1024 return dwc2_init_common(priv);
1027 int usb_lowlevel_stop(int index)
1029 dwc2_uninit_common(local.regs);
1035 #ifdef CONFIG_DM_USB
1036 static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
1037 unsigned long pipe, void *buffer, int length,
1038 struct devrequest *setup)
1040 struct dwc2_priv *priv = dev_get_priv(dev);
1042 debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
1043 dev->name, udev, udev->dev->name, udev->portnr);
1045 return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
1048 static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
1049 unsigned long pipe, void *buffer, int length)
1051 struct dwc2_priv *priv = dev_get_priv(dev);
1053 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1055 return _submit_bulk_msg(priv, udev, pipe, buffer, length);
1058 static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
1059 unsigned long pipe, void *buffer, int length,
1062 struct dwc2_priv *priv = dev_get_priv(dev);
1064 debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
1066 return _submit_int_msg(priv, udev, pipe, buffer, length, interval);
1069 static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
1071 struct dwc2_priv *priv = dev_get_priv(dev);
1074 addr = dev_get_addr(dev);
1075 if (addr == FDT_ADDR_T_NONE)
1077 priv->regs = (struct dwc2_core_regs *)addr;
1082 static int dwc2_usb_probe(struct udevice *dev)
1084 struct dwc2_priv *priv = dev_get_priv(dev);
1086 return dwc2_init_common(priv);
1089 static int dwc2_usb_remove(struct udevice *dev)
1091 struct dwc2_priv *priv = dev_get_priv(dev);
1093 dwc2_uninit_common(priv->regs);
1098 struct dm_usb_ops dwc2_usb_ops = {
1099 .control = dwc2_submit_control_msg,
1100 .bulk = dwc2_submit_bulk_msg,
1101 .interrupt = dwc2_submit_int_msg,
1104 static const struct udevice_id dwc2_usb_ids[] = {
1105 { .compatible = "brcm,bcm2835-usb" },
1109 U_BOOT_DRIVER(usb_dwc2) = {
1110 .name = "dwc2_exynos",
1112 .of_match = dwc2_usb_ids,
1113 .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
1114 .probe = dwc2_usb_probe,
1115 .remove = dwc2_usb_remove,
1116 .ops = &dwc2_usb_ops,
1117 .priv_auto_alloc_size = sizeof(struct dwc2_priv),
1118 .flags = DM_FLAG_ALLOC_PRIV_DMA,